Status Register

• Status = system byte (supervisor only) + user byte

= system status + condition code register
• usually, it is not important to know the order of the bits in this
register

Fig 2-4 from M68000 8-/16-/32-Bit Microprocessors User’s Manual [pdf, 184p; Motorola]
Status Register … system byte

T - trace e.g. STOP #$2700

= 1 in trace mode
= 0 otherwise  If supervisor state
> single step instruction trace then
[SR] ← <#data>
S - supervisor STOP
= 1 in supervisor mode else
= 0 in user mode privilege violation

I2I1I0 - interrupt mask

= coded interrupt level
Status Register … condition codes
N - negative
= 1 if the most significant bit of an operand or result is 1

Z - zero
= 1 if all bits in the operand or result are 0

V - overflow
= 1 if an out-of-range condition, i.e. overflow, occurs in
signed arithmetic

C - carry
= 1 if a carry is generated out of the most significant bit
during an arithmetic operation; if borrow generated during
subtract – indicates an overflow in unsigned arithmetic

X - extend (extended carry)

- used in multiple precision arithmetic (typically mirrors C,
the carry)
Condition Code Notation
Condition code register representation in reference
manuals follow a standard convention:

* Set according to the result of the operation.

- Not affected by the operation; contents of the bit are not
changed.
0 Cleared, i.e. bit set to 0.
1 Set, i.e. bit set to 1.
U Undefined or unpredictable after the operation.
? Unstable (Intel – does not apply to us)

e.g. AND X N Z V C LSL XNZVC

- **0 0 ** *0*
Binary Arithmetic + CCR
e.g. 0011 1010
+1110 0000

C=X=
N=
Z=
V=
Binary Arithmetic + CCR
e.g. 0011 1010
-1110 0000

C=X=
N=
Z=
V=
Binary Arithmetic + CCR
e.g. 0110 1010
+0100 0000

C=X=
N=
Z=
V=
Using the Condition Codes
 the machine does 2’s complement
arithmetic
 the machine generates ALL the flags
 the machine does not know if you are
doing signed or unsigned operations
 you pick which flags are appropriate to
your operation
A language
is like a bar
Python bar
.
.
C bar
.
.
Assembly language bar
Valid flags for unsigned arithmetic
Carry
e.g. A – B
= 1 → result incorrect
→ can not be stored if C=0 A B
→ unsigned overflow if C=1 A B
= 0 → result correct

Zero if C=0 and Z=0 A B

= 1 → result is zero if C=1 or Z=1 A B
= 0 → result is not zero
Conditional Branch … Bcc
 M68000 Assembly Language [p16, N. Znotinas]
 conditional branches
 come in pairs to test complementary cases
e.g. equal to zero or not equal to zero
 syntax: Bcc label

 for unsigned arithmetic:

BHI | BLS Br high |Br low or same
BCC | BCS Br C clear |Br C set
BHS*| BLO* Br high/same |Br low
BNE | BEQ Br not equal |Br equal

* depends on IDE if synonym accepted

Loops … counting loops
 simple counting loops  in assembly language
count down to zero

 before loop: initialize count

register to maximum count
 in loop: decrement count
register
 at end of loop: test if count
is zero
 if count not zero: branch to
the start of the loop
 if count is zero: drop
through to next instruction
Write a program to calculate x**y, given x and y.
Reading/Expectations:
 Reading:
 M68000 8-/16-/32-Bit Microprocessors User’s Manual -
section: 2.1.3 Status Register
 M68000 Assembly Language [pdf, 92p; N. Znotinas]
 Look at the condition codes for the MOVE, ADD, AND,
ASR/L, CLR, EOR, LSR/L, MULS, MULU, NOT, OR, SUB
commands.
 Focusing on N, V, Z, and C for the above instructions, do
you understand why some flags are cleared, some are set,
and some depend on the operation of the instruction
 Note that instructions that work specifically on addresses
do not modify the flags (with one exception not shown
here). See: ADDA, MOVEA, SUBA.
 Expectations:
 You can determine the state of the C, Z, N, and V condition
code bits for any operation.