RISC-V Lab Project PDF

Embedded Systems Lab
Lab Manual
Authors: Mr. Umer Shahid

Miss. Shehzeen Malik
Name:
Registration Number:
Section:
Department of Electrical Engineering

University of Engineering and Technology Lahore
Contents
Instructions ii
A Experiment 1
1 Implementation of SPI Protocol using verilog on Nexys A7 . . . . . . . . 2
B Lab Project 12
1 Multi Cycle RISC-V Processor Design - 32bit version . . . . . . . . . . . 13
i
Important Instructions
• Read out the Manual very carefully
ii
Part A
Experiment
1
Experiment 1 2
Experiment No. 1
Implementation of SPI Protocol using verilog on
Nexys A7
Section 1.1: Objectives

Understanding the SPI protocol for communicating with the memory.
Introduction to SPI Protocol

SPI is the acronym of Serial Peripheral Interface. SD card modules and card reader
modules use SPI to communicate with microcontrollers. Devices communicating via SPI
are in a master-slave relationship, with the microcontroller being the master and the
memory card being the slave. There can only be one master but multiple slaves (but in
our case flash memory is the only slave).
Following lines are used for communication
1. MOSI Master Output Slave Input line is used for sending data from the master
to the slave. MSB is sent first.
2. MISO Master Input Slave Output line is used for sending data to the master from
the slave. LSB is sent first.
3. SCLK This is a serial clock signal that is transmitted by the bus master to the
slave device(s)
4. SS Slave Select line is for master to choose between different slaves to send the
data.
The SPI bus connections, for point to point communication between master and single
slave device are shown in Figure 1.1. In case of multiple devices, a separate slave select
(SS) signal is used by the bus master, to enable the desired slave device.
Figure 1.1: SPI Master Connected with SPI slave
Embedded Systems Lab, EED, UET, Lahore

Experiment 1 3
SPI Signal Sequence

Due to single bus master protocol followed by the SPI interface, all the bus communi-
cations with the slave devices are initiated by the master device. When the SPI master
intends to send/receive data to/from a slave device, it pulls the corresponding SS line
low. This is followed by the activation of the clock signal at the desired frequency. The
master transmits data using MOSI line, while the incoming data from the selected slave
is received by sampling MISO line. The timing diagram for SPI communication is shown
in Figure 1.2.
Figure 1.2: SPI Timing Diagram
Section 1.2: Experiment Procedure

The guide for creating a project in vivado is as follows:
1.2.1 Creating a Project in Vivado 2019.1
1. Select the Create Project in the welcome dialog. (Figure 1.3) Then click Next when
the next window pops up.
Figure 1.3: Welcome Dialog
2. Name your project and choose its location. Then click Next to continue.
3. In the New Project dialog choose RTL Project and check the Do not specify sources
at the time box. Click Next to continue. (Figure 1.4)

Experiment 1 4
Figure 1.4: Choosing New Project
4. In the next window select the Boards tab and it will display a list of boards. Select
your board Nexys A7 100T Click Next to Continue.(Figure 1.5)
Figure 1.5: Choosing Board
5. Click Finish in the New Project Summary dialog. (Figure 1.6)
Figure 1.6: Project Summary

Experiment 1 5
6. In the Project Manager, under the Sources tab, right click on Design Sources and
choose Add Sources. (Figure 1.7)
Figure 1.7: Project Manager
7. In the window that pops up, select Add or create design sources, then click Next to
continue.
8. In the Add Sources dialog, clickCreate File.
9. You will be prompted to select a File type, File name, and File location. Make sure
to pick Verilog and Local to project for the type and location. Give your file a name
ending in .v. (Figure 1.8)
Figure 1.8: Naming Source File
10. In the Define Module dialog that appears, you can define your inputs and outputs
if you want. Otherwise they will be defined in the Verilog file.
11. Open the file from design sources and write your code.

Experiment 1 6
12. If you are adding the file directly to your project, make sure to check Copy sources
into project. (Figure 1.9)
Figure 1.9: Adding Source File
1.2.2 Simulating SPI Master in verilog
1. Create a new source file with the name SPI master.v.
2. Copy the code of file SPI master.v (given with the manual) and synthesize it.
3. In the window that pops up, select Add or create simulation sources, then click Next
to continue.
4. Create a new source file with the name SPI master tb.v.
5. Copy the code of file SPI master tb.v (given with the manual) and synthesize it.
6. Right Click on SPI master tb.v in Source section, and make it top module.
7. Go to simulation tap, and make SPI master tb.v top module using the step men-
tioned in 5.
8. Select Run Behavioral Simulation by clicking the Run Simulation in Flow Navigator.
9. Remember to Choose Full view to observe simulation.
Figure 1.10: Full view

Experiment 1 7
10. Observe the simulated waveform and compare it with the timing diagram of shown
above.
1.2.3 Simulating SPI Slave in verilog
1. Create a new source file with the name SPI slave.v.
2. Copy the code of file SPI slave.v (given with the manual) and synthesize it.
3. Create a new source file with the name SPI slave tb.v.
4. Copy the code of file SPI slave tb.v (given with the manual) and synthesize it.
5. Right Click on SPI slave tb.v in Source section, and make it top module.
6. Go to simulation tap, and make SPI slave tb.v top module using the step men-
tioned in 5.
above.
1.2.4 Simulating SPI Master and SPI Slave
1. Create a new source file with the name main code.v.
2. Copy the code of file main code tb.v (given with the manual) and synthesize it.
3. Right Click on main code tb.v in Source section, and make it top module.
4. Go to simulation tap, and make main code tb.v top module using the step men-
tioned in 5.
above.
6. Close the project and if you want also exit Vivado.
1.2.5 Final Implementation
1. Create a new project for hardware implementation as shown in section 1.2.1 Creating
a Project in Vivado 2019.2.
2. Add the three source file with the name main code.v, SPI master.v and SPI slave.v
provided to you with the manual.
3. Right Click on main code.v in Source section, and make it top module.

Experiment 1 8
Figure 1.11: Opening Eleborate Design
4. In the Flow navigator, click Open Elaborated Design in the RTL Analysis. (Figure
1.11)
5. Open theI/O ports tab and assign your input output pin connections under Pack-
age Pin according to the given table 1.1 or you may refer Nexys A7 Reference
Manual (attached with the manual).
6. In the I/O Std choose your required voltage level (Figure 1.12) then press ctrl S
and save the XDC file by name of your choice.
Figure 1.12: Assigning Input Output

Experiment 1 9
7. Run synthesis and click OK in the pop up appeared.
8. Click Run Implementation under Implementation in the Flow Navigator.
9. Click Generate BitStream under Program and Debug in the Flow Navigator.
Figure 1.13: Synthesis, Implementation, Generate BitStream
10. You can view your Schematic Design under Synthesis. (Figure 1.11)
Figure 1.14: Schematic Design
11. Connect your FPGA Board to your computer using USB port.
12. Open the Hardware Manager under Program and Debug in the Flow Navigator or
from the pop up that appeared at the finish of generating BitStream.
13. From the dropdown that opens, select Open Target.
14. Choose AutoConnect.

Experiment 1 10
Figure 1.15: Connect Hardware
15. Now its time to program the bit file into your hardware. In the dropdown of
theHardware Manager, click Program Device and choose the device (xc..) to pro-
gram.
16. The Bitstream File field should be automatically filled in with the bit file generated
earlier. If not, click the button at the right end of the field and navigate to
< P rojectDirectory > / < P rojectN ame > .runs/impl 1/
and select the bit file and click Program.
Figure 1.16: Hardware Manager
17. Your code is loaded to your FPGA. Pressing buttons or as your code chose it should
have your output displayed on your FPGA.

Experiment 1 11
Table 1.1: Pin Configuration
Input/Output Name Pin Assigned Comments

Anode Activate[7] U13 Output to be connected to AN7
Anode Activate[6] K2 Output to be connected to AN6
Anode Activate[5] T14 Output to be connected to AN5
Anode Activate[4] P14 Output to be connected to AN4
Anode Activate[3] J14 Output to be connected to AN3
Anode Activate[2] T9 Output to be connected to AN2
LED out[6] T10 Output to Segment A
LED out[5] R10 Output to Segment B
LED out[4] K16 Output to Segment C
LED out[3] K13 Output to Segment D
LED out[2] P15 Output to Segment E
LED out[1] T11 Output to Segment F
LED out[0] L18 Output to Segment G
data led[7] H17 Output to LED 7
data led[6] K15 Output to LED 6
data led[5] J13 Output to LED 5
data led[4] N14 Output to LED 4
data led[3] R18 Output to LED 3
data led[2] V17 Output to LED 2
data led[1] U17 Output to LED 1
data led[0] U16 Output to LED 0
indicator[3] M16 RGB-GREEN Led Status Output
indicator[2] R11 RGB-GREEN Led Status Output
indicator[1] N15 RGB-RED Led Status Output
indicator[0] N16 RGB-RED Led Status Output
data[7] R15 Switch to get Input
data[5] T18 Switch to get Input
data[4] U18 Switch to get Input
data[2] H6 Switch to get Input
data[1] T13 Switch to get Input
clk fpga E3 System Clock
write signal L16 Switch to control write operation
read signal M13 Switch to control read operation
slave sel J15 Switch to select slave device

Part B
Lab Project
12
Lab Project 13
Experiment No. 1
Multi Cycle RISC-V Processor Design - 32bit version
Pre-Project Reading
• Chapter 4 and Appendix A of ”Computer Organization and Design - The Hard-

ware/Software Interface RISC-V Edition” by David A. Patterson and John L. Hen-
nessy.
• CSCE-513 Computer Architecture (Contents of Lecture 7-10)
• Resources for CS152: Computer Architecture and Engineering Spring 2016 - UC

Berkeley Resources
All the reference material is available in the google link here and resources here.
Objectives
• Studying, Designing, Implementing, and testing a 32-bit multi cycle RISC-V Pro-
cessor using Verilog.
• Familiarizing with multi cycle architecture design steps of defining an instruction,

fetching, decoding and executing it, and writing results back in memory.
Tools
• Nexys A7 100T FPGA Board
• Xilinx Vivado 2019.2
Section 1.1: Deliverables

Implement a very simple processor that supports a subset of the RISC-V ISA. The pro-
cessor does not support all RISC-V ISA instruction, so it cannot execute most programs.
However, the processor has most parts that a real processor has: A fetch unit, decode
logic, functional units, a register file, I/O support and access to memory. You will be
implementing the datapath while designing a multi cycle RISC-V processor which will
work with five stages mainly,
1. Intruction Fetch
2. Operand Fetch

Lab Project 14
3. Execution
4. Memory Access
5. Write back the result
It must contain a file that will be used as Random Access Memory. Memory is 8-bits
wide but the processor accesses 32-bits (4B) for operation. It has 32 Registers working
as General purpose Register. While one special purpose register (Program Counter) will
be used to hold the address of the instruction. Each Register must be 32 bit wide and
clock edge triggered. It must be designed for a total of 15 Instructions, out of which 6 are
Arithmetic instructions, 3 are logical instructions, 2 are shift instructions, and remaining
are branch, load-store instruction. These instructions include
1. Add Instruction to add contents of two registers and store in 3rd register (add
Rd, Rm, Rn ; Rd = Rm + Rn)
2. Subtract Instruction to subtract contents of two registers and store in 3rd register
(sub Rd, Rm, Rn ; Rd = Rm − Rn)
3. Add Immediate Instruction to add 12bit immediate value and content of one
registers and store in destination register (add Rd, Rm, #immed ;
Rd = Rm + immed)
4. Multiply Instruction to multiply contents of two registers and store in 3rd register
(mul Rd, Rm, Rn ; Rd = Rm ∗ Rn)
5. Divide Instruction to divide contents of two registers and store in 3rd register
(div Rd, Rm, Rn ; Rd = Rm/Rn)
6. Remainder Instruction to get reminder of contents of two registers and store in

3rd register (rem Rd, Rm, Rn ; Rd = Rm%Rn)
7. Shift Left Logical Instruction to shift left the contents of 1st register Rn times
and store the results in destination register (sll Rd, Rm, Rn ; Rd = Rm << Rn)
8. Shift Right Logical Instruction to shift right the contents of 1st register Rn
times and store the results in destination register (srl Rd, Rm, Rn ; Rd = Rm >>
Rn)
9. AND Instruction to take logical AND of the contents of two registers and store
in 3rd register (and Rd, Rm, Rn ; Rd = Rm&Rn)
10. OR Instruction to take logical OR of the contents of two registers and store in
3rd register (or Rd, Rm, Rn ; Rd = Rm|Rn)

Lab Project 15
11. XOR Instruction to take logical XOR of the contents of two registers and store
in 3rd register (xor Rd, Rm, Rn ; Rd = Rm XOR Rn)
12. Load Word Instruction to load the contents from the memory and store it in
destination register. It will contain the 3rd operand as offset value (lw Rd, Rm,
offset)
13. Store Word Instruction to store the contents of a register inside the memory at
the address provided by the 3rd operand. (sw Rm, Rd, offset)
14. Branch Equal Instruction to jump to the any provided address if the given
operands are equal (beq Rn, Rm, label ; Jump to label if Rn==Rm)
15. Branch Not Equal Instruction to jump to the any provided address if the given
operands are not equal (bne Rn, Rm, label ; Jump to label if Rn !=Rm)
Section 1.2: Diagrams and Tables

All the neccessary details related to datapath, controller, and instruction format is at-
tached for the help. The details can be read from the provided reference material here.
Instruction Formats
Instruction Format for four different classes (arithmatic R-type, Immediate or load I-
Type, Store S-type, and conditional branch SB-Type) is shown in Figure 1. Instruction
format for R-type arithmetic instructions, which have three register operands: rs1, rs2,
and rd. Fields rs1 and rd are sources, and rd is the destination. The ALU function is
in the funct3 and funct7 fields and is decoded by the ALU control design. The R-type
instructions that is supposed to be implement are add, sub, mul, div, rem, and, xor, and
or. Instruction format for I-type load is for immediate instructions. The register rs1 is
the base register that is added to the 12-bit immediate field to form the memory address.
Field rd is the destination register for the loaded value.
Figure 1.1: Instruction Formats for four different classes of Instructions
Instruction format for S-type is for store instructions.The register rs1 is the base register

Lab Project 16
that is added to the 12-bit immediate field to form the memory address. (The immediate
field is split into a 7-bit piece and a 5-bit piece.) Field rs2 is the source register whose
value should be stored into memory. Instruction format for SB-type conditional branch.
The registers rs1 and rs2 compared. The 12-bit immediate address field is sign-extended,
shifted left 1 bit, and added to the PC to compute the branch target address.
Instruction Opcode Func3 Func7
bits[6 − 0] bits[14 − 12] bits[31 − 25]
add 0110011 000 0000000
sub 0110011 000 0100000
mul 0110011 000 0000001
div 0110011 100 0000001
rem 0110011 110 0000001
and 0110011 111 0000000
or 0110011 110 0000000
xor 0110011 100 0000000
sll 0110011 001 0000000
srl 0110011 101 0000000
addI 0010011 000 Not Applicable
beq 1100011 000 Not Applicable
bneq 1100011 001 Not Applicable
lw 0000011 010 Not Applicable
sw 0100011 010 Not Applicable
Datapath and Controller Diagram

The datapath with all necessary multiplexers and all control lines identified is shown in
Figure 2. The control lines are shown in color. The ALU control block has also been
added, which depends on the funct3 field and part of the funct7 field. Whereas the com-
plete diagram of datapath with controller is shown in Figure 3. The input to the control
unit is the 7-bit opcode field, 3-bit func3 and 7-bit func7 fields from the instruction. The
outputs of the control unit consist of two 1-bit signals that are used to control multi-
plexers (ALUSrc and MemtoReg), three signals for controlling reads and writes in the
register file and data memory (RegWrite, MemRead, and MemWrite), a 1-bit signal used
in determining whether to possibly branch (Branch), and a 4-bit control signal for the
ALU (ALUOp). An AND gate is used to combine the branch control signal and the Zero
output from the ALU; the AND gate output controls the selection of the next PC.

Lab Project 17
Figure 1.2: Datapath with all neccessary control lines
Figure 1.3: Datapath with Controller

Lab Project 18
Conversion of Instruction into Machine Language

The instruction Add R1,R0,#5 becomes
00000000010100000000000010010011
dividing it into 4 bits each and then converting to hexadecimal:
0000 −− > 0
0000 −− > 0
0101 −− > 5
0000 −− > 0
0000 −− > 0
0000 −− > 0
1001 −− > 9
0011 −− > 3
makes it 0x00500093.

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Embedded Systems Lab

Authors: Mr. Umer Shahid

Department of Electrical Engineering

Section 1.1: Objectives

Introduction to SPI Protocol

Figure 1.1: SPI Master Connected with SPI slave

Embedded Systems Lab, EED, UET, Lahore

SPI Signal Sequence

Figure 1.2: SPI Timing Diagram

Section 1.2: Experiment Procedure

1.2.1 Creating a Project in Vivado 2019.1

Figure 1.3: Welcome Dialog

Embedded Systems Lab, EED, UET, Lahore

Figure 1.4: Choosing New Project

Figure 1.5: Choosing Board

5. Click Finish in the New Project Summary dialog. (Figure 1.6)

Figure 1.6: Project Summary

Embedded Systems Lab, EED, UET, Lahore

Figure 1.7: Project Manager

8. In the Add Sources dialog, clickCreate File.

Figure 1.8: Naming Source File

Embedded Systems Lab, EED, UET, Lahore

Figure 1.9: Adding Source File

1.2.2 Simulating SPI Master in verilog

1. Create a new source file with the name SPI master.v.

9. Remember to Choose Full view to observe simulation.

Figure 1.10: Full view

Embedded Systems Lab, EED, UET, Lahore

1.2.3 Simulating SPI Slave in verilog

1. Create a new source file with the name SPI slave.v.

1.2.4 Simulating SPI Master and SPI Slave

1. Create a new source file with the name main code.v.

6. Close the project and if you want also exit Vivado.

1.2.5 Final Implementation

Embedded Systems Lab, EED, UET, Lahore

Figure 1.11: Opening Eleborate Design

Figure 1.12: Assigning Input Output

Embedded Systems Lab, EED, UET, Lahore

7. Run synthesis and click OK in the pop up appeared.

8. Click Run Implementation under Implementation in the Flow Navigator.

Figure 1.13: Synthesis, Implementation, Generate BitStream

Figure 1.14: Schematic Design

13. From the dropdown that opens, select Open Target.

14. Choose AutoConnect.

Figure 1.15: Connect Hardware

Figure 1.16: Hardware Manager

Embedded Systems Lab, EED, UET, Lahore

Table 1.1: Pin Configuration

Input/Output Name Pin Assigned Comments

Embedded Systems Lab, EED, UET, Lahore

• Chapter 4 and Appendix A of ”Computer Organization and Design - The Hard-

• CSCE-513 Computer Architecture (Contents of Lecture 7-10)

• Resources for CS152: Computer Architecture and Engineering Spring 2016 - UC

• Familiarizing with multi cycle architecture design steps of defining an instruction,

• Nexys A7 100T FPGA Board

• Xilinx Vivado 2019.2

Section 1.1: Deliverables

Embedded Systems Lab, EED, UET, Lahore

5. Write back the result

6. Remainder Instruction to get reminder of contents of two registers and store in

Embedded Systems Lab, EED, UET, Lahore

Section 1.2: Diagrams and Tables