EE141- Spring 2004

Lecture 4
Metrics
CMOS Inverter
MOS Transistor Model

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Today’s lecture
‰ Design Metrics (continued)
‰ The CMOS inverter at a glance
‰ An MOS transistor model for manual
analysis

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 Important!
‰ Labs start next week
‰ You must show up in one of the lab sessions
‰ If you don’t show up you will be dropped from
the class
ƒ Unless you let me know that you still want to be in
the class
‰ Homework 2 will be posted later today. Due
next Thursday, February 6.

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The Ideal Gate

V out

Ri = ∞
Ro = 0
Fanout = ∞
g=∞
NMH = NML = VDD/2

V in

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 An Old-time Inverter
5.0

4.0 NML

3.0
(V )

V
o u
t

2.0
VM
NMH
1.0

0.0 1.0 2.0 3.0 4.0 5.0

Vin (V)

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Example: An Old-time Inverter

‰ VOH = 3.6V
‰ VOL = 0.4V
‰ VIL = 0.6V
‰ VIH = 2.3V
‰ NMH = VOH – VIH = 1.3V
‰ NML = VIL – VOL = 0.2V

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 Delay Definitions
Vin

50%

tpHL tpLH
Vout
90%

50%

10% t
tf tr

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Ring Oscillator

v0 v1 v2 v3 v4 v5

v0 v1 v5

T = 2 × tp × N
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 A First-Order RC Network

R
vout

vin C

tp = ln (2) τ = 0.69 RC

Important model – matches delay of an inverter

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Power Dissipation
Instantaneous power:
p(t) = v(t)i(t) = Vsupplyi(t)

Peak power:
Ppeak = Vsupplyipeak

Average power:
1 t +T Vsupply t +T
Pave = ∫ isupply (t )dt
T ∫t
p(t )dt =
T t
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 Energy and Energy-Delay
Power-Delay Product (PDP) =
E = Energy per operation = Pav × tp

Energy-Delay Product (EDP) =

quality metric of gate = E × tp

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A First-Order RC Network
R
vout

vin CL

T T VDD
E 0→1 = ∫ PDD (t )dt = VDD ∫ i DD (t )dt = VDD ∫ CLdv out
2
= CLVDD
0 0 0
T T VDD
1
EC = ∫ PC (t )dt = ∫ v out i L (t )dt = ∫ CLv out dv out = 2
CLVDD
2
0 0 0
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 Summary
‰ Understanding the design metrics that
govern digital design is crucial
ƒ Cost
ƒ Robustness
ƒ Speed
ƒ Power and energy dissipation

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CMOS Inverter
MOS Transistor

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 What is a Transistor?

A MOS Transistor A Switch!

|V GS|
VGS ≥ VT
Ron
S D

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NMOS and PMOS

NMOS Transistor PMOS Transistor

G G
V GS>0 V GS<0

S D S D

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CMOS Inverter: First Glance
N Well
VDD
VDD
PMOS
2λ

PMOS Contacts

In Out

In Out
Metal 1
NMOS Polysilicon

NMOS
GND

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CMOS Inverter
First-Order DC Analysis

V DD V DD

Rp
VOL = 0
VOH = VDD
V out VM = f(Rn, Rp)
V out

Rn

V in ⫽ V DD V in ⫽ 0
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 CMOS Inverter: Transient Response
VDD VDD

Rp tpHL = f(Ron.CL)
= 0.69 RonCL

Vout
Vout
CL
CL
Rn

Vin ⫽ 0 Vin ⫽ VDD

(a) Low-to-high (b) High-to-low
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CMOS Properties
‰ Full rail-to-rail swing
‰ Symmetrical VTC
‰ Propagation delay function of load
capacitance and resistance of transistors
‰ No static power dissipation
‰ Direct path current during switching

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MOS Transistors -
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

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Threshold Voltage: Concept

+
S VG S D
G
–

n+ n+

n-channel Depl etion

region
p-substrate

B
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The Threshold Voltage

Threshold

Fermi potential

2φF is approximately - 0.6V for p-type substrates

γ – the body factor
VT0 is approximately 0.45V for our process

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The Body Effect

0.9

0.85

0.8

0.75

0.7
V (V)

0.65
T

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
BS

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 The Drain Current
Charge in the channel is controlled by the gate voltage:

Drain current is proportional to charge and velocity:

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The Drain Current

Combining velocity and charge:

Integrating over the channel:

Transconductance:

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Transistor in Linear
Linear (Resistive) mode
VGS VDS
S
G ID
D

n+ –
V(x)
+ n+

L x

p-substrate

MOS transistor and its bias conditions

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Transistor in Saturation
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off

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 Saturation
For VGD < VT, the drain current saturates

k′ W
I D = n (VGS − VT )2
2 L

Including channel-length modulation

k′ W
I D = n (VGS − VT )2 (1 + λVDS )
2 L

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Modes of Operation
Cutoff:

VGS < VT ID = 0

Resistive:
k′ W ⎡ V2 ⎤
VT < VGS ; VGS − VT > VDS ID = n ⎢(VGS − VT )VDS − DS ⎥
2 L ⎣⎢ 2 ⎥⎦
Saturation:

VT < VGS ; VGS − VT < VDS k′ W

I D = n (VGS − VT )2
2 L
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 Current-Voltage Relations
A Good Ol’ Transistor
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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A model for manual analysis

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 Current-Voltage Relations
The Deep-Submicron Era
-4
x 10
2.5

VGS= 2.5 V
Early Saturation
2

VGS= 2.0 V
1.5
ID (A)

Linear
1
VGS= 1.5 V Relationship

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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Velocity Saturation
υ n (m/s)

υsat = 105
Constant velocity

Constant mobility (slope = µ)

ξc = 1.5 ξ (V/µm)
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 Velocity Saturation
ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

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ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

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 ID versus VDS
-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5

ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

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Including Velocity Saturation

Approximate velocity:

And integrate current again:

In deep submicron, there are four regions of operation:

(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation
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 Regions of Operation

Long Channel Short Channel

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An Unified Model
for Manual Analysis

S D

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 Regions of Operation
-4
x 10
2.5

VDS=VDSAT
2
Velocity
Linear
Saturated
1.5
I D (A)

0.5
VDSAT=VGT

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
V DS (V) 41
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A PMOS Transistor
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6 Assume all variables
negative!
-0.8 VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

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 Transistor Model
for Manual Analysis

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The Transistor as a Switch

VGS ≥ VT
Ron ID
V GS = VD D
S D
Rmid

R0

V DS
VDD/2 VDD

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 The Transistor as a Switch
5
x 10
7

5
(Ohm)

4
eq

3
R

0
0.5 1 1.5 2 2.5
V (V)
DD

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The Transistor as a Switch

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 Future Perspectives

25 nm MOS transistor (Folded Channel)

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