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INSTRUCTION SET ARCHITECTURE
• The Instruction Set Architecture (ISA) of a processor include the followings:
⇒ Instruction specific set, instruction formats and types
⇒ Supported data types by the instruction set, and
⇒ Operating context for the instructions.
• The ISA level is the interface between the compilers and the hardware.
1. Instruction formats
• A computer will usually have a variety of instruction code formats. It is the function of
the control unit within the CPU to interpret each instruction code and provide the
necessary control functions needed to process the instruction.
• The format of an instruction is usually depicted in a rectangular box symbolizing the bits
of the instruction as they appear in memory words or in control register. The bits of the
instruction are divided into groups called fields. The most common fields found in
instruction formats are:
1. An operation code (opcode) field that specifies the operation to be performed.
2. An address field that designates a memory address or a processor register
3. A mode field that specifies the way the operand or the effective address is determined.
• Other special fields are sometimes employed under certain circumstances, (e.g. a field
that gives the number of shifts in a shift-type instruction, repeat instruction N times,
extended type operand, etc.).
• Instruction format tells how the instructions are coded in binary
• Instruction type information (opcode) can vary quite a lot between different instruction
words.
C program compiled
to ISA program
ASM program
C program
ASM program assembled
to ISA program
ISA level
Software
Hardware
ISA program executed by
microprogram or hardware
Hardware
OPCODE
ADDR1
ADDR2
ADDR3
OPCODE
ADDRESS1 ADDRESS2
OPCODE
ADDRESS
OPCODE
Zero address instruction
One-address instruction
Two-address instruction
Three-address instruction
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• Every instruction is stored in main memory as successive bytes.
• Interpreting memory addresses. There are two different conventions for ordering the bytes
within a word, as shown in figure 3.
• Little Endian byte order puts the byte whose address is "x...x00" at the least significant
position in the word (the little end). In Little Endian, the address of a datum is the least
significant byte address.
• Big Endian byte order puts the byte whose address is "x...x00" at the most significant
position in the word (the big end). In Big Endian addressing, the address of a datum is the
address of the most significant byte
Figure 3. Example word: 6A0244FFh (on 32 bits), for Little and Big Endian conventions. Every byte can be
accessed by an specific address.
• In some machines accesses to objects larger than a byte must be aligned. An access to an
object of size s bytes at byte address A is aligned if A mod s = 0. See examples at lecture!
• Misalignment causes hardware complications, since the memory is typically aligned on a
word boundary. A missaligned memory access will, therefore, take multiple aligned
memory references.
Example aligned / missaligned (for little endian convention)
FF
44
02
6A
Little Endian
x0000
memory address
x0001
x0002
x0003
x0004
x0005
x0006
x0007
x0008
word 1
word 2
Least significant
byte in word 1
Most significant
byte in word 1
6A
02
44
FF
Big Endian
x0000
memory address
x0001
x0002
x0003
x0004
x0005
x0006
x0007
x0008
word 1
word 2
Least significant
byte in word 1
Most significant
byte in word 1
Byte 0
Byte 2
x0000
memory address
x0004
x0008
x000C
x0010
word 1 aligned at
address x0000h
Byte 2
Byte 0
Byte 1
Byte 3
Byte 3
Byte 1
word 2 misaligned at
address x000Ah
Data bus
32 bits
8 bits
8 bits
8 bits
8 bits

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Main desirable features of an ISA
1. Regularity (Orthogonality) - No special registers, few special cases, all operand modes
available with any data type or instruction type. Orthogonal instruction sets simplify
programming both by reducing the number of distinct opcodes needed and by simplifying
the rules for operand address specification. Most computers have very little orthogonality
since processor costs can be reduced at the expense of programming costs.
2. Completeness - Support for a wide range of operations and target applications. But, for a
real microprocessor, ISA can not include an entire set of operators. In programs the
operators have different frequency of utilization, and accordingly there must censor the set
of operators. The rule for design an ISA is: execute fast the frequent operations and
correct the infrequent one.
Classifying instruction set architectures
Instruction sets can be broadly classified along the five dimensions described in the table
below, which are roughly ordered by the role they play in distinguishing instruction sets.
Operand storage in the CPU Where are operands kept other than in memory?
Number of explicit operands
per instruction
How many operands are named explicitly in a typical
instruction?
Operand location
Can any ALU instruction operand be located in memory
or must some or all of the operands be in internal
storage in the CPU? If an operand is located in memory,
how is the memory location specified?
Operations
What operations are provided in the instruction set?
Type and size of operands
What is the type and size of each operand and how is it
specified?
• The type of internal storage in the CPU is the most basic differentiation. Operands may be
named explicitly or implicitly. The major alternatives for storing operands within the
CPU are:
➢ a stack - operands stored implicitly on the top of the stack (stack machine).
➢ an accumulator - at least one operand is implicitly in the accumulator (accumulator
machine).
➢ a set of registers - general purpose register architectures have only explicit operands
either in registers or memory locations (general-purpose register machine).
Stack
Accumulator
Register
push A
load A
load R1,A
push B
add B
add R1,B
add
store C
store C, R1
pop C
Figure 3.3. Example of the code sequence for C = A+B for three different instruction sets. It is assumed that A,
B, and C all belong in memory and that the values A and B cannot be destroyed.
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• We can note the primary advantages and disadvantages of each of these approaches (he
advantages and disadvantages are related to three issues: (1) how well the structure
matches the needs of a compiler, (2) how efficient the approach is from an
implementation viewpoint and (3) what the effective code size is relative to other
approaches.):
Stack machine type:
A: Simple model of expression evaluation (reverse polish). Short instructions can
yield good code density.
D: A stack cannot be randomly accessed ⇒ makes it difficult to generate efficient
code. It's also difficult to implement efficiently, since the stack becomes a bottleneck.
Accumulator machine type:
A: Minimizes internal state of machine. Short instructions.
D: Since accumulator is only temporary storage, memory traffic is highest for this
approach.
Register machine type:
A: Most general model for code generation.
D: All operands must be named, leading to longer instructions.
• Number of explicit addresses per instruction:
⇒ the fewer the address, the shorter the instruction
⇒ limiting the number of addresses also limits the range of functions each instruction
can perform
⇒ fewer addresses mean more primitive instructions, and longer programs required to
perform any given task
⇒ larger programs require longer execution times
⇒ long instructions, with multiple addresses usually require more complex decoding and
processing circuits.
• Example:
3 address machine
add z,x,y ; z ← x+y , where x,y,z, are registers or memory locations
2 address machine
add x,y ; ac ← x+y (ac = accumulator), or
; x ← x+y
1 address machine
add x ; ac ← ac+x
• There is a strong relation between the two above classification criterion.
• Example:
AC: add x ; ac ← ac + @x
RG: add r1,r2,r3 ; r1 ← r2 + r3 or r3 ← r1 + r2
add r1,r2 ; r1 ← r1 + r2
mov r1,r2 ; r1 ← r2 or r2 ← r1
add r1,x ; r1 ← r1 + @x
ST: push x ; TopS ← @x
add ; Result in TopS
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RISC versus CISC
The major attributes of RISC machines are the followings:
1. The instruction set is limited and includes only simple instructions.
⇒ few instruction types and few addressing modes (usually register-direct, register-
indirect, relative)
⇒ simple instruction set that execute quickly (executed in a single machine cycle by
pipelining).
⇒ hardwired control unit, to decode simple instructions
⇒ reduced complexity of the control unit and the data path allow the processor to work at
a high clock frequency.
2. Load-and-store architecture
Only LOAD and STORE instructions reference data in memory; all other instructions
operate only with registers (are register-to-register instructions)
3. Instructions are of fixed length and uniform format
⇒ advantages in pipelining
⇒ loading and decoding of instructions is simple and fast
4. A large number of registers is available
⇒ because of the reduced complexity of the processor there is enough space on the chip
to be allocated to a large number of registers.
5. Use compilers to optimize object code performance
⇒ Compilers are used to optimize the object code, by resolving pipeline hazards