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8-1. Introduction 8-2. General Register Organization
8-1. Introduction 8-2. General Register Organization
l 1) Register Set l 2) MUX B selector (SELB) : to place the content of R3 into BUS B
l 3) Control l 4) Decoder selector (SELD) : to transfer the content of the output bus into R1
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
u Bus organization for 7 CPU registers : Fig. 8-2 » POP : Pop-Up = Deletion 64
l 2 MUX : select one of 7 register or external data
3×8 A bus B bus
decoder l Stack의 종류
input by SELA and SELB » 1) Register Stack (Stack Depth가 제한) FULL EMTY
l BUS A and BUS B : form the inputs to a SELD Arithmetic logic unit n a finite number of memory words or register(stand alone)
OPR (ALU)
common ALU » 2) Memory Stack (Stack Depth가 유동적)
l ALU : OPR determine the arithmetic or logic n a portion of a large memory 4
External Output
microoperation u Register Stack : Fig. 8-3
SP C 3
Output B 2
» The result of the microoperation is available for (a) Block diagram
l PUSH : SP ← SP + 1
A 1
external data output and also goes into the inputs 3 3 3 5 : Increment SP Last Item 0
of all the registers SELA SELB SELD OPR * 초기 상태 M [ SP ] ← DR : Write to the stack
SP = 0,
l 3 X 8 Decoder : select the register (by SELD) (b) Control word
» The first item is stored at address 1, and the last item is stored at address 0 u 3 types of CPU organizations X = Operand Address
l POP : DR ← M [ SP ] : Read item from the top of stack * Memory Stack
l 1) Single AC Org. : ADD X AC ← AC + M [ X ]
PUSH = Address 감소
SP ← SP − 1 : Decrement Stack Pointer R1 ← R 2 + R 3
* Register Stack l 2) General Register Org. : ADD R1, R2, R3
If ( SP = 0 ) then ( EMTY ← 1) : Check if stack is empty PUSH = Address 증가
l 3) Stack Org. : PUSH X TOS ← M [ X ]
FULL ← 0 : Mark not full Address
Memory unit
u The influence of the number of addresses on computer instruction
u Memory Stack : Fig. 8-4 PC
1000
[예제] X = (A + B)*(C + D)
l PUSH : SP ← SP − 1 Program
(instructions) - 4 arithmetic operations : ADD, SUB, MUL, DIV
M [ SP ] ← DR
* 초기 상태
2000 - 1 transfer operation to and from memory and general register : MOV
SP = 4001 » The first item is stored at address 4000 AR
Data - 2 transfer operation to and from memory and AC register : STORE, LOAD
l POP : DR ← M [ SP ] (operands)
- Operand memory addresses : A, B, C, D
SP ← SP + 1 * Error Condition
3000
PUSH when FULL = 1 - Result memory address : X
Stack
u Stack Limits POP when EMTY = 1
l 1) Three-Address Instruction
l Check for stack overflow(full)/underflow(empty) 3997 ADD R1, A, B R1 ← M [ A] + M [ B ]
SP 3998
» Checked by using two register
3999
ADD R2, C, D R 2 ← M [C ] + M [ D ]
n Upper Limit and Lower Limit Register
4000 MUL X, R1, R2 M [ X ] ← R1 ∗ R 2
» After PUSH Operation 4001
Start Here » Each address fields specify either a processor register or a memory operand
n SP compared with the upper limit register
» After POP Operation » : Short program
» Require too many bit to specify 3 address
y
n SP compared with the lower limit register DR
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
8-4. Instruction Formats 9 / 22 8-5. Addressing Modes 11 / 22
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
l Example : LD $ADR AC ← M [ PC + ADR ] l 8 Addressing Mode for the LOAD Instruction : Tab. 8-6
» @ : Indirect Address
u Indexed Addressing Mode
» $ : Address relative to PC
l XR (Index register) is added to the address part of the instruction to obtain the » # : Immediate Mode
effective address » ( ) : Index Mode, Register Indirect, Autoincrement 에서 register 지정
l Example : LD ADR(XR) AC ← M [ ADR + XR ]
u Data Manipulation Instruction
u Base Register Addressing Mode Not Here l 1) Arithmetic, 2) Logical and bit manipulation, 3) Shift Instruction
l the content of a base register is added to the address part of the instruction to
obtain the effective address
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
l Similar to the indexed addressing mode except that the register is now called a l Arithmetic Instructions : Tab. 8-7
base register instead of an index register
l Logical and Bit Manipulation Instructions : Tab. 8-8
» index register (XR) : LD ADR(XR) AC ← M [ ADR + XR ] ADR 기준
n index register hold an index number that is relative to the address part of the instruction l Shift Instructions : Tab. 8-9
» base register (BR) : LD ADR(BR) AC ← M [ BR + ADR ] BR 기준 n 8-7 Program Control
n base register hold a base address
n the address field of the instruction gives a displacement relative to this base address u Program Control Instruction : Tab. 8-10
Address Memory l Branch and Jump instructions are used interchangeably to mean the same thing
u Numerical Example
PC = 200 200 Load to AC Mode
Addressing Mode Effective Address Content of AC u Status Bit Conditions : Fig. 8-8
201 Address = 500
Immediate Address Mode 201 500
l Condition Code Bit or Flag Bit
Direct Address Mode 500 800 R1 = 400 202 Next instruction
Indirect Address Mode 800 300 » The bits are set or cleared as a result of an operation performed in the ALU
Register Mode 400 u 4-bit status register
XR = 100
Register Indirect Mode 400 700
Relative Address Mode 702 325 399 450 l Bit C (carry) : set to 1 if the end carry C8 is 1
Indexed Address Mode 600 900 AC 400 700 l Bit S (sign) : set to 1 if F7 is 1
Autoincrement Mode 400 700
u
Autodecrement Mode 399 450 500 800 l Bit Z (zero) : set to 1 if the output of the ALU contains all 0’s
R1 = 400 l Bit V (overflow) : set to 1 if the exclusive-OR of the last two carries (C8 and C7) is
600 900 equal to 1
500 + 202 (PC)
R1 = 400 (after) l Flag Example : A - B = A + ( 2’s Comp. Of B ) : A =11110000, B = 00010100
702 325
500 + 100 (XR) 11110000
R1 = 400 -1 (prior)
+ 11101100 (2’s comp. of B) C = 1, S = 1, V = 0, Z = 0
800 300
1 11011100
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
8-7. Program Control 17 / 22 8-8. Reduced Instruction Set Computer (RISC) 19 / 22
u Conditional Branch : Tab. 8-11 n 8-8 Reduced Instruction Set Computer (RISC)
u Subroutine Call and Return u Complex Instruction Set Computer (CISC)
l CALL : SP ← SP − 1 : Decrement stack point l Major characteristics of a CISC architecture
M [ SP ] ← PC : Push content of PC onto the stack » 1) A large number of instructions - typically from 100 to 250 instruction
PC ← Effective Address : Transfer control to the subroutine » 2) Some instructions that perform specialized tasks and are used infrequently
l RETURN : PC ← M [ SP ] : Pop stack and transfer to PC » 3) A large variety of addressing modes - typically from 5 to 20 different modes
» 4) Variable-length instruction formats
SP ← SP + 1 : Increment stack pointer
» 5) Instructions that manipulate operands in memory (RISC 에서는 in register)
u Program Interrupt
u Reduced Instruction Set Computer (RISC)
l Program Interrupt
l Major characteristics of a RISC architecture
» Transfer program control from a currently running program to another service program
as a result of an external or internal generated request » 1) Relatively few instructions
» Control returns to the original program after the service program is executed » 2) Relatively few addressing modes
» 3) Memory access limited to load and store instruction
l Interrupt Service Program 과 Subroutine Call 의 차이점
» 4) All operations done within the registers of the CPU
» 1) An interrupt is initiated by an internal or external signal (except for software interrupt)
» 5) Fixed-length, easily decoded instruction format
n A subroutine call is initiated from the execution of an instruction (CALL)
» 2) The address of the interrupt service program is determined by the hardware » 6) Single-cycle instruction execution
n The address of the subroutine call is determined from the address field of an instruction » 7) Hardwired rather than microprogrammed control
» 3) An interrupt procedure stores all the information necessary to define the state of the
CPU
n A subroutine call stores only the program counter (Return address)
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
» User Mode : User program 실행 PC, CPU Register, Status Condition Common to D and A
Circular Window
u Overlapped Register Windows R10
n When the CPU is executing an user program Store Information
R73
CPU operating mode is determined from special bits in the PSW l Time consuming operations during procedure call Local to D
R64
» Saving and restoring registers R63
Common to C and D
u Types of Interrupts Main body of ISR » Passing of parameters and results R58
R57
Proc D
» come from I/O device, from a timing device, from a circuit » Provide the passing of parameters and avoid the need R48
R47
R42
l 2) Internal Interrupts or TRAP u Concept of overlapped register windows : Fig. 8-9 Proc C R41
Local to B
Interrupt
» caused by register overflow, attempt to divide by zero, Return l Total 74 registers : R0 - R73 R32
R31
Common to A and B
an invalid operation code, stack overflow, and protection violation » R0 - R9 : Global registers
R26
l 3) Software Interrupts » R10 - R63 : 4 windows Proc B R25
Local to A
Computer System Architecture Chap. 8 Central Processing Unit Computer System Architecture Chap. 8 Central Processing Unit
8-8. Reduced Instruction Set Computer (RISC) 21 / 22
» Example) ADD R22, R21, R23 (a) Register mode : (S2 specifies a register)
n ADD Rs, S2, Rd : Rd = Rs + S2
l Register Immediate Mode : bit 13 = 1 31 24 23 19 18 14 13 12 0
Opcode Rd Rs 1 S2
» S2 = sign extended 13 bit constant
8 5 5 1 13
» Example) LDL (R22)#150, R5
n LDL (Rs)S2, Rd : Rd = M[R22] + 150 (b) Register-immediate mode : (S2 specifies an operand)
l PC Relative Mode
31 24 23 19 18 0
» Y = 19 bit relative address Opcode COND Y
» Example) JMPR COND, Y 8 5 19
n Jump to PC = PC + Y
» CWP (Current Window Pointer) (c) PC relative mode :
n CALL, RET시 stack pointer 같이 사용됨
l RISC Architecture Originator
Architecture Originator Licensees
Alpha DEC Mitsubishi, Samsung
MIPS MIPS Technologies NEC, Toshiba
PA-RISC Hewlett Packard Hitachi, Samsung
PowerPC Apple, IBM, Motorola Bul r p
Sparc Sun Fujitsu, Hyundai
i960 Intel Intel only (Embedded Controller)