PIC Microcontrollers

Chapter 7: ADDRESSING MODES,BANK SWITCHING,

TABLE PROCESSING,

Gaby A.H- M.S. Fall 2017 - 2018

 • The various addressing modes of a microconrroller are
determined when it is designed, and therefore cannot be changed
by the programmer.
• The PIC 18 provides a total of four distinct addressing modes.
They are as follows:
▫ Immediate
▫ Direct
▫ Register indirect
▫ Indexed-ROM

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 • In immediate addressing mode: as the name implies, the operand
comes immediately after the opcode.
• Notice that immediate data is called a literal in the PIC.
MOVLW 0x25 ;load 25H into WREG
SUBLW D'62' ;subtract WREG from 62
ANDLW B„0l000000' ;AND WREG with 40H
• Direct addressing mode
MOVLW 0x56 ;WREG = 56H (immediate addressing mode)
MOVWF 0x40 ;copy WREG into fileReg RAM location 40H
MOVFF 0x40,0x50 ;copy data from loc 40H to 50H.

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 • The difference between "INCF fileReg, W' and "INCF fileReg, F“
▫ In direct addressing mode, when an operation is performed on a file
register, we have the option of saving the result in the file register itself or
in WREG, This creates a major source of errors:

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 • DECFSZ and DECF:

▫ Or this

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 • Register indirect addressing mode
▫ In the register indirect addressing mode, a register is used as a pointer to
the data RAM location. In the PIC18, three registers are used for this
purpose:
 FSR0, FSRl, and FSR2.
 FSR stands for file select register and must not be confused with SFR (special
function register).
▫ The FSR is a 12-bit register allowing access to the entire 4096 bytes of
data RAM space in the PIC18.
▫ We use LFSR (load FSR) to load the RAM address.
▫ In other words, when FSRx are used as pointers, they must be loaded first
with the RAM addresses as shown below

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 LFSR 0, 0x30 ;load FSRO with 0x30
LFSR 1, 0x40 ;load FSR1 with 0x40
LFSR 2, 0x6F ;load FSR2 with 0x6F

▫ Because FSR0, FSRl, and FSR2 are 12-bit registers they cannot fit into
the SFR address space unless they are split into pieces of an 8-bit size.
▫ That is exactly what PIC18 has done.
▫ The FSR registers have the low-byte and high-byte parts called FSRxL
and FSRxH, as shown in the SFR table.
▫ we see FSR0L and FSR0H, representing the low and high parts of the 12-
bit FSR0 register.
▫ Note that the FSRxH is only 4-bit and the upper 4 bits are not used.

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 ▫ Another register associated with the register indirect addressing mode is
the INDF (indirect register).
▫ Each of the FSR0, FSRI, and FSR2 registers has an INDF register
associated with it, and these are called INDFO, INDFl, and INDF2.
▫ When we move data into INDFx we are moving data into a RAM location
pointed to by the FSR.
▫ In the same way, when we read data from the INDF register, we are
reading data from a RAM location pointed to by the FSR.

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 • Advantages of register indirect addressing mode
▫ One of the advantages of register indirect addressing mode is that it make
accessing data dynamic rather than static, as with direct addressing mode.
▫ In the following example shows three cases of copying 55H into RAM locations
40H to 45H.
▫ Notice in solution (b) that two instructions are repeated numerous times.
▫ We can create a loop with those two instructions as shown in solution (c).
Solution (c) is the most efficient and is possible only because of the register
indirect addressing mode.

• Example: Write a program to copy the value 55H into RAM memory
locations 40H to 45H using
(a) Direct addressing mode.
(b) Register indirect addressing mode without a loop.
(c) A loop.

Gaby A.H- M.S. Fall 2017 - 2018

 MOVLW 0x55
MOVWF 0x40
MOVWF 0x41
MOVWF 0x42
MOVWF 0x43
MOVWF 0x44

MOVLW 55H
LFSR 0,0x40
MOVWF INDF0
INCF FSR0L,F
MOVWF INDF0
INCF FSR0L,F
MOVWF INDF0
INCF FSR0L,F
MOVWF INDF0
INCF FSR0L,F
MOVWF INDF0
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 COUNT EQU 0x10
MOVLW 0x5
MOVWF COUNT
LFSR 0,0x40
MOVLW 0x55
B1 MOVWF INDF0
INCF FSR0L,F
DECF COUNT,F
BNZ B1

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 • Example: Assume that RAM locations 30-34H have a string of ASCII
data, as shown below. Write a program to get each character and send
it to Port B one byte at a time. Show the program using:
(a) Direct addressing mode.
(b) Register indirect addressing mode.

30 = ('H')
31 = ('E')
32 = ('L')
33 = ('L')
34 = ('O')

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 CLRF TRISB
MOVFF 0x30, PORTB
MOVFF 0x31, PORTB
Using direct addressing mode
MOVFF 0x32, PORTB
MOVFF 0x33, PORTB
MOVFF 0x34, PORTB

COUNTREG EQU 0x20

CNTVAL EQU 5
CLRF TRISB
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 2,0x30 Using register indirect mode
B3 MOVF INDF2,W
MOVWF PORTB
INCF FSR2L
DECF COUNTREG,F
BNZ B3
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 • Auto-increment option for FSR
▫ Because the FSR is a 12-bit register, it can go from 000 to FFFH, which
covers the entire 4K RAM space of the PIC18.
▫ Using the “INCF FSR0L, F“ instruction to increment the pointer can
cause a problem when an address such as 5FFH is incremented.
▫ The instruction “INCF FSR0L, F" will not propagate the carry into the
FSR1H register.
▫ The PIC 18 gives us the options of auto-increment and auto-decrement
for FSRn to overcome this problem.

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 • Note:
▫ This table shows the syntax for the CLRF instruction, it works for all
such instructions.
▫ The auto-decrement or auto-increment affects the entire 12 bits of the
FSRn and has no effect on status register.
▫ This means that FSR0 going from FFF to 000 will not raise any flag.
▫ The option of PLUSWn is widely used for a RAM-based look-up table.

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 Example: Write a program to clear 16 RAM locations starting at RAM address 60H.
Use the following:
(a) INCF FSRnL
(b) Auto-increment

COUNTREG EQU 0x10 COUNTREG EQU 0x10

CNTVAL EQU D'16' CNTVAL EQU D'16'
MOVLW CNTVAL MOVLW CNTVAL
MOVWF COUNTREG MOVWF COUNTREG
LFSR 1,0x60 LFSR 1,0x60
B2 CLRF INDF1 B3 CLRF POSTINC1
INCF FSR1L,F DECF COUNTREG,F
DECF COUNTREG,F BNZ B3
BNZ B2
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Gaby A.H- M.S. Fall 2017 - 2018
 • Example: Write a program to copy a block of 5 bytes of data from
RAM locations starting at 30H to RAM locations starting at 60H.
COUNTREG EQU 0x10
CNTVAL EQU D'5'
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 0,0x30
LFSR 1,0x60
B3 MOVF POSTINC0,W
MOVWF POSTINC1
DECF COUNTREG,F
BNZ B3

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 • BCD (binary coded decimal) number system
▫ Unpacked BCD
 In unpacked BCD, the lower 4 bits of the number represent the BCD number,
and the rest of the bits are 0.
 Example: "0000 1001" and "0000 0101" are unpacked BCD for 9 and 5,
respectively.
 Unpacked BCD requires 1 byte of memory, or an 8-bit register, to contain it.
▫ Packed BCD
 In packed BCD, a single byte has two BCD numbers in it: one in the lower 4
bits, and one in the upper 4 bits.
 For example, “0101 1001" is packed BCD for 59H.
 Only 1 byte of memory is needed to store the packed BCD operands.
 Thus one reason to use packed BCD is that it is twice as efficient in storing
data.
Gaby A.H- M.S. Fall 2017 - 2018
 MOVLW 0x17
ADDLW 0x28

▫ Adding these two numbers gives “0011 1111” B (3FH), which is not BCD!
▫ A BCD number can only have digits from 0000 to 1001 (or 0 to 9).
▫ In other words, adding two BCD numbers must give a BCD result.
▫ The result above should have been 17 + 28 = 45 (0100 0101).
▫ To correct this problem, the programmer must add 6 (0110) to the low digit: 3F +
06 = 45H.
▫ The same problem could have happened in the upper digit (for example, in 52H +
87H = D9H).
▫ Again, 6 must be added to the upper digit (D9H + 60H = 139H) to ensure that the
result is BCD (52 + 87 = 139).
▫ This problem is so widespread that most microprocessors such as the PIC 18
have an instruction to deal with it.
▫ In the PIC18 instruction "DAW" is designed to correct the BCD addition
problem.

Gaby A.H- M.S. Fall 2017 - 2018

 • DAW instruction
▫ The DAW (decimal adjust WREG) instruction in the PIC18 is provided to
correct the aforementioned problem associated with BCD addition.
▫ The mnemonic "DAW" works only with an operand in the WREG
register.
▫ The DAW instruction will add 6 to the lower nibble or higher nibble if
needed; otherwise, it will leave the result alone.
▫ The following example will clarify these points.

MOVLW 0x47 ;WREG = 47H first BCD operand

ADDLW 0x25 ;hex(binary) addition (WREG = 6CH)
DAW ;adjust for BCD addition (WREG = 72H)

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 • Example: Assume that 5 BCD data items are stored in RAM locations
starting at 40H, as shown below. Write a program to find the sum of
all the numbers. The result must be in BCD.
40 (71)
41 (BB)
42 (69)
43 ( 9 7)

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 L_Byte EQU 0x6
H_Byte EQU 0x7

MOVLW 0
MOVWF H_Byte
ADDWF 0x40,W
DAW
BNC N_1
INCF H_Byte,F
N_1 ADDWF 0x41,W
DAW
BNC N_2
INCF H_Byte,F
N_2 ADDWF 0x42,W
DAW
BNC N_3
INCF H_Byte
N_3 ADDWF 0x43,W
DAW
BNC N_4
INCF H_Byte,F
N_4 MOVWF L_Byte

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Gaby A.H- M.S. Fall 2017 - 2018
 • Example: Assume that RAM locations 40-43H have the following
hex data. Write a program to add them together and place the result in
COUNTREG EQU 0x20
locations 0x06 and 0x07.
L_BYTE EQU 0x06
H_BYTE41
40 = (7D) EQU 0x07
=(EB) 42 = (C5) 43 = (5B)
CNTVAL EQU 4
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 0,0x40
CLRF WREG
CLRF H_BYTE
B5 ADDWF POSTINC0, W
BNC OVER
INCF H_BYTE,F
OVER DECF COUNTREG,F
BNZ B5
MOVWF L_BYTE
Gaby A.H- M.S. Fall 2017 - 2018
 • The PIC18 has a maximum of 2M of code (program) space and 4K of
data RAM space.
• While we never use any of the data RAM space for storing code, we
can use the code space to store fixed data.
• In this section we discuss how to access fixed data residing in the
program ROM space of the PIC 18.
• DB (define byte) and fixed data in program ROM
▫ The DB data directive is widely used to allocate ROM program (code)
memory in byte-sized chunks.
▫ DB is used to define an 8-bit fixed data.
▫ When DB is used to define fixed data, the numbers can be in decimal,
binary, hex, or ASCII formats.
▫ The DB directive is used to define ASCII strings.
Gaby A.H- M.S. Fall 2017 - 2018
 • Example: Assume that we have burned the following fixed data into
program ROM of a PIC chip. Give the contents of each ROM location
starting at 500H.

ORG 500H
DATA1 DB D'28'
DATA2 DB B'00110101'
DATA3 DB 0x39
ORG 510H
DATA4 DB 'Y'
DATA5 DB '2','0','0','5'
ORG 518H
DATA6 DB "Hello ALI"
END

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Gaby A.H- M.S. Fall 2017 - 2018
 • Reading table elements in the PIC18
▫ The 2M of program (code) space is under the direct control of the
program counter register.
▫ This means that we need to have a special function register to point to the
data to be fetched from the code space.
▫ For this reason we can call it register indirect ROM addressing mode.
▫ This is an addressing mode widely used to access data elements located in
the program ROM space of the PIC 18.
▫ This is often called table processing.
▫ There is a group of instructions in the PIC 18 designed for both table read
and table write.

Gaby A.H- M.S. Fall 2017 - 2018

 ▫ TBLPTR is a 21-bit register and is used to point to the byte to be fetched.
▫ With the 21- bit register TBLPTR, we can cover the entire 2M program
(code) space for the PIC 18.
▫ TBLPTR is divided into three 8-bit parts.
▫ These are called TBLPTRL (low), TBLPTRH (high), and TBLPTRU
(upper), and all are part of the SFRs.
▫ Notice that the last 2 bits of TBLPTRU (upper) are not used and are
cleared to 0s.

• Auto-increment option for TBLPTR

▫ Using the "INCF TBLPTRL,F" instruction to increment the pointer can
cause a problem when an address such as 5FFH is incremented.

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Gaby A.H- M.S. Fall 2017 - 2018
Gaby A.H- M.S. Fall 2017 - 2018
Gaby A.H- M.S. Fall 2017 - 2018
 • The file register RAM is divided into banks of 256 bytes each, which
gives us a total of 16 banks in the PIC18.
• The minimum bank that every PIC18 has is called the access bank, as
we discussed earlier.
• The access bank is made of 128 bytes of lower addresses and 128
bytes of higher addresses.
• While the lower 128 bytes of address space 000 - 07FH are used for
general-purpose RAM, the higher 128 bytes are dedicated to the SFRs
(special function registers) residing in address space F80 - FFFH.

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 • The A bit and bank switching
▫ All the instructions we have used so far assumed the access bank as the
default bank.
▫ This was achieved by ignoring the letter A in instructions such as
"MOVWF fileReg, A".
▫ In other words, the instruction "MOVWF fileReg" is really "MOVWF
fileReg, A" where the A bit can be 0 or 1.
▫ If A= 0, then the access bank is the default bank.
▫ If A= I, however, then the instruction will use the bank selector register
(BSR) to select the bank instead of using the access bank.
▫ If A is not stated in a given instruction, it means A= 0 and the access bank
is the default bank.

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 • The BSR register and bank switching
▫ To use banks other than the access bank, we need to set bit A= 1 in the
coding of the instruction.
▫ With A= 1, we use the BSR (bank select register) to choose the desired
bank.
▫ The BSR is an 8-bit register and is part of the SFRs.
▫ Of the 8 bits of the BSR, only 4 least-significant bits are used in the
PIC18.
▫ The upper 4 bits are set to zero and are ignored by the PIC18.
▫ The 4-bit BSR gives us 16 banks, and because each bank is 256 bytes, we
cover the entire 4096 (16 x 256 = 4096) bytes of the data RAM file
register using bank switching.
▫ The 4K ( 4096) bytes of the data RAM are organized as banks 0 to F,
where the lowest bank, 0, has an address of 00 - FFH, and the highest
bank is bank F with the addresses of F00 - FFFH.
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 • The BSR register and bank switching
▫ Upon power-on reset, BSR = 0 (0000 binary), which indicates that only
the lowest addresses of data RAM, from 000 to 0FFH, can be used for the
general-purpose register in addition to the SFRs, which always reside in
the last half of bank F.
▫ Similarly, if we make BSR = 1 (0001 binary), then PIC18 selects bank 1
using the 100-lFFH addresses in addition to the SFRs, which use only the
last half of the bank with addresses of F80 - FFFH.
▫ To select bank 2, we load BSR with the value 02 (0010 binary), which
allows access to the bank addresses 200 - 2FF in addition to the SFR
addresses of F80-FFFH.

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 • Bank switching and "INCF F, D, A" instruction
▫ All the examples we have seen so far ignored the A bit in the instruction,
which means that A = 0.
▫ With A= 0, the access bank is the default bank.
▫ Now to use banks other than the access bank, two things must be done:
1. Load the BSR with the desired bank number, and
2. Make A= 1 in the instruction itself.
▫ Therefore, instruction "INCF MYREG, F, 1" has a totally different
meaning from "INCF MYREG, F, o".
▫ The A= 1 means to use the bank pointed to by BSR.
▫ In the following code, we first load the bank number into the BSR
register using the MOVLB instruction, and then manipulate the contents
of RAM location 0x240 (location 40 of bank 2):
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Gaby A.H- M.S. Fall 2017 - 2018
 • Example: Write a program to copy the value 55H into RAM memory
locations 340H to 345H using:
(a) direct addressing mode.
(b) a loop.
MOVLB 0x3 COUNT EQU 0x10
MOVLW 0x55 MOVLB 0x3
MOVWF 0x40, 1 MOVLW 0x5
MOVWF 0x41, 1 MOVWF COUNT
MOVWF 0x42, 1 LFSR 0,0x340
MOVWF 0x43, 1 MOVLW 0x55
MOVWF 0x44, 1 B1 MOVWF INDF0,0
INCF FSR0L
DECF COUNT,F,0
BNZ B1

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 • MOVFF and banks
▫ The great thing about the MOVFF instruction is that there is no need to
worry about bank switching because it can move data anywhere within
the 4K of RAM space.
• Example: Assume RAM locations 330-334H of the PIC18F458 have
the string of ASCII data shown below. Write a program to get each
character and send it to Port B one byte at a time. Show the program
using
(a) direct addressing mode. 330 = ('H')
(b) register indirect addressing mode. 331 = ('E')
332 = ('L')
333 = ('L')
334 = ('O')
Gaby A.H- M.S. Fall 2017 - 2018
 CLRF TRISB
MOVFF 0x330, PORTB
MOVFF 0x331, PORTB
MOVFF 0x332, PORTB
MOVFF 0x333, PORTB
MOVFF 0x334, PORTB

COUNTREG EQU 0x20

CNTVAL EQU 5
CLRF TRISB
MOVLW CNTVAL
MOVWF COUNTREG
LFSR 2,0x330
B3 MOVF INDF2,W
MOVWF PORTB
INCF FSR2L
DECF COUNTREG,F
BNZ B3
Gaby A.H- M.S. Fall 2017 - 2018