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The MC34129/MC33129 are high performance current mode switching
HIGH PERFORMANCE
regulators specifically designed for use in low power digital telephone CURRENT MODE
applications. These integrated circuits feature a unique internal fault timer
that provides automatic restart for overload recovery. For enhanced system
CONTROLLERS
efficiency, a start/run comparator is included to implement bootstrapped SEMICONDUCTOR
operation of VCC. Other functions contained are a temperature compensated TECHNICAL DATA
reference, reference amplifier, fully accessible error amplifier, sawtooth
oscillator with sync input, pulse width modulator comparator, and a high
current totem pole driver ideally suited for driving a power MOSFET.
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Also included are protective features consisting of soft–start,

undervoltage lockout, cycle–by–cycle current limiting, adjustable deadtime, P SUFFIX
PLASTIC PACKAGE
and a latch for single pulse metering.
CASE 646
Although these devices are primarily intended for use in digital telephone 14
systems, they can be used cost effectively in many other applications. 1

• Current Mode Operation to 300 kHz

• Automatic Feed Forward Compensation
• Latching PWM for Cycle–by–Cycle Current Limiting
• Continuous Retry after Fault Timeout
D SUFFIX
• Soft–Start with Maximum Peak Switch Current Clamp
14
PLASTIC PACKAGE
• Internally Trimmed 2% Bandgap Reference 1
CASE 751A
(SO–14)
• High Current Totem Pole Driver
• Input Undervoltage Lockout
• Low Startup and Operating Current
• Direct Interface with Motorola SENSEFET Products PIN CONNECTIONS

Drive Output 1 14 VCC

Drive Ground 2 13 Start/Run Output

Ramp Input 3 12 CSoft–Start

Sync/Inhibit 4 Feedback/
11 PWM Input
Simplified Block Diagram Input
Error Amp
RT/CT 5 10
Inverting Input
13 Start/Run
Start/Run
Output Vref 2.5 V 6 9 Error Amp
Noninverting Input
Soft–Start Gnd 7 8 Vref 1.25 V
12 Undervoltage 14
CSoft–Start and VCC
Lockout
Fault Timer (Top View)
1.25V 8
Reference Vref 1.25V
7
Gnd

Error Amp
9 Noninverting ORDERING INFORMATION
+ Input
6 10
X2 – Inverting Operating
Vref 2.5V
Input Device Temperature Range Package
Latching 11
Feedback/
PWM
1 PWM Input MC34129D
TA = 0° to +70°C
SO–14
5 Drive Out Plastic DIP
RT/CT Oscillator MC34129P
2
Drive Gnd MC33129D SO–14
Sync/Inhibit 4 3 TA = – 40° to +85°C
Input Ramp Input MC33129P Plastic DIP

 Motorola, Inc. 1996 Rev 1

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MAXIMUM RATINGS
Rating Symbol Value Unit
VCC Zener Current IZ(VCC) 50 mA
Start/Run Output Zener Current IZ(Start/Run) 50 mA
Analog Inputs (Pins 3, 5, 9, 10, 11, 12) – –0.3 to 5.5 V
Sync Input Voltage Vsync –0.3 to VCC V
Drive Output Current, Source or Sink IDRV 1.0 A
Current, Reference Outputs (Pins 6, 8) Iref 20 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package Case 751A
Maximum Power Dissipation @ TA = 70°C PD 552 mW
Thermal Resistance, Junction–to–Air RθJA 145 °C/W
P Suffix, Plastic Package Case 646
Maximum Power Dissipation @ TA = 70°C PD 800 mW
Thermal Resistance, Junction–to–Air RθJA 100 °C/W
Operating Junction Temperature TJ +150 °C
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Operating Ambient Temperature TA °C

MC34129 0 to +70
MC33129 –40 to +85
Storage Temperature Range Tstg –65 to +150 °C

ELECTRICAL CHARACTERISTICS (VCC = 10 V, TA = 25°C [Note 1], unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit
REFERENCE SECTIONS
Reference Output Voltage, TA = 25°C Vref V
1.25 V Ref., IL = 0 mA 1.225 1.250 1.275
2.50 V Ref., IL = 1.0 mA 2.375 2.500 2.625
Reference Output Voltage, TA = Tlow to Thigh Vref V
1.25 V Ref., IL = 0 mA 1.200 – 1.300
2.50 V Ref., IL = 1.0 mA 2.250 – 2.750
Line Regulation (VCC = 4.0 V to 12 V) Regline mV
1.25 V Ref., IL = 0 mA – 2.0 12
2.50 V Ref., IL = 1.0 mA – 10 50
Load Regulation Regload mV
1.25 V Ref., IL = –10 µA to +500 µA – 1.0 12
2.50 V Ref., IL = –0.1 mA to +1.0 mA – 3.0 25
ERROR AMPLIFIER
Input Offset Voltage (Vin = 1.25 V) VIO mV
TA = 25°C – 1.5 –
TA = Tlow to Thigh – – 10
Input Offset Current (Vin = 1.25 V) IIO – 10 – nA
Input Bias Current (Vin = 1.25 V) IIB nA
TA = 25°C – 25 –
TA = Tlow to Thigh – – 200
Input Common Mode Voltage Range VICR – 0.5 to 5.5 – V
Open Loop Voltage Gain (VO = 1.25 V) AVOL 65 87 – dB
Gain Bandwidth Product (VO = 1.25 V, f = 100 kHz) GBW 500 750 – kHz
Power Supply Rejection Ratio (VCC = 5.0 V to 10 V) PSRR 65 85 – dB
Output Source Current (VO = 1.5 V) ISource 40 80 – µA
Output Voltage Swing V
High State (ISource = 0 µA) VOH 1.75 1.96 2.25
Low State (ISink = 500 µA) VOL – 0.1 0.15
NOTE: 1. Tlow = 0°C for MC34129 Thigh = +70°C for MC34129
–40°C for MC33129 +85°C for MC33129

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ELECTRICAL CHARACTERISTICS (VCC = 10 V, TA = 25°C [Note 1], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
PWM COMPARATOR
Input Offset Voltage (Vin = 1.25 V) VIO 150 275 400 mV
Input Bias Current IIB – –120 –250 µA
Propagation Delay, Ramp Input to Drive Output tPLH(IN/DRV) – 250 – ns
SOFT–START
Capacitor Charge Current (Pin 12 = 0 V) Ichg 0.75 1.2 1.50 µA
Buffer Input Offset Voltage (Vin = 1.25 V) VIO – 15 40 mV
Buffer Output Voltage (ISink = 100 µA) VOL – 0.15 0.225 V
FAULT TIMER
Restart Delay Time tDLY 200 400 600 µs
START/RUN COMPARATOR
Threshold Voltage (Pin 12) Vth – 2.0 – V
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Threshold Hysteresis Voltage (Pin 12) VH – 350 – mV

Output Voltage (ISink = 500 µA) VOL 9.0 10 10.3 V
Output Off–State Leakage Current (VOH = 15 V) IS/R(leak) – 0.4 2.0 µA
Output Zener Voltage (IZ = 10 mA) VZ – (VCC + 7.6) – V
OSCILLATOR
Frequency (RT = 25.5 kΩ, CT = 390 pF) fOSC 80 100 120 kHz
Capacitor CT Discharge Current (Pin 5 = 1.2 V) Idischg 240 350 460 µA
Sync Input Current µA
High State (Vin = 2.0 V) IIH – 40 125
Low State (Vin = 0.8 V) IIL – 15 35
Sync Input Resistance Rin 12.5 32 50 kΩ
DRIVE OUTPUT
Output Voltage V
High State (ISource = 200 mA) VOH 8.3 8.9 –
Low State (ISource = 200 mA) VOL – 1.4 1.8
Low State Holding Current IH – 225 – µA
Output Voltage Rise Time (CL = 500 pF) tr – 390 – ns
Output Voltage Fall Time (CL = 500 pF) tf – 30 – ns
Output Pull–Down Resistance RPD 100 225 350 kΩ
UNDERVOLTAGE LOCKOUT
Startup Threshold Vth 3.0 3.6 4.2 V
Hysteresis VH 5.0 10 15 %
TOTAL DEVICE
Power Supply Current ICC 1.0 2.5 4.0 mA
RT = 25.5 kΩ, CT = 390 pF, CL = 500 pF

Power Supply Zener Voltage (IZ = 10 mA) VZ 12 14.3 – V

NOTE: 1. Tlow = 0°C for MC34129 Thigh = +70°C for MC34129
–40°C for MC33129 +85°C for MC33129

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Figure 1. Timing Resistor versus Figure 2. Output Deadtime versus

Oscillator Frequency Oscillator Frequency
1.0 M 100

%DT, PERCENT OUTPUT DEAD–TIME

VCC = 10 V 2.0 nF 1.0 nF 500 pF 200 pF
500 k 50 CT = 5.0 nF
TA = 25°C
R T , TIMING RESISTOR ( Ω )

100 pF

200 k 20

100 k

50 k 5.0

20 k 2.0 VCC = 10 V
100pF
TA = 25°C
CT = 5.0 nF 2.0 nF 1.0 nF 500 pF 200 pF
10 k 1.0
5.0 10 20 50 100 200 500 5.0 10 20 50 100 200 500
fOSC, OSCILLATOR FREQUENCY (kHz) fOSC, OSCILLATOR FREQUENCY (kHz)
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Figure 3. Oscillator Frequency Change Figure 4. Error Amp Open Loop Gain and
versus Temperature Phase versus Frequency
∆ f OSC, OSCILLATOR FREQUENCY CHANGE (%)

60 0
8.0 VCC = 10 V A VOL , OPEN LOOP VOLTAGE GAIN (dB) VCC = 10 V
RT = 25.5 k VO = 1.25 V

φ, EXCESS PHASE (DEGREES)

CT = 390 pF RL = ∞
40 TA = 25°C 45
4.0 Gain

20 Phase
0 90

–4.0
0 135

–8.0
–20 180
–55 –25 0 25 50 75 100 125 1.0 k 10 k 100 k 1.0 M 10 M
TA, AMBIENT TEMPERATURE (°C) f, FREQUENCY (Hz)

Figure 5. Error Amp Small–Signal Figure 6. Error Amp Large–Signal

Transient Response Transient Response

TA = 25°C TA = 25°C
1.05 V 1.5 V
200 mV/DIV
20 mV/DIV

1.0 V 1.0 V

0.95 V 0.5 V

0.5 µs/DIV 1.0 µs/DIV

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Figure 7. Error Amp Open Loop DC Gain Figure 8. Error Amp Output Saturation
versus Load Resistance versus Sink Current
90 1.0

V sat , OUTPUT SATURATION VOLTAGE (V)

A VOL, OPEN LOOP VOLTAGE GAIN (dB)

VCC = 10 V
Pins 8 to 9, 6 to 10
0.8 Pins 2, 5, 7 to Gnd
80
TA = 25°C
0.6
70
0.4

60 VCC = 10 V
VO = 1.25 V 0.2
RL to 1.25 Vref
TA = 25°C
50 0
0 20 40 60 80 100 0 2.0 4.0 6.0 8.0
RL, OUTPUT LOAD RESISTANCE (kΩ) ISink, OUTPUT SINK CURRENT (mA)
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Figure 9. Soft–Start Buffer Output Saturation Figure 10. Reference Output Voltage versus
versus Sink Current Supply Voltage
1.0 3.2

V ref , REFERENCE OUTPUT VOLTAGE (V)

V sat , OUTPUT SATURATION VOLTAGE (V)

TA = 25°C
VCC = 10 V Vref 2.5 V, RL = 2.5 k
Pins 8 to 9
0.8 2.4
Pins 2, 5, 7, 10, 12 to Gnd
TA = 25°C
0.6
1.6 Vref 1.25 V, RL = ∞
0.4

0.8
0.2

0 0
0 100 200 300 400 500 0 4.0 8.0 12 16
ISink, OUTPUT SINK CURRENT (µA) VCC, SUPPLY VOLTAGE (V)

Figure 11. 1.25 V Reference Output Voltage Figure 12. 2.5 V Reference Output Voltage
∆ V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)

∆ V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)

Change versus Source Current Change versus Source Current

0 0
VCC = 10 V VCC = 10 V
–4.0 –4.0

–8.0 –8.0

–12 +25°C –12

TA = – 40°C +85°C
TA = – 40°C 25°C 85°C
–16 –16

–20 –20

–24 –24
0 2.0 4.0 6.0 8.0 10 0 0.4 0.8 1.2 1.6 2.0
Iref, REFERENCE OUTPUT SOURCE CURRENT (mA) Iref, REFERENCE OUTPUT SOURCE CURRENT (mA)

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Figure 13. 1.25 V Reference Output Voltage Figure 14. 2.5 V Reference Output Voltage
∆ V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)

∆ V ref , REFERENCE OUTPUT VOLTAGE CHANGE (mV)

versus Temperature versus Temperature
*Vref = 1.225 V *Vref = 1.250 V *Vref = 1.275 V *Vref = 2.375 V *Vref = 2.500 V *Vref = 2.625 V
0 0

–2.0 4.0

–4.0 8.0

–6.0 –12
VCC = 10 V VCC = 10 V
RL = ∞ RL = 2.5 k
–8.0 *Vref at TA = 25°C –16 *Vref at TA = 25°C

–10 –20
–55 –25 0 25 50 75 100 125 –55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (°C) TA, AMBIENT TEMPERATURE (°C)
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Figure 15. Drive Output Saturation

versus Load Current Figure 16. Drive Output Waveform
0
R
V sat , OUTPUT SATURATION VOLTAGE (V)

VCC VCC = 10 V 10 RL =
–1.0 TA = 25°C CL = 500 pF
TA = 25°C
–2.0 Source Saturation
(Load to Ground)

2.0 V/DIV
–3.0

3.0 Sink Saturation

(Load to VCC)
2.0

1.0 0
Gnd
0
0 200 400 600 800 1.0 µs/DIV
IO, OUTPUT LOAD CURRENT (mA)

Figure 17. Supply Current versus Supply Voltage

10
RT = 25.5 k
I CC , SUPPLY CURRENT (mA)

CT = 390 pF
8.0 TA = 25°C

6.0

4.0
CL = 500 pF

2.0
CL = 15 pF

0
0 4.0 8.0 12 16
VCC, SUPPLY VOLTAGE (V)

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PIN FUNCTION DESCRIPTION
Pin Function Description
1 Drive Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are
sourced and sinked by this pin.

2 Drive Ground This pin is a separate power ground return that is connected back to the power source. It is
used to reduce the effects of switching transient noise on the control circuitry.

3 Ramp Input A voltage proportional to the inductor current is connected to this input. The PWM uses this
information to terminate output switch conduction.

4 Sync/Inhibit Input
5 RT/CT
6 Vref 2.50 V
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A rectangular waveform applied to this input will synchronize the Oscillator and limit the
maximum Drive Output duty cycle. A dc voltage within the range of 2.0 V to VCC will inhibit
the controller.
The free–running Oscillator frequency and maximum Drive Output duty cycle are
programmed by connecting resistor RT to Vref 2.5 V and capacitor CT to Ground. Operation
to 300 kHz is possible.
This output is derived from Vref 1.25 V. It provides charging current for capacitor CT through
resistor RT.

7 Ground This pin is the control circuitry ground return and is connected back to the source ground.
8 Vref 1.25 V This output furnishes a voltage reference for the Error Amplifier noninverting input.
9 Error Amp Noninverting Input This is the noninverting input of the Error Amplifier. It is normally connected to the 1.25 V
reference.

10 Error Amp Inverting Input This is the inverting input of the Error Amplifier. It is normally connected to the switching
power supply output through a resistor divider.

11 Feedback/PWM Input This pin is available for loop compensation. It is connected to the Error Amplifier and
Soft–Start Buffer outputs, and the Pulse Width Modulator input.

12 CSoft–Start A capacitor CSoft–Start is connected from this pin to Ground for a controlled ramp–up of peak
inductor current during startup.

13 Start/Run Output This output controls the state of an external bootstrap transistor. During the start mode,
operating bias is supplied by the transistor from Vin. In the run mode, the transistor is
switched off and bias is supplied by an auxiliary power transformer winding.
14 VCC This pin is the positive supply of the control IC. The controller is functional over a minimum
VCC range of 4.2 V to 12 V.

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OPERATING DESCRIPTION
The MC34129 series are high performance current mode
switching regulator controllers specifically designed for use in
low power telecommunication applications. Implementation
will allow remote digital telephones and terminals to shed
their power cords and derive operating power directly from
the twisted pair used for data transmission. Although these
devices are primarily intended for use in digital telephone
systems, they can be used cost effectively in a wide range of
converter applications. A representative block diagram is
shown in Figure 18.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 2.5 V reference through resistor RT to
approximately 1.25 V and discharged by an internal current
sink to ground. During the discharge of CT, the oscillator
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generates an internal blanking pulse that holds the lower
input of the NOR gate high. This causes the Drive Output to
be in a low state, thus producing a controlled amount of
output deadtime. Figure 1 shows Oscillator Frequency
versus RT and Figure 2 Output Deadtime versus Frequency,
both for given values of CT. Note that many values of RT and
CT will give the same oscillator frequency but only one
combination will yield a specific output deadtime at a give
frequency. In many noise sensitive applications it may be
desirable to frequency–lock one or more switching regulators
to an external system clock. This can be accomplished by
applying the clock signal to the Synch/Inhibit Input. For
reliable locking, the free–running oscillator frequency should
be about 10% less than the clock frequency. Referring to the
timing diagram shown Figure 19, the rising edge of the clock
signal applied to the Sync/Inhibit Input, terminates charging
of CT and Drive Output conduction. By tailoring the clock
waveform, accurate duty cycle clamping of the Drive Output
can be achieved. A circuit method is shown in Figure 20. The
Sync/Inhibit Input may also be used as a means for system
shutdown by applying a dc voltage that is within the range of
2.0 V to VCC.
PWM Comparator and Latch
The MC34129 operates as a current mode controller
whereby output switch conduction is initiated by the oscillator
and terminated when the peak inductor current reaches a
threshold level established by the output of the Error Amp or
Soft–Start Buffer (Pin 11). Thus the error signal controls the
peak inductor current on a cycle–by–cycle basis. The PWM
Comparator–Latch configuration used, ensures that only a
single pulse appears at the Drive Output during any given
oscillator cycle. The inductor current is converted to a voltage
by inserting the ground–referenced resistor RS in series with
the source of output switch Q1. The Ramp Input adds an
offset of 275 mV to this voltage to guarantee that no pulses
appear at the Drive Output when Pin 11 is at its lowest state.
This occurs at the beginning of the soft–start interval or when
the power supply is operating and the load is removed. The
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peak inductor current under normal operating conditions is
controlled by the voltage at Pin 11 where:
V(Pin 11) – 0.275 V
Ipk =
RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the voltage at Pin 11 will be
internally clamped to 1.95 V by the output of the Soft–Start
Buffer. Therefore the maximum peak switch current is:
1.95 V – 0.275 1.675 V
Ipk(max) = =
RS RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method which adjusts this voltage in discrete
increments is shown in Figure 22. This method is possible
because the Ramp Input bias current is always negative
(typically –120 µA). A positive temperature coefficient equal
to that of the diode string will be exhibited by Ipk(max). An
adjustable method that is more precise and temperature
stable is shown in Figure 23. Erratic operation due to noise
pickup can result if there is an excessive reduction of the
clamp voltage. In this situation, high frequency circuit layout
techniques are imperative.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Ramp Input with a time
constant that approximates the spike duration will usually
eliminate the instability; refer to Figure 25.
Error Amp and Soft–Start Buffer
A fully–compensated Error Amplifier with access to both
inputs and output is provided for maximum design flexibility.
The Error Amplifier output is common with that of the
Soft–Start Buffer. These outputs are open–collector (sink
only) and are ORed together at the inverting input of the PWM
Comparator. With this configuration, the amplifier that
demands lower peak inductor current dominates control of
the loop. Soft–Start is mandatory for stable startup when
power is provided through a high source impedance such as
the long twisted pair used in telecommunications. It
effectively removes the load from the output of the switching
power supply upon initial startup. The Soft–Start Buffer is
configured as a unity gain follower with the noninverting input
connected to Pin 12. An internal 1.0 µA current source
charges the soft–start capacitor (CSoft–Start) to an internally
clamped level of 1.95 V. The rate of change of peak inductor
current, during startup, is programmed by the capacitor value
selected. Either the Fault Timer or the Undervoltage Lockout
can discharge the soft–start capacitor.
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Figure 18. Representative Block Diagram

Vin = 20V
Start/Run
Output
+ +
1.95V – Start/Run 13
VCC
Comparator 7.0V
Undervoltage
1.0µA Lockout 14
12 Fault Timer
VCC VCC
+
35k

PWM VCC 3.6V 14.3V

CSoft–Start Comparator
80µA
1.95V

+ 8
1.25V
7 – Reference
+
275mV 9 Noninverting
2.5V Reference + + Input
6 + 1.25V 10 Inverting
– Error Amp –
– Input
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R VCC Feedback/PWM
Soft–Start 11 Input
Buffer
RT R Latch Q1
R 1 Drive Output
Q

225k
5
Oscillator S 2
CT Drive
Gnd
4 3

Sync/Inhibit Input Ramp Input

32k RS

+ Sink Only
– = Positive True Logic

Figure 19. Timing Diagram

600 µs Delay

Sync/Inhibit Input

Capacitor CT

Latch
“Set” Input

Feedback/PWM Input

Ramp Input
Latch
“Reset” Input

Drive Output

20 V
Start/Run
Output
14.3 V

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Fault Timer
This unique circuit prevents sustained operating in a
lockout condition. This can occur with conventional switching
control ICs when operating from a power source with a high
series impedance. If the power required by the load is greater
than that available from the source, the input voltage will
collapse, causing the lockout condition. The Fault Timer
provides automatic recovery when this condition is detected.
Under normal operating conditions, the output of the PWM
Comparator will reset the Latch and discharge the internal
Fault Timer capacitor on a cycle–by–cycle basis. Under
operating conditions where the required power into the load is
greater than that available from the source (Vin), the Ramp
Input voltage (plus offset) will not reach the comparator
threshold level (Pin 11), and the output of the PWM
Comparator will remain low. If this condition persists for more
that 600 µs, the Fault Timer will active, discharging CSoft–Start
and initiating a soft–start cycle. The power supply will operate
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in a skip cycle or hiccup mode until either the load power or
source impedance is reduced. The minimum fault timeout is
200 µs, which limits the useful switching frequency to a
minimum of 5.0 kHz.
Start/Run Comparator
A bootstrap startup circuit is included to improve system
efficiency when operating from a high input voltage. The
output of the Start/Run Comparator controls the state of an
external transistor. A typical application is shown in Figure 21.
While CSoft–Start is charging, startup bias is supplied to VCC
(Pin 14) from Vin through transistor Q2. When
CSoft–Start reaches the 1.95 V clamp level, the Start–Run
output switches low (VCC = 50 mV), turning off Q2. Operating
bias is now derived from the auxiliary bootstrap winding of the
transformer, and all drive power is efficiently converted down
from Vin. The start time must be long enough for the power
supply output to reach regulation. This will ensure that there
is sufficient bias voltage at the auxiliary bootstrap winding for
sustained operation.
1.95 V CSoft–Start
tStart = = 1.95 CSoft–Start in µF
1.0 µA
The Start/Run Comparator has 350 mV of hysteresis. The
output off–state is clamped to VCC + 7.6 V by the internal
zener and PNP transistor base–emitter junction.
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Drive Output and Drive Ground
The MC34129 contains a single totem–pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current and
has a typical fall time of 30 ns with a 500 pF load. The
totem–pole stage consists of an NPN transistor for turn–on
drive and a high speed SCR for turn–off. The SCR design
requires less average supply current (ICC) when compared to
conventional switching control ICs that use an all NPN
totem–pole. The SCR accomplishes this during turn–off of
the MOSFET, by utilizing the gate charge as regenerative
on–bias, whereas the conventional all transistor design
requires continuous base current. Conversion efficiency in
low power applications is greatly enhanced with this
reduction of ICC. The SCR’s low–state holding current (IH) is
typically 225 µA. An internal 225 kΩ pull–down resistor is
included to shunt the Drive Output off–state leakage to
ground when the Undervoltage Lockout is active. A separate
Drive Ground is provided to reduce the effects of switching
transient noise imposed on the Ramp Input. This feature
becomes particularly useful when the Ipk(max) clamp level is
reduced. Figure 24 shows the proper implementation of the
MC34129 with a current sensing power MOSFET.
Undervoltage Lockout
The Undervoltage Lockout comparator holds the Drive
Output and CSoft–Start pins in the low state when VCC is less
than 3.6 V. This ensures that the MC34129 is fully functional
before the output stage is enabled and a soft–start cycle
begins. A built–in hysteresis of 350 mV prevents erratic
output behavior as VCC crosses the comparator threshold
voltage. A 14.3 V zener is connected as a shunt regulator
from VCC to ground. Its purpose is to protect the MOSFET
gate from excessive drove voltage during system startup. An
external 9.1 V zener is required when driving low threshold
MOSFETs. Refer to Figure 21. The minimum operating
voltage range of the IC is 4.2 V to 12 V.
References
The 1.25 V bandgap reference is trimmed to ±2.0%
tolerance at TA = 25°C. It is intended to be used in
conjunction with the Error Amp. The 2.50 V reference is
derived from the 1.25 V reference by an internal op amp with
a fixed gain of 2.0. It has an output tolerance of ±5.0% at TA =
25°C and its primary purpose is to supply charging current to
the oscillator timing capacitor.
For further information, please refer to AN976.
MOTOROLA ANALOG IC DEVICE DATA
 Freescale Semiconductor,
MC34129 MC33129 Inc.

Figure 20. External Duty Cycle Clamp Figure 21. Bootstrap Startup
and Multi–Unit Synchronization Vin

6 2.5V
+ + 13
– – Q2

CSoft–Start 14
–+ 9.1
12 +
5.0V V
5 8
7
+– 1.25V
RA OSC
8 4 9
+– +
RB 5.0k 6 2.5V –
+
4 +– 10
6 R
5 – 3 11
5.0k Q
R 1
2 + 7 Q
– S 5
OSC S 2
To Additional
5.0k MC1455 MC34129’s
C 4 3
1
Freescale Semiconductor, Inc...

1.44 RB
f= Dmax = The external 9.1 V zener is required when driving low threshold MOSFETs.
(RA + 2RB)C RA + 2RB

Figure 22. Discrete Step Reduction of Clamp Level Figure 23. Adjustable Reduction of Clamp Level
Vin
Vin 8
8 1.25V
1.25V 9
9 + + +
+ + 275mV 10
275mV
+ – – R2
– 10
–
11
11
R1
Q1
Q1 R 1
R 1 Q
Q S 2
S 2
3
3 D1 D2
RS
≈ 120µA RS

1.25
1.675 – (VF(D1) + VF(D2)) – 0.275
Ipk(max) = R2
RS +1
R1
1.25 V
If: ≥ 1.0 mA Then: Ipk(max) ≈
R1 + R2 RS

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DATA 11
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Figure 24. Current Sensing Power MOSFET Figure 25. Current Waveform Spike Suppression

Vin RS ⋅ Ipk ⋅ rDS(on)

8 VRS ≈
rDM(on) + rS
1.25V Vin
9 If: SENSEFET = MTP10N10M
+ RS = 200
– Then: VRS ≈ 0.075 Ipk
10
D Q1
1
SENSEFET
11

2
1 S
G K 3 R
M
2
C RS
3
Power Ground:
To Input Source
RS Return
1/4W
The addition of the RC filter will eliminate instability caused by the
Control Circuitry Ground: leading edge spike on the current waveform.
Freescale Semiconductor, Inc...

To Pin 7

Virtually lossless current sensing can be achieved with the implementation of a

SENSEFET power switch.

Figure 26. MOSFET Parasitic Oscillations Figure 27. Bipolar Transistor Drive

IB
Vin
Vin +

0 t

– Base Charge
Removal
Q1
1 Rg C1

1
Q1
2
2
3

3
RS

RS

Series gate resistor Rg will damp any high frequency parasitic The totem–pole output can furnish negative base current for enhanced
oscillations caused by the MOSFET input capacitance and any transistor turn–off, with the addition of capacitor C1.
series wiring inductance in the gate–source circuit.

12 For More Information On This Product,

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Figure 28. Non–Isolated 725 mW Flyback Regulator

Vin = 20V to 48V

+
220k 2.2k 50
+ 13
2N5551
–

14 1N4148
12 +
– + 10 1N5819

5V/125mA
1N958A T1
0.1 +
+ 8 36k 100
1.25V R2
7 –
9 Gnd
+ +
10
– –
6 2.5 V +
+ 12k 100
500pF
– R1
Freescale Semiconductor, Inc...

11
–5V/20mA
24k
1 1N5819
R
Q MTP
5
2 2N20L
OSC S
470pF
T1: Coilcraft #G6807–A
4 3
Primary = 90T #28 AWG
Secondary ±5V = 26T #30 AW
128kHz 10
Gap = 0.05 n, for Lp of 600 µH
Sync
Core = Ferroxcube 813E187–3C8
Bobbin = Ferroxcube E187PCB1–8

Test Conditions Results

Line Regulation 5.0 V Vin = 20 V to 40 V, Iout 5.0 V = 125 mA, Iout –5.0 V = 20 mA ∆ = 1.0 mV
Load Regulation 5.0 V Vin = 30 V, Iout 5.0 V = 0 mA to 150 mA, Iout –5.0 V = 20 mA ∆ = 2.0 mV
Output Ripple 5.0 V Vin = 30 V, Iout 5.0 V = 125 mA, Iout –5.0 V = 20 mA 150 mVpp
Efficiency Vin = 30 V, Iout 5.0 V = 125 mA, Iout –5.0 V = 20 mA 77%

R2
Vout = 1.25 +1
R1

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DATA 13
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Figure 29. Isolated 2.0 W Flyback Regulator

220k Vin = 20V to 48V

+
2.2k 100
+ 13
2N5551
–

14 1N5819 180 1N5819 5V/380mA

12 pF
+
1N5819
– T1 +
+
2 100
0.1
+ 8
7 1.25V 0.1 140k Gnd
– 9 330 +
+ +
100
6 2.5V – –
+ 10 20k
–
1N5819 –5V/20mA
11
24k
R 1

5 Q MTP
Freescale Semiconductor, Inc...

OSC S 2 2N20
470pF
4 3
128kHz
Sync
100pF

2.7k 100
0.1
1 6
10k
T1: Primary = 35T #32 AWG
Feedback = 12T #32 AWG
4 Secondary ±5 V = 7T #32 AWG
Gap = 0.004″, for Lp of 180 µH
2 5 Core = Ferroxcube 813E187–3C8
MOC5007
Bobbin = Ferroxcube E187PCB1–8

Test Conditions Results

Line Regulation 5.0 V Vin = 20 V to 40 V, Iout 5.0 V = 380 mA, Iout –5.0 V = 20 mA ∆ = 1.0 mV
Load Regulation 5.0 V Vin = 30 V, Iout 5.0 V = 100 mA to 380 mA, Iout –5.0 V = 20 mA ∆ = 15 mV
Output Ripple 5.0 V Vin = 30 V, Iout 5.0 V = 380 mA, Iout –5.0 V = 20 mA 150 mVpp
Efficiency Vin = 30 V, Iout 5.0 V = 380 mA, Iout –5.0 V = 20 mA 73%

14 For More Information On This Product,

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MC34129 MC33129 Inc.

Figure 30. Isolated 3.0 W Flyback Regulator with Secondary Side Sensing

Vin = 12V

L1
+ 13 1N5821 5/60mA
–

3.9k
14
12 51
100 + 1/2 +
4N26 100
470
0.1 0.1
+ 8

3.9k
7 – 1.25V
9
+ +
– – D TL431A Return
6 2.5V + 10
– MTP10N10M
11
2.2k
15k

R 1 G S
Q
Freescale Semiconductor, Inc...

5 M K
OSC S 2

4 3 T1: Primary = 22T #18 AWG

Secondary = 22T #18 AWG
0.002
510

Lp = 50 µH

0.001
1/2

200
Core = Ferroxcube
4N26 2616PA100–3C8
L1: Bobbin = Ferroxcube 2616F1D
Coilcraft Z7156, 15 µH

Test Conditions Results

Line Regulation Vin = 8.0 V to 12 V, Iout 600 mA ∆ = 1.0 mV
Load Regulation Vin = 12 V, Iout = 100 mA to 600 mA ∆ = 8.0 mV
Output Ripple Vin = 12 V, Iout = 600 mA 20 mVpp
Efficiency Vin = 12 V, Iout = 600 mA 81%

An economical method of achieving secondary sensing is to combine the TL431A with a 4N26 optocoupler.

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DATA 15
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 Freescale Semiconductor,
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OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
14 8 MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
B FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
1 7 FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
F L B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
C G 0.100 BSC 2.54 BSC
H 0.052 0.095 1.32 2.41
J J 0.008 0.015 0.20 0.38
N K 0.115 0.135 2.92 3.43
Freescale Semiconductor, Inc...

L 0.300 BSC 7.62 BSC

SEATING
PLANE K M 0_ 10_ 0_ 10_
H G D M N 0.015 0.039 0.39 1.01

D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14) NOTES:
ISSUE F 1. DIMENSIONING AND TOLERANCING PER
–A– ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14 8 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
–B– P 7 PL 5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
1 7
0.25 (0.010) M B M PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS INCHES
G R X 45 _ F DIM MIN MAX MIN MAX
C A 8.55 8.75 0.337 0.344
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
–T– F 0.40 1.25 0.016 0.049
K M J G 1.27 BSC 0.050 BSC
SEATING D 14 PL
PLANE J 0.19 0.25 0.008 0.009
0.25 (0.010) M T B S A S K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.228 0.244
R 0.25 0.50 0.010 0.019

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
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Opportunity/Affirmative Action Employer.

How to reach us:

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1 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

For More Information On This Product,

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16 ◊ MOTOROLA ANALOG IC DEVICE DATA
MC34129/D
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