RTL to GDS Flow Automation

This document gives a brief description of how to generate a GDS for your design given a
RTL. The RTL is taken through various steps broadly divided into two :-
1. Logic Synthesis- Conversion of RTL to an equivalent netlist. Here netlist specifies the cells
and the interconnections between them.
2. Physical Design- Conversion of netlist to an equivalent GDS. GDS is a file that contains
geometrical information for designing masks in the foundry.

Figure 1: RTL to GDS Flow

How to get from RTL to GDS would be explained in the following steps: -

Step -1: Initially the design environment needs to be setup.

1. Open the terminal from the ‘scripts’ directory. Assume that ‘Scripts’ is a directory where

all the script files are saved.

2. Type ‘tcsh’ to change the shell from bash to T shell.

3. Source the cad files using ‘source /cad/cshrc’. (Note the space after source)

A ‘Welcome to Cadence Tools’ message is displayed on the shell.

4. Run the setup_script.tcl file by typing ‘tclsh setup_script.tcl’, this runs the tcl file using

the tcl interpreter. The following directories are created when this file is run.
 Figure 2: Initial Setup

5. Create a directory with name ‘90’ in the lib folder if you are going to use 90nm library

files. Put the 90 nm library files into this directory. The 90nm library files are available at

this path : /cad/FOUNDRY/digital/90nm/dig/lib. Libraries for different technology nodes

are available at : /cad/FOUNDRY/digital.

6. Put the constraints file into the ‘constraints’ directory and put the RTL files and

testbench into the ‘rtl’ directory.

Step-2 : Compile, Elaborate, Simulate and generate code coverage data for the design using Incisive

Simulation tool

Simulation is performed to check the functionality of the design.

1. Source the compile_elaborate_simulate.tcl file.

The compile_elaborate_simulate.tcl file is given in the appendix. The ncsim tool uses

simulation.tcl file as input. A cov_work folder is created which contains the code coverage

data.

Step-3 : Generate code coverage report

1. To invoke the ICCR (Incisive Comprehensive Coverage Tool) type ‘iccr name_of_tcl_file’

in the shell. Here the tcl file is iccr_tcl.tcl. The commands in the file are given in the
 appendix. If you want the tool to run in gui mode, type ‘-gui’ along with the tool invocation

command.

Two report files are generated namely detail.rpt and summary.rpt.

Step-4: LOGIC SYNTHESIS AND DESIGN FOR TEST(DFT) - Synthesise netlist and generate timing,

power and area reports. (Logic Synthesis)

Figure 3: Logic Synthesis

1. For synthesis RTL Compiler is used. To invoke the tool type ‘rc -bg -files name_of_tcl_file’.

Here the tcl file is rc_script.tcl. The dft_script.tcl is used if you want to insert scan chains

in your design for Post-Si testing. The commands in the file are given in the appendix. The

-bg option is to run the tool in background mode without showing the gui. If you want the

tool to run with GUI remove the -bg option.

Step -5 : Equivalence Checking

1. Make a directory ‘logical_eq_check’ in the scripts directory for storing all the report files

generated during equivalence checking.

2. For equivalence checking Conformal is used. To invoke the tool type ‘lec -lp -dofile

name_of_dofile’. Here the dofile is logical_eq_check.do. The commands in the file are

given in the appendix. The first command switches Off the gui , if you want the tool to run

in gui mode, you can comment that line.

Step -6 : Static Timing Analysis

a) Using Tempus

Type ‘/cad/SSV/bin/tempus -nowin -file sta_cad_after_synthesis.tcl’ to run the tempus tool

and execute the tcl script file. The tcl script file used is sta_cad_after_synthesis.tcl given in

appendix.

b) Using PrimeTime

Type ‘pt_shell’ on the terminal. Source ‘primetime_script.tcl’. The timing reports are

generated separately for setup(max) and hold checks(min).

Step -7: Physical Design

Figure 4: Physical Design

Inputs
1. Input-output assignment file
2. LEF file
3. Netlist from logic synthesis
4. View file which contains the delay corners, constraints etc. to be used. A sample view file is
given in the appendix (n).
 Type ‘encounter -file encounter_script.tcl’ file in the shell. The script will do floorplanning,
placement, global routing, detail routing, generate timing reports after CTS and routing.
Finally, it will generate the GDS for the given RTL, final netlist and DEF file which can be used
for power analysis etc.
Step-8 : Power Analysis using Voltus Tool
a) Type ‘/cad/SSV/bin/voltus -no_gui -file voltus_power_analysis_script.tcl’ to run the voltus

tool and execute the tcl script file. The tcl script file used is voltus_power_analysis_script.tcl

given in appendix. It performs dynamic power analysis on the routed netlist.

Step-9 : Timing Sign-off Using Primetime

a) Using PrimeTime

Type ‘pt_shell’ on the terminal. Source ‘timing_sign_off_script.tcl’. It checks for setup and

hold violations using the netlist and SDF file generated after physical design.
APPENDIX

a) Setup_script.tcl

1. #!/cad/PVS151/tools/bin/tclsh

2. file mkdir ../lib

3. file mkdir ../rtl

4. file mkdir ../constraints

5. file mkdir ../lib/worklib

6. set channelid [open ../lib/cds.lib w+]

7. puts $channelid {define worklib "./worklib"}

8. close $channelid

b) Compile_elaborate_Simulate.tcl

1. ncvlog -work worklib -cdslib ../lib/cds.lib -logfile ncvlog.log -errormax 15 -update

-linedebug -status ../rtl/rtl_topmodule.v

2. ncelab -work worklib -cdslib ../lib/cds.lib -logfile ncelab.log -errormax 15 -access

+wc -status worklib.rtl_module

3. ncvlog -work worklib -cdslib ../lib/cds.lib -logfile ncvlog.log -errormax 15 -update

-linedebug -status ../rtl/testbench.v

4. ncelab -work worklib -cdslib ../lib/cds.lib -logfile ncelab.log -errormax 15 -access

+wc -status -coverage block -coverage expr -coverage fsm -coverage toggle

worklib.test_module:module

5. ncsim -batch -cdslib ../lib/cds.lib -logfile ncsim.log -input simulation_cmd_file.tcl -

errormax 15 -status worklib.test_module:module

c) simulation.tcl

1. database -open waves -into waves.shm -default

 2. probe -create -shm -all -variables -depth all

3. run

d) iccr_tcl_file.tcl

1. load_test cov_work/scope/test

2. #<summary>

3. report_summary -module -bets * > summary.rpt

4. #</summary>

5. #<detail>

6. report_detail -module -both -bets * > detail.rpt

7. #</detail>

e) rc_script.tcl

1. set_attr lib_search_path ../lib/90

2. set_attr hdl_search_path ../rtl/

3. set_attr library slow.lib

4. read_hdl rtl_topmodule.v

5. elaborate

6. read_sdc ../constraints/constraints_top.sdc

7. synthesize -to_mapped -effort medium

8. write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge >

syn_report/delays.sdf

9. write_hdl > syn_report/synthesised_netlist.v

10. write_sdc > syn_report/dc_file_for_physical_design.sdc

11. write_script > syn_report/synthesis_script_sdc.g

12. report timing > syn_report/synthesis_timing_report.rep

13. report power > syn_report/synthesis_power_report.rep

14. report gates > syn_report/synthesis_cell_report.rep

 15. report area > syn_report/synthesis_area_report.rep

16. exit

f) dft_script.tcl

1. set_attr lib_search_path ../lib/90

2. set_attr hdl_search_path ../rtl/

3. set_attr library slow.lib

4. read_hdl rtl_topmodule.v

5. elaborate

6. read_sdc ../constraints/constraints_top.sdc

7. report timing -lint

8. set_attribute dft_scan_style muxed_scan

9. define_dft shift_enable -active high -create_port scan_en

10. define_dft test_mode -active high -create_port test_mode

11. define_dft test_clock clk

12. report dft_setup

13. check_dft_rules >dft_report/dft_rules_report

14. fix_dft_violations -test_control test_mode -async_set -async_reset -clock

15. synthesize -to_mapped

16. set_attr dft_min_number_of_scan_chains 2 rtl_module

17. set_attr dft_mix_clock_edges_in_scan_chains true rtl_module

18. #replace_scan

19. connect_scan_chains -auto_create_chains -preview

20. connect_scan_chains -auto_create_chains

21. report qor

22. write_atpg -cadence > rtl_module.atpg

 23. write_atpg -stil > rtl_module_still.atpg

24. write_scandef> dft_report/rtl_module.def

25. write_sdf -timescale ns -nonegchecks -recrem split -edges check_edge >

syn_report/delays.sdf

26. write_hdl > dft_report/synthesised_netlist.v

27. write_sdc > dft_report/sdc_file_for_physical_design.sdc

28. write_script > dft_report/synthesis_script_sdc.g

29. report timing > dft_report/synthesis_timing_report.rep

30. report power > dft_report/synthesis_power_report.rep

31. report gates > dft_report/synthesis_cell_report.rep

32. report area > dft_report/synthesis_area_report.rep

33. exit

34. #gui_show

g) logical_eq_check_script.tcl

1. file mkdir logical_eq_check

2. set_log_file logical_equivalence_checking.log -replace

3. read_library ../lib/90/slow.v -verilog -both

4. read_design ../rtl/rtl_topmodule.v -verilog -golden

5. read_design syn_report/synthesised_netlist.v -verilog -revised

6. set_system_mode lec

7. add_compared_points -all

8. compare

9. report_messages -compare -verb

10. report_compare_data -noneq

11. report_verification
 12. write_compared_points -replace logical_eq_check/lec_compared_points

13. write_mapped_points -replace logical_eq_check/lec_mapped_points

14. set_verification_information logical_eq_check

15. write_verification_information

16. exit

h) Sta_after_synthesis.tcl

1. file mkdir sta_after_synthesis/reports

2. set report_dir sta_after_synthesis/reports

3. read_lib ../lib/90/slow.lib

4. read_verilog syn_report/synthesised_netlist.v

5. set_top_module rtl_module

6. read_sdc ../constraints/constraints_top.sdc

7. check_timing > $report_dir/check_timing.rpt

8. report_timing > $report_dir/timing_report.rpt

9. report_analysis_coverage > $report_dir/analysis_coverage.rpt

10. report_analysis_summary > $report_dir/analysis_summary.rpt

11. #report_annotated_parasitics > $report_dir/annotated.rpt

12. report_clocks > $report_dir/clocks.rpt

13. report_case_analysis > $report_dir/case_analysis.rpt

14. report_constraints -all_violators > $report_dir/allviolations.rpt

15. #exit

i) primetime_script.tcl

1. set link_library ../lib/90/slow_new.db

2. read_verilog syn_report/synthesised_netlist.v
 3. link

4. source ../constraints/synopsys_constraints.sdc

5. check_timing

6. report_timing -slack_lesser_than 1000 -path_type full -input_pins -nets -

max_paths 200 -transition_time -capacitance -delay max >

timing_report_max

7. report_timing -slack_lesser_than 1000 -path_type full -input_pins -nets -

max_paths 200 -transition_time -capacitance -delay min > timing_report_min

8. start_gui

j) encounter_script.tcl

1. set init_gnd_net GND

2. set init_io_file pin_location.io

3. set init_lef_file ../lib/90/gsclib090_translated_ref.lef

4. set init_mmmc_file rtl_module.view

5. set init_pwr_net VDD

6. set init_top_cell rtl_module

7. set init_verilog syn_report/synthesised_netlist.v

8. init_design

9.

10. #/*Floorplanning*/

11. getIoFlowFlag

12. setIoFlowFlag 0

13. floorPlan -site gsclib090site -r 1 0.5 4.06 4.06 4.06 4.06

14.

15. #/*Power Planning*/

16. #/*Adding Rings*/

17. addRing -skip_via_on_wire_shape Noshape -skip_via_on_pin Standardcell -

center 1 -stacked_via_top_layer Metal9 -type core_rings -jog_distance 0.435

-threshold 0.435 -nets {GND VDD} -follow core -stacked_via_bottom_layer

Metal1 -layer {bottom Metal8 top Metal8 right Metal9 left Metal9} -width

1.25 -spacing 0.4 -offset 0.435

18.

19. #/*Adding Stripes*/

20. addStripe -skip_via_on_wire_shape Noshape -block_ring_top_layer_limit

Metal9 -max_same_layer_jog_length 0.88 -

padcore_ring_bottom_layer_limit Metal7 -number_of_sets 10 -

skip_via_on_pin Standardcell -stacked_via_top_layer Metal9 -

padcore_ring_top_layer_limit Metal9 -spacing 0.4 -merge_stripes_value

0.435 -layer Metal8 -block_ring_bottom_layer_limit Metal7 -width 0.44 -nets

{VDD GND} -stacked_via_bottom_layer Metal1

21.

22. #/*Placement*/

23. setPlaceMode -fp false

24. placeDesign

25.

26. #/*Clock Tree Synthesis*/

27.

28. createClockTreeSpec -bufferList {CLKBUFX12 CLKBUFX16 CLKBUFX2

CLKBUFX20 CLKBUFX3 CLKBUFX4 CLKBUFX6 CLKBUFX8 CLKINVX1 CLKINVX12

CLKINVX16 CLKINVX2 CLKINVX20 CLKINVX3 CLKINVX4 CLKINVX6 CLKINVX8} -

file Clock.ctstch
29. clockDesign -specFile Clock.ctstch -outDir clock_report -fixedInstBeforeCTS

30.

31. #/*Post-CTS timing report generation*/

32. #/*Setup Timing check*/

33. timeDesign -postCTS -pathReports -drvReports -slackReports -numPaths 50 -

prefix rtl_module_postCTS -outDir timingReports

34. #/*Hold Timing Check*/

35. timeDesign -postCTS -hold -pathReports -slackReports -numPaths 50 -prefix

rtl_module_postCTS -outDir timingReports

36.

37. #Optimizing design if timing violation

38. setOptMode -fixCap true -fixTran true -fixFanoutLoad false

39. optDesign -postCTS; # for setup violation

40. optDesign -postCTS -hold; #for hold violation

41.

42. #/*Global & Detail Routing*/

43. setNanoRouteMode -quiet -timingEngine {}

44. setNanoRouteMode -quiet -routeWithSiPostRouteFix 0

45. setNanoRouteMode -quiet -drouteStartIteration default

46. setNanoRouteMode -quiet -routeTopRoutingLayer default

47. setNanoRouteMode -quiet -routeBottomRoutingLayer default

48. setNanoRouteMode -quiet -drouteEndIteration default

49. setNanoRouteMode -quiet -routeWithTimingDriven false

50. setNanoRouteMode -quiet -routeWithSiDriven false

51. routeDesign -globalDetail

52.
53. #/*RC Extraction*/

54. extractRC

55. rcOut -setload rtl_module.setload

56. rcOut -setres rtl_module.setres

57. rcOut -spf rtl_module.spf

58. rcOut -spef rtl_module.spef

59.

60. #/*Writing SDF file with interconnect and gates delay*/

61. write_sdf -ideal_clock_network physical_design_rtl_module.sdf

62.

63. #/*Generating gate count report*/

64. #summaryReport -outdir summaryReport

65. reportGateCount -level 5 -limit 100 -outfile rtl_module.gateCount

66.

67. #/*Power Analysis*/

68. set_power_analysis_mode -reset

69. set_power_analysis_mode -method static -analysis_view view1 -corner max -

create_binary_db true -write_static_currents true -honor_negative_energy

true -ignore_control_signals true

70. set_power_output_dir -reset

71. set_power_output_dir ./

72. set_default_switching_activity -reset

73. set_default_switching_activity -input_activity 0.2 -period 10.0

74. read_activity_file -reset

75. set_power -reset

76. set_powerup_analysis -reset

 77. set_dynamic_power_simulation -reset

78. report_power -rail_analysis_format VS -outfile .//rtl_module.rpt

79.

80. #/*Generating GDS*/

81. streamOut rtl_module.gds -mapFile streamOut.map -libName DesignLib -

units 2000 -mode ALL

82.

83. #/*Saving the Design*/

84. saveNetlist rtl_module_post_route_netlist.v

85. defOut -floorplan -netlist -routing rtl_module.def

86. saveDesign new_uptoGDS.enc

k) Voltus_power_analysis_script.tcl

1. set period 4ns

2. set resolution 50ps

3. set input_activity 0.2

4. set seq_activity 0.15

5. read_lib -lef ../lib/90/gsclib090_translated_ref.lef

6. read_lib -min ../lib/90/slow.lib

7. read_lib -max ../lib/90/fast.lib

8. read_verilog rtl_module_postroute_netlist.v

9. set_top_module rtl_module

10. read_sdc ../constraints/constraints_top.sdc

11. read_def rtl_module.def

12. read_spef rtl_module.spef

13. #read_power_domain -cpf design.cpf

 14. set_power_analysis_mode -method dynamic_vectorless -disable_static false

15. #write_static_currents true

16. set_dynamic_power_simulation -period $period -resolution $resolution

17. set_default_switching_activity -input_activity $input_activity -seq_activity

$seq_activity

18. report_power -output voltus_power_reports

l) Timing_sign_off_script.tcl

1. set link_library ../lib/90/slow_new.db

2. read_verilog rtl_module_postroute_netlist.v

3. link

4. source ../constraints/synopsys_constraints.sdc

5. read_sdf physical_design_rtl_module.sdf

6. check_timing

7. report_timing -slack_lesser_than 1000 -path_type full -input_pins -nets -

max_paths 200 -transition_time -capacitance -delay max >

timing_sign_off_report_max

8. report_timing -slack_lesser_than 1000 -path_type full -input_pins -nets -

max_paths 200 -transition_time -capacitance -delay min >

timing_sign_off_report_min

9. start_gui
m) I/O Assignment file- An example

The direction of the pin location is specified as North(N), South(S), East(E) ,West(W), North-East(NE),

North-West(NW) and so on.

n) Sample View file for Encounter

1. # Version:1.0 MMMC View Definition File

2. # Do Not Remove Above Line

3. create_library_set -name timing_lib1 -timing {../lib/90/slow.lib}

4. create_constraint_mode -name sdc1 -sdc_files

{../constraints/constraints_top.sdc}

5. create_delay_corner -name delay1 -early_library_set {timing_lib1} -

late_library_set {timing_lib1}

6. create_analysis_view -name view1 -constraint_mode {sdc1} -delay_corner

{delay1}

7. set_analysis_view -setup {view1} -hold {view1}