M.

Tech
VLSI
Laboratory-I

ADVD
INTRODUCTION:

This document gives a overview of how to design & simulate with Mentor Graphics
tools.

There are five basic steps:

1. Design the schematic in Pyxis.

2. Simulate the schematic and check for parameters.
3. Layout the schematic in Pyxis.
4. Perform Physical Verification using Calibre which includes DRC, LVS and PEX
& Net list Extraction.
5. Back annotation of parasitics into the schematic.

INVOKING MENTOR TOOLS:

Right click on the Linux desktop and click on open in terminal.

Type csh and press enter.

Type source /home/software/cshrc/cshrc130.cshrc

Type cd /home/software/FOUNDRY/GDK/Pyxis_SPT_HEP
Type ./pyxismgr and press enter then pyxis project manager window will be invoked
as shown below.
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CREATING A PROJECT:

To create a new project click on File New project, this will invoke the new project window
as shown.

Select the project path in the project navigator

window. Select the root folder.

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Create a new directory and give the directory name as shown and click on OK.

Next technology libraries have to be added to the project. In order to add the
technology files browse on the folder as shown.

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Browse the folder to
root/software/FOUNDRY/GDK/Pyxis_SPT_HEP/ic_reflibs/tech_libs/generic13 file and
click on OK.

Again click on OK then manage external/logic libraries window will pop up as shown.
Click on the Add Standard Libraries. The libraries will be added up as shown below and click
on OK.

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Then the pyxis project manager window will be shown where the technology libraries are added
to the project and are placed below the project name.

CREATING A LIBRARY:

To create a library right click on the project name and select new library or click on the icon on

the icon bar.

Then a new library window will pop up asking for the library name.

Next name the library and click on OK.

CREATING A SCHEMATIC CELL VIEW:

To create a schematic cell view, a new cell has to be created in which new Schematic has to be
defined. In order to create new cell right click on the manual library below the project name
and select new cell or select the library and click on the iconin the icon bar.

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Then a new cell window will pop up asking for the cell name in which give the cell name
and click OK.

To create a schematic in the cell, right click on the cell name and select new
schematic or click on the new cell and select the icon in the icon bar.

A window will pop up asking for the schematic name.

Now name the schematic and click on OK which in turn leads to the pyxis
schematic editor window as shown.

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CREATING A SCHEMATIC:
In this section you will become familiar with placing primitive analog devices for a inverter.
You‟ll learn how to:
• place primitives on the schematic
• select and manipulate devices
• customizing hotkeys for placing devices
• route devices
• edit device parameter values
• name instances
• check and save the schematic
• create upper hierarchical symbols
• create test bench
• simulate using eldo
• view results

CREATING AN INVERTER:
Placing devices:
From the left icon bar press on add instance

icon or press „I‟

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Then a file browser which contains entire libraries will pop up as shown.

Next double click on generic13 in the library list.

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And then follow the path to select pmos from $generic13/symbols/pmos as shown in the figure.

Select the pmos and click on OK to place the pmos on the workspace as shown.

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And then follow the path to select nmos from $generic13/symbols/nmos as shown.

Select the nmos and click on OK to place the nmos on the workspace as shown.

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CHANGING DEVICE PROPERTIES:

In order to change the properties of the devices on the workspace click on the device then the
corresponding device properties will be shown in the object editor as shown.

Change the Width & Length values of the Transistors to

For PMOS : L = 0.13u; W=0.3u
For NMOS : L = 0.13u; W =0.15u

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Connect the circuit as shown below.

ADDING THE PORTS AND CONNECTING THE DEVICES:

Select generic library and place ground from the Instance window.
In the similar way place IN and OUT ports as above from the generic library.
Then the schematic would look as follows
For changing the port names click on the port and change the net name in the object editor to the
required name as shown below.

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After editing the schematic check for errors by selecting check & save option in the icon
bar.

This will result to an window which shows the error report where the errors and warnings in
the schematic can be seen in the Transcript Area.

GENERATING THE
SYMBOL:

Go to Add Generate
Symbol
Select Replace existing & activate symbol options. Click Ok.
Symbol gets generated for you.
Change the shape of symbol if required from choose shape.
Then click on OK which leads to the pyxis symbol window.
Save the symbol.

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After saving the symbol check for errors by selecting check and save option in the icon
bar.

This will result to an window which shows the error report where the errors and warnings in the
schematic can be seen in the Transcript Area.

TEST BENCH CREATION:

To create a test bench close all schematics and symbol windows and go back to pyxis project
manager window. In the project manager window to create a new cell right click on the
manual library below the project name and select new cell or select the library
and click on the icon in the icon bar.

Then a new cell window will pop up asking for the cell name in which give the cell
name and click OK.

Here the test bench cell name has been specified as inv_tb.

Right click on the test bench cell and select new schematic which in turn opens pyxis
Schematic editor window.
Add symbol of the schematic
made. AddInstanceChoose
Symbol.
Place the symbol on the work space as shown.

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Add a Pulse Source at the input to inverter and a DC Voltage source VDD port.
And do the necessary connections as per the figure given below.
Right click on the Pulse Source and select Edit Properties.
 Change the values of the below mentioned parameters and apply the changes.
 Initial = 0V Pulse = 5V Delay = 1nS Rise = 1nS
 Fall = 1nS Width = 25nS Period = 50ns.
Also change the magnitude of the Voltage Source from 1V to 5V by following the
below step.
Right Click on the Voltage source adjacent to VDD and then Edit properties

Next click on check & save icon in the icon bar.

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This will result to an window which shows the error report where the errors and warnings in
the symbol can be seen in the Trascript area.

SIMULATING THE SCHEMATIC:

SIMULATING TEST BENCH

When you have no errors select the simulation icon from the left icon palette to go into
the design context and simulate our design and select the run simulation.

Now in the design context we need to setup the analysis type, plots and load in the ELDO
models.

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Select a New configuration (Give a new name for the simulation).

Select ac, dc, tran from setup simulation window.

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Select Analysis setup and enable “DC” and ”Transient” and click on Apply.

Drop down the Analysis setup and select DC setup give the parameters as
 Select option Source
 Select the voltage source as V1
 Start: 0 Stop: 5 Step 0.1 and click on Apply.

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Select Transient Setup and change the Stop time to 1000N click on Apply.

Select the input path A and then hold CTRL key and then output path Y.

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Click on Edit Probes from the Setup Simulation. Select DC in Analysis tab, Plot from
Task tab. Select add.

Select TRAN from Analysis tab and select add and close the window.

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Select the symbol, and from the setup simulation select TRAN in Analysis tab,
Plot from task tab, power from type tab then save and select add.

Select libraries from setup simulation, edit libraries window will pop up.
Select import library and browse for library path to
/home/software/FOUNDRY/GDK/ Pyxis_SPT_HEP/ ic reflibs/tech
libs/generic13/models/lib.eldo

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Select Edit Corners/Families, from Library Corners tab check for TT
Click on Ok.

Select Edit Scenarios from Device Families tab check for TT

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After adding the analysis, libraries and edit probes minimize the setup simulation window
and run the simulator. To run the simulation select from the left icon palette or select
simulaterun simulation

View the simulation results by selecting the plot results from latest run icon from the
left icon palatte. This will open EZ Wave for you with the output waveforms.

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Click on Measurement tool in the icon bar which opens up the
measurement tool window where we can measure the different properties of your
waveforms.

Save these waveform as inv_ideal .

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CREATING A LAYOUT:
• To create a layout select inv cell. Right click on the cell and select New layout.

A new window named New layout will pop up, here the layout name is same as the cell name
as shown and click Ok.

Pyxis layout window will be invoked with a New layout sub-window in it and keep
the settings as shown and click on OK.

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Make the Schematic window active by selecting it with the Left Menu Bar. Select PMOS and
Press on the Pick & Place icon from the SDL tool bar on the Icon Bar. The tool will place
the device on the Workspace of IClayout window. Similarly select the NMOS and place it on
the workspace.

Note: To make SDL toolbar active, goto setup->toolbar->SDL tool

bar

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With the layout window active, select the Pick Place Ports icon from the SDL toolbar.

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Place Schematic ports window will pop up. Select the VDD port and select a layer for this port.
The Width and Height will be updated automatically according to the minimum metal1
dimensions. Press Apply to place the port.

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Place the rest of the ports.

To add the substrate contacts to the mosfets. Select Add Device icon from the Left Hand Palette,
then select Path-based Guard Band select psub

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Do the same for but choose nwell instead of psub

To add the over flow lines for both psub & nwell , Select psub then Connectivity > Net > Add
to Net to set psub to Ground and the same for nwell to set it to VDD

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ROUTING THE LAYOUT:

Manual routing:

To start routing press on the IRoute icon in the SDL toolbar. Once you place the cursor
on where you want to start routing, it will start guided by the fly lines. You can toggle between
the connectivity layers by pressing space-bar

Route all the ports in the layout except input port as

shown

For routing poly and input port of M1, VIA has to be

created.

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Routing Poly-M1
VIA CREATION:
Select Route in the ic palatte window as shown

Now select Options in ARoute Setup then following window will be invoked

Click on Advanced button in the ARoute Options window.

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Then Advanced route options window pops up, Select the VIA OPTIONS check use via
generator and click OK and OK.

Select Iroute, place POLYG at the input and start routing as shown. Now press SPACE BAR
automatically VIA will be created.

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Then complete layout for the inverter will be generated as shown.

PHYSICAL VERIFICATION OF LAYOUT:

1. DRC
2. LVS
3. PEX

1.DRC:
Now you can verify the layout by running DRC and LVS checks. We will run Calibre Interactive
RUNNING CALIBRE INTERACTIVE DRC:
In the pyxis layout window, Select ToolsCalibreRun DRC
This will bring up the Calibre Interactive – DRC

Note: Make sure the tabs named Rules, Inputs, Outputs, Run control should be green in color as
shown above which ensures the paths specified are correct. Otherwise paths have to be changed .

Select Run DRC in the Calibre Interactive window.

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The Calibre RVE window will popup and you should see the following results.

The error in the layout will be highlighted as shown in the fig once if you select on the error.

Here the error is due to the percentage of the polysilicon. It requires polyarea coverage of
14% which is not possible in the smaller circuits. So you can ignore that error.

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RUNNING LVS (Layout versus Schematic):

Before going to LVS, text the ports on the layout .In the pyxis window menu bar select
Add Text on Ports.

Add text on ports window will pop up. Here click on OK then automatically port names will be
assigned to layout.

LVS:

Select Tools Calibre Run LVS entry from the pull down
menu. The Calibre Interactive – LVS window will popup.
Inputs : layout browse for GDS file.
Check “Export from layout viewer” & “Export from schematic viewer” format.

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Select Run LVS in the Calibre Interactive window shown above.
Calibre RVE window will popup and you should see results similar to this.

If the comparison is wrong click on the comparison results in the RVE window, which shows
the results and select schematics then the netlists will be displayed as shown

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Click on the blocks of the Netlist of the schematic and layout which yields the circuits from you
can verify the connections and ports name and avoid the incorrect LVS.

RUNNING CALIBRE INTERACTIVE PEX:

Select Tools Calibre Run PEX from the menu.

The Calibre Interactive – PEX window will popup.
Make sure Export from schematic viewer is selected while the Inputs and Netlist tabs
are active as shown.

Choose the Outputs netlist to be in DSPF Format and select only R+C instead of R+C+C
from the Extraction Type as in the figure below.

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Select Run PEX
The PEX Netlist file windows will be invoked as shown.

Save the PEX netlist file as inv.pex.dspf in the path as shown in the figure or any location of
your computer.

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The File is successfully written and click on OK.

Select Start RVE from Calibre Interactive - PEX.

Calibre RVE window will pop up select parasitics in the navigator then extraction results will
be shown as shown below

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Double click on the port name then the parasitic values will be shown

Double click on the value, then corresponding value will be highlighted in the layout as Shown.

POST LAYOUT SIMULATION:

Open the test bench schematic and enter the simulation mode, then select the inverter block

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Select Tools ParasiticsAdd DSPF
A window named Add DSPF will pop up where browse on the folder to the saved Netlist
inv.pex.dspf and click OK as shown.

Run the simulation by selecting run simulation icon on left icon panel.

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You can Add & Remove DSPF in Parasitic which show results with & without

Parasitic. View the wave‟s output signal.

There is a noticable increase in the delay due to the

parasitics. Save the waveforms as practical.

WAVEFORM COMPARISION:

To compare the waveforms we must save both ideal and practical waveforms i.e, test
bench waveform and layout waveform.

Open both ideal and practical waveforms on the database which we have saved earlier.

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In EZ wave 12.1 production window select the Tools menu and click on the waveform
compare wizard as shown in the figure below.

Browse the path for Choose Reference Dataset from List or Disk as shown below.

Select Compare All Waveforms and click on Next.

Click on Finish.

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The comparision results of both ideal and practical waveforms are shown below.

This ends the full custom IC design flow for an inverter using HEP 1 Design tools from
Mentor Graphics.

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