module test;

reg [3:0] var1,var2,var3;

initial var1=10;
initial var2=var3;// var2=x
initial var3=var1;//10
$monitor (var1, var2, var3);
end
endmodule

var1=10;
var2=var3;// var2=x
var3=var1;//10
all these 3 statements are scheduled in active region , order of execution can be anything, it depends
on tool.

Var2=var3 , should be excute after execution of all blocking stamenets.

I can achive it using #0 delay.
Initial #0 var2=var3, instead of executing in active region it will be excuted in inactive region.
We don’t use #0 delay. Bacause if there is some race condition , you are using #0 delay, then you
wont be able to detect race around condition.

Var1=10; var2=20
Always @ (clk) var1=var2;
Always @ (clk) var2=var1;
Above is a case of race condiiton

Ff_op is coonected to mux ( designed using casex ),mux op is final op.

You have not reset your ff, ff op=x , mux op will have some value (0 or 1) // x propagation , gate
level simulation . will be unable to check case x propagation, if you are using casex. (it will interpret
x as 0 or 1)
To avoid it we use case z.

For encoder ref logic or decoder reference logic

Inp=(1<<op)
Op=00, inp=1<<00=1
Op=01, inp=1<<01=10;
Op=10. Inp=1<<10, 100;
Op=11, inp=1<<11, 100

Full case: all combination of case expression, no latch inferred

Non full acse : not all combination of case expression, latch inferred
Synthesis full case:synthesis directive, even if its not a full case synthesis tool will not inferred
latch.but simulation synthesis result mismatch, should be avoied.
3’b1?? // 100,101,110,111
3’b1?1// 101,111
3’b?11 // 011, 111 here case item are overlapping. Not a parallel. proryity logic will be
syntheiszed.

3’b1?? // 110, 100

3’b1?1// 101,111
3’b?11 // 011 if your case expression are like this, then you have to pass synthesis directive parralle
case, so that tool will synthesize it in to decoder logic like a parallel case.

Encoder: data flow, case , today_logic