UNIT-IV NMOS PLAs

The basic PLA structure consists of an AND plane driving an OR plane as shown in Figure .
The terminology corresponds to a sum of products (SOP) realization of the desired function.
The SOP realization converts directly into a NAND–NAND implementation. When a product of
sums (POS) realization is desired, it can be implemented in OR–AND or NOR–NOR logic.
In either case, the first array is referred to as the AND plane, and the second array as the OR
plane. The lines connecting the AND plane to the OR plane are called the product lines.

The OR plane matrix is identical in form to the AND plane matrix, but its layout is rotated 90
degrees with respect to the AND plane. The input and output registers need not be identical, but
they are also repetitive structures. The overall size of a PLA is a function of the number of
inputs, the number of product terms, the number of outputs, and the value of the parameter
lambda. The PLA must be programmed by appropriately locating transistors on the array.

NAND–NAND realization of NMOS PLA

The procedure for laying out a NAND–NAND PLA is described below: AND plane. For each
logic 1 in the input columns of the personality matrix, place an ion implant under the appropriate
product line where it intersects the noninverted input line in the PLA AND plane. The transistor
thus created is always ON and the non-inverted input line has no control over that product line.
Whenever all the controlling input lines in the AND plane are high, the product line will be low.
For each logic 0 in the input columns of the personality matrix, place an ion implant under the
appropriate product line where it intersects the inverted-input line in the PLA AND plane. The
transistor thus created is always ON and the inverted input line has no control over that product
line. Whenever all the controlling input lines are high, the product line will be low. A don’t care
requires ion implants for both the true and complemented input signals. OR plane. For each
logic 0 in the output columns of the personality matrix, place an ion implant under the product
line where it intersects the output line in the PLA OR plane. The transistor thus created is always
ON and that product line has no control over the output line. Whenever the controlling product
lines are high, the non-inverted output will be low. A NAND–NAND realization of NMOS PLA
for the above example in Eqns. is shown in Figure . The pull-up device is a depletion-mode
NMOS device.