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Register Transfer and Microoperations
Register Transfer and Microoperations
O
REGISTER
r TRANSFER AND MICROOPERATIONS
• Register Transfer
• Arithmetic Microoperations
• Shift Microoperations
R ← f(R, R)
15 0 15 8 7 0
R2 PC(H) PC(L)
Numbering of bits Subfields
Representation of a transfer(parallel)
R2 ← R1
Compute
A simultaneous transfer of all bits from the
source to the destination register, during one clock pulse
Representation of a controlled(conditional) transfer
P: R2 ← R1
A binary condition(p=1) which determines when the transfer
is to occur
If (p=1) then (R2 ← R1)
Register µ-op 5 Register
O
HARDWARE
r
IMPLEMENTATION OF CONTROLLED TRANSFERS
Load
Transfer occurs here
Compute
Bus lines
0 0 0 0
4 x1 4 x1 4 x1 4 x1
MUX MUX MUX MUX
x
select
y
4-line bus
Register µ-op 7 Bus and
O
TRANSFER
r FROM BUS TO A DESTINATION REGISTER
Bus lines
Load
Reg. R0 Reg. R1 Reg. R2 Reg. R3
D 0 D1 D2 D 3
z E (enable)
Select 2x4
w
Decoder
S0 0
Select 1
S1 2
Enable 3
Register µ-op 8 Bus and
O
r MEMORY TRANSFERS
Memory Read
AR
unit Write
ead DR
Binary Adder
B3 A3 B2 A2 B1 A1 B0 A0
FA C3 FA C2 FA C1 FA C0
C4 S3 S2 S1 S0
Binary Adder-Subtractor
B3 A3 B2 A2 B1 A1 B0 A0
C3 C2 C1 C0
FA FA FA FA
Compute
C4 S3 S2 S1 S0
Binary Incrementer
A3 A2 A1 A0 1
x y x y x y x y
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
Register µ-op 11 Ar
O
r ARITHMETIC CIRCUIT
Cin
S1
S0
A0 X0 C0
S1 D0
S0 FA
B0 0 4x1 Y0 C1
1 MUX
2
3
A1 X1 C1
S1 FA D1
S0
B1 0 4x1 Y1 C2
1 MUX
2
3
A2 X2 C2
S1 FA D2
S0
B2 0 4x1 Y2 C3
1 MUX
2
3
A3 X3 C3
S1 FA D3
S0
B3 0 4x1 Y3 C4
1 MUX
2
3 Cout
Compute 0 1
Applications
Manipulating individual bits or a field(portion) of
a word in a register
Compute
- Selective-set A+B
- Selective-complement A⊕B
- Selective-clear A•B
- Mask (Delete) A•B
- Insert (A • B) + C
- Compare A⊕B
- Packing (A • B) + C
- Unpacking A•B
er
Ai
0
Bi
1
4X1 Fi
MUX
2
3 Select
S1
S0
S
MUX H0
0
1
A0
A1 S
MUX H1
0
A2 1
A3
S
Compute H2
0 MUX
1
S
MUX H3
0
1
Serial
input (IL)
Register µ-op 17 Shift Micr
O
r ARITHMETIC LOGIC SHIFT UNIT
S3
S2 Ci
S1
S0
Arithmetic D i
Circuit
Select
Ci+1
0 4x1 Fi
1 MUX
2
3
Ei
Logic
Bi Circuit
Ai
Ai-1 shr
Ai+1 shl