IET Power Electronics

Research Article

ISSN 1755-4535
Improved three-phase, five-level pulse-width Received on 6th December 2013
Accepted on 5th October 2014
modulation switched voltage source inverter doi: 10.1049/iet-pel.2014.0133
www.ietdl.org

Charles I. Odeh ✉
Department of Electrical Engineering, University of Nigeria, Nsukka, Nigeria
✉ E-mail: charles.odeh@unn.edu.ng

Abstract: This study presents an improved three-phase, five-level pulse-width modulation (PWM) switched voltage source
inverter. The single-carrier, multilevel PWM scheme is employed to generate the gating signals for the power switches.
Operational principles with switching functions are given. By controlling the amplitude modulation index, three- and
five-level output phase voltage waveforms can be achieved. For modulation indices of 0.45, and 0.9, the proposed
inverter topology was subjected to an R–L load and the respective number of output voltage level were synthesised.
For a step change in the modulation index, the response of the proposed multilevel inverter circuit topology is
demonstrated. Fast Fourier transform analyses of the output line voltage waveforms, at the indicated depth of
modulation, were carried out and the corresponding total harmonic distortion values were obtained. Comparison of the
proposed inverter configuration and the classical 3-f topologies is given based on the power circuit component count.
Moreover, analysis of the conduction power losses in the power semiconductor switches of the proposed inverter
topology is given. To verify the performance of the proposed inverter architecture, simulations and experiments are
carried out on a 3.46 kW rated prototype of the proposed inverter for an R–L load; and adequate results are presented.

1 Introduction
High power demanding industries are usually connected to medium
voltage grids. For connecting power electronic converters to medium
voltage grids two trends are observed, one using classic power
converter topologies with high-voltage power semiconductor
switches and other using new multilevel converter (MLC)
topologies with medium voltage semiconductor switches. Out of
these two trends, MLCs have become popular for medium voltage
high power applications because of reduced rating of power
semiconductor devices, improved quality of output voltage, near
sinusoidal input currents, lower common-mode voltages, less dv/dt
stress, smaller input and output filters, increased efficiency because
of possibility of low switching operation, reduced output torque
ripple, reduced electromagnetic interference problems and possible
fault-tolerant operation [1–6].
The popular multilevel topologies are neutral-point converter
(NPC) or diode-clamped converter [7], flying-capacitor (FC)
converters [8] and cascaded H-bridge (CHB) converter [9]. In
addition, generalised multilevel inverter topology with self-voltage
balancing [10], mixed-level hybrid multilevel cells [11],
asymmetric hybrid multilevel cells [12] and soft switched
multilevel inverters [13–15] have been proposed. The topology of
NPC inverter is limited to three-level operation because of
capacitor voltage balancing issues as well as excessive clamping
diodes required for high level inverters [4]. The topology of
capacitor-clamped inverters is limited to three-level or four-level
because of several limitations like a capacitor voltage balance
requirement, pre-charge of the capacitors at the start and need of
larger number of capacitors. In addition, this topology is not
suitable for low and medium switching frequencies because of the
high cost of FCs [16]. For higher-level operation, cascaded
inverters are preferred as they require the least number of
components compared to other topologies as well as modularised
circuit layout; and packaging is possible, because each level has
the similar structure [16]. Although the modular structure solves
the voltage imbalance problem, this approach requires many
isolated DC sources and link voltage controllers.
In recent years, several topologies with various control techniques
have been presented for single- and three-phase cascaded multilevel
inverters [17–30]. In all, the driving objective is to obtain a high level
of stepped output voltage waveforms, which result in low total
harmonic distortion (THD), with fewer power circuit components
and/or minimum number of input DC sources, for medium and
high power applications.
With this pivot objective, works done in [31, 32] achieved the
enhancement of the basic H-bridge inverter configuration for
single- and three-phase applications. In [31], an auxiliary steering
circuit is inserted between the midpoint of two DC sources and the
H-bridge configuration. This 1-ɸ power circuit arrangement is
capable of synthesising five-level output voltage. Also, proposed
in [32] is a 3-ɸ, three-level pulse-width modulation (PWM)
switched voltage source (SVS) inverter, which has the inherent
capability of employing one common DC-supply to synthesise
five-level output line voltages.
In furtherance of the aforementioned concept of fewer power
circuit components and/or minimum number of input DC sources
for an appreciable output voltage levels, this paper presents an
improved 3-ɸ, five-level, PWM SVS inverter; wherein two equal
DC sources and auxiliary steering circuits are introduced in the
SVS inverter configuration in [32]. With appropriate single-carrier
PWM switching scheme, the proposed inverter topology is capable
of generating nine-level output line voltages. The increased output
voltage level leads to a considerable reduction in the output
voltage THD.
The aforementioned effect is of prime importance in
transformerless power conditioning systems and makes the
proposed inverter configuration well suited for these systems.
Moreover, in drive systems conventional multilevel PWM inverters
generate common-mode voltage or a ‘neutral shift effect’ within
the motor windings. This common mode voltage may build up the
motor shaft voltage through electrostatic couplings between the
rotor and the stator windings and between the rotor and the frame
[33]. Moreover, since the conventional inverters have a DC offset
voltage between the ground and the motor neutral point, the
common mode voltage becomes higher and the motor
line-to-ground voltage may be much higher than its rated
line-to-neutral (phase) voltage. Therefore the transformerless
design of the drive with the conventional PWM inverters may
cause a much larger common-mode leakage current to flow into

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Fig. 1 Power circuit configuration and operational modes of the improved three-phase multilevel SVS inverter
a Power circuit
b Vag = 0
c Vag = VS
d Vag = 2VS
e Vag = 0
f Vag = −VS
g Vag = −2VS

the ground [33] and cause a high-voltage stress on motor insulation have the same ground with the input DC source, and the motor
life. However, in the case of the proposed multilevel inverter line-to-ground voltage is identical to its phase voltage. Therefore,
configuration, the neutral point of the motor stator windings can the ‘neutral shift effect’ disappears, and as long as the motor phase

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Table 1 Definition of switching states per phase for the SVS inverter Table 2 Comparison of the proposed five-level inverter with the
well-known five-level inverter topologies on the basis of power circuit
Phase voltage, Vag State of the switching signals component requirements

g1a g2a g3a g4a g5a Inverter type Proposed Diode-clamped FCs CHB
inverter
0 on on off off off
VS off off on off on main 15 24 24 24
2VS on off on off off switching
0 off off on on off device
−VS off on off off on main diodes 15 18 0 0
−2VS off on off on off DC bus 2 1 (split into four by 1 6
(non-isolated) DC-link capacitors) (isolated)
clamping 3 0 18 0
capacitor

Fig. 2 Operation of the SVS inverter module depicting buck converter

a Powering mode
b Free-wheeling mode
c Possible cascade structure with the proposed inverter as the building block

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voltage is kept within its rated value during operation, the motor
insulation will not be deteriorated. Operational principles and
switching functions are analysed. Simulation and experimental
results are presented to verify the validity of the proposed 3-ɸ
inverter configuration.
2 Circuit configuration and operational principle
of the proposed 3-ɸ, five-level PWM SVS inverter
The power circuit of the 3-f, five-level PWM SVS inverter consists
of three H-bridge modules, three auxiliary steering circuits with
common two input DC sources as shown in Fig. 1a.
With this circuit components arrangement, proper switching of
any of the H-bridge inverter module with the corresponding
auxiliary circuit in a phase-leg can produce five output phase
voltage levels: 0, Vs, 2Vs, −Vs and −2Vs. In effect, line-to-line
output voltage waveforms of nine-levels are generated at the
star-connected load terminals. Each phase can be independently
operated with the common two equal DC input sources. However,
just like the traditional neutral-point-converter (NPC) three-level
inverter topology and other inverter configurations that utilises two
equal split DC sources for their power conversion processes, the
proposed SVS inverter configuration can function properly with
two DC-link capacitors fed from a single DC source; probably
from a rectifier, battery bank or even from renewable energy
sources. The common demand in these inverter configurations is
Fig. 3 Switching pattern, for phase ‘a’, of the 3-ɸ, five-level pulse-width modulated SVS inverter and switching angles
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that two equal stiff voltage sources should be provided at the input
terminals. Considering phase ‘a’ leg, the basic operational modes,
occurring simultaneously in each of the phases of the SVS
inverter, are shown in Fig. 1b. For phase ‘a’ leg in Fig. 1a, the
synthesised output voltages and the corresponding state of the
switching signals are summarised in Table 1.
Table 2 gives a comparison between the proposed inverter and the
well-known five-level conventional inverter topologies.
For higher level/power inverter application, the proposed inverter
topology can be a basic building cell for a cascaded structure. Such
possible configuration can be seen in Fig. 2b, wherein the maximum
voltage stress on any of the switches is 2Vs. Any of the MLC
modulation schemes [34–36], can be extended to this cascaded
structure for its control.
3 PWM scheme
Single-carrier sinusoidal PWM (SCSPWM) scheme is employed in
the generation of the gating signals. Basic principle of the
proposed switching strategy is to generate gating signals by
comparing rectified sinusoidal modulating/reference signals, at the
fundamental frequency, with only one triangular carrier at the
desired switching frequency and whose peak-to-peak amplitude is
Ac. For n-level SCSPWM, k number of rectified sinusoidal
modulating signals have the same fundamental frequency, fm and
amplitude, Am, with DC bias of Ac as a difference between these
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Table 3 Range of modulation index and the corresponding values of For one cycle of the fundamental frequency, the proposed
the phase angle displacement multilevel inverter operates through four modes in each phase.
Range of Ma θ1 θ2 θ3 θ4 Fig. 3 also illustrates the per unit output voltage waveform for one
cycle in a phase leg.
Ma ≤ 0.5 π/2 π/2 3π/2 3π/2 The four modes are described as follows:
Ma > 0.5 sin−1(Ac/Am) π − θ1 π − θ1 2π − θ1
Mode 1: = 0 < ωt ≤ θ1 and θ2 ≤ ωt ≤ π
Mode 2: = θ1 ≤ ωt ≤ θ2
Mode 3: = π < ωt ≤ θ3 and θ4 ≤ ωt ≤ 2π
signals [34, 35]. The switching/modulation scheme adopted in the Mode 4: = θ3 ≤ ωt ≤ θ4
proposed cascaded multilevel inverter is illustrated in Fig. 3, for
phase ‘a’. The basic principle in generating the gate signals begins The angle, θ, depends on the modulation index, Ma, which is
from the comparison of the modulating signals with the carrier given as [27, 28]
wave. The actual gate signals are produced by the logical
combinations of the results of such comparisons and the
Am
synchronised base square waveforms, having the fundamental Ma = (1)
frequency, fm. Ac (k − 1)

Fig. 4 Power losses plots

a Normalised plots of PTC, PDC, PTV and PDV and their variation with power factor and depth of modulation
b Normalised contour plots of PSW and its variation with phase angle and depth of modulation

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Fig. 5 Simulated inverter output voltages and currents
a Ma = 0.45
b Ma = 0.9

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Fig. 6 Inverter output voltage and current waveforms for a step change in modulation index
where Ac is the peak-to-peak value of the triangular carrier signal, Am
is the peak value of the rectified sinusoidal reference signals and k is
the number of voltage levels synthesised, per half-cycle; in this case,
k = 3. Table 3 shows the ranges of modulation index and the
corresponding values of the phase angle displacement. Also, the
frequency modulation index expression is
fc
Mf = (2)
fm
where fc and fm are the frequencies corresponding to the carrier and
modulating signals, respectively.
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For Ma equal to or less than 0.5, only the upper reference wave, R1
is compared with the triangular carrier signal, T. The inverter’s
behaviour matches exactly to that of the SVS inverter proposed in
[32], synthesising three-level output voltage waveform per phase
for a period. On the other hand, Ma is set to be greater than 0.5
for five-level output phase voltage to be produced in this work. In
this case, the two reference signals, R1 and R2 have to be
compared with the triangular carrier signal to produce switching
signals for the power switches.
Considering phase ‘a’, and referring to Fig. 2, the gating signals
are then given by the use of basic logical AND, OR and NOT gates

 
g1a = (T . R1 ) + (R2 . T ) · A (3)
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g2a = (T . R1 ) · A + (R1 . T) · B (4) The first term in (8) is the loss because of the constant
components of on-state voltage VTO, whereas the second term is
g3a = g2a (5) the loss because of the linear dependence on current of the

  on-state voltage as expressed in terms of KT. Hence, (8) can be
g4a = (T . R1 ) + (R2 . T ) · B (6) rewritten in terms of these two components as
g5a = (g1a + g4a ) (7)
PT = PTC + PTV (9)

4 Analysis of the SVS inverter module Also, the conduction loss expression, PD, for the diodes in the power
circuit can be written as
Analytical expressions for the average conduction power losses in
the main power semiconductor switches can be obtained in terms
of the voltage and current amplitudes, depth of modulation and VDO Im  p  K I 2 p 2
PD = 1 − Ma cos f + D m − Ma cos f (10)
power factor for typical conditions prevailing in pulse-width 2p 4 2p 4 3
modulated inverters, [37]. For each of the active switches
(insulated gate bipolar transistors – IGBT) used herein, a good
approximation for the average on-state loss, PT, is where VDO and KD are the constant on-state voltage across a diode
and on-state resistance, respectively. Similarly, (10) can be
VTO Im  p  K I 2 p 2 rewritten as
PT = 1 + Ma cos f + T m + Ma cos f (8)
2p 4 2p 4 3
PD = PDC + PDV (11)
where VTO, KT, Im, Ma and f are the constant on-state voltage across
a switch, on-state resistance, peak load current through a device, Equations (8) and (10) can be normalised to have the
applied modulation index and power factor angle, respectively. three-dimensional plots of

Fig. 7 Phase ‘a’ capacitor and switches’ voltages and currents waveforms for Ma = 0.9

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Fig. 8 FFT analyses of the synthesised output line voltages
a Ma = 0.45
b Ma = 0.9

2p 2p 2p 2p EOFF = 0.00443e0.0021 Ma Im sin (u−f) − 0.0547e−0.00107 Ma Im sin (u−f)

P , P , P , P
VTO Im T KT Im2 T VTO Im D KT Im2 D (13)
against the modulation index and the load power factor as depicted in
Erec = 0.00806e−0.000322 Ma Im sin (u−f) − 0.0077e−0.00446 Ma Im sin (u−f)
Fig. 4.
The two components of the switch’s losses can be seen increasing (14)
while the corresponding diode losses decrease complimentarily as
the load power factor improves. Similar trends are apparent as Therefore the average switching loss is expressed as
depth of modulation increases.


Switching losses (PSW) are generated during the turn-ON and fc 
turn-OFF switching processes; and are directly related to the PSW = EON + EOFF + Erec (15)
2p
switching frequency. Hence, these losses are usually greatest in
PWM power converters. The switching loss for every power
Equation (15) can be normalised to have the contour plots of PSW
device is obtained by identifying every turn-ON and turn-OFF
against the modulation index, Ma and the load angle, j, as shown
instants, θ, during one reference period. The semiconductor
in Fig. 4b.
average switching losses can be estimated from the characteristic
In Section 2, it was assumed that the capacitor C is charged to a
curves, which are presented in the datasheets of each power device
constant overall input voltage value, 2VS; and hence regarded as a
[38]. The IGBTs used to implement the proposed inverter
constant voltage source. However, in real time operation, there is
configuration are IXYS FII40-06D. Considering this
a slight difference between the actual capacitor voltage, VC and
semiconductor loss, the characteristics curves, which represent the
the input voltage, 2VS. This slight difference may cause an inrush
energy losses during commutation are EON(θ)(turn-on commutation
current on the switch S1a, for phase ‘a’, and the diode when they
loss), EOFF(θ)(turn-off commutation loss) and Erec(θ) (for diode
turn on. This possible occurrence is avoided by placing a very
reverse recovery process). These curves are approximated by
small snubber inductor L is between the diode and the capacitor C.
exponential equations, using curve-fitting tool of MATLAB
However, this small snubber inductor does not affect the operation
mathematical models obtained for the IGBTs, and are given as
of the proposed SVS inverter.
EON = 0.0041e0.0044 Ma Im sin (u−f) − 0.0037e−0.0088 Ma Im sin (u−f) Fig. 2 shows one of the switching circuits of the SVS (given in
Fig. 1) of the SVS inverter module depicting buck converter
(12) operation. The snubber inductor L is quite small and the buck

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Table 4 Prototype specification From (16), the design equation of L can be expressed as
Power switches: IXYS FII40-06D 
2 
Power diodes: STTH12012TVL
R = 60 Ω, L = 40 mH
D2 2
L = RTs − 1 −1
8 M

2 
Vs (1 − Ma )2 2
= Ts − 1 −1 (17)
IL 8 M
converter circuits in Figs. 2a and b operate in discontinuous
conduction mode. In this mode of operation, its voltage conversion
ratio, M, is expressed as

 5 Simulation and experimental results
vo 2
=M = 


 (16)
2Vs 5.1 Simulation results
8t
1+ 1 + 2L
D The operational principles and the switching scheme of the improved
SVS inverter shown in Fig. 3 and Table 1 have been investigated by
MATLAB SIMULINK simulation. A balanced three-phase star
where tL = L/RTs ; Ts is the switching period; and R is the load connected R–L load with 40 Ω resistance and 60 mH inductance
resistance. per phase were used for input voltages of 100 V each.

Fig. 9 Inverter prototype and experimentally obtained gating signals

a Laboratory prototype setup for the proposed SVS inverter
b Experimental gating signals for phase ‘a’
CH1: g1a, CH2: g2a, CH3: g3a and CH4: g4a

Fig. 10 Experimental output voltages for Ma = 0.45

a Phase voltages
b Line voltages

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Fig. 11 Experimental output voltages for Ma = 0.9
a Phase voltages
b Line voltages
Fig. 5 shows the simulated waveforms of the output voltages and
load current at switching frequency of 3 kHz for the indicated
loading condition, when modulation indices are 0.45 and 0.9. The
phase voltage waveforms in Fig. 5 exhibit three-levels: VS, 0 and
−VS; while the corresponding line-to-line voltage waveforms show
five-levels: 2VS, VS, 0, −VS and −2VS. Furthermore, increasing Ma
to 0.9 results in the synthesised phase voltage waveforms to have
a five-levels: 2VS, VS, 0, −VS and −2VS, whereas the
corresponding line voltages have a nine-levels: 4VS, 3VS, 2VS, VS,
0, −VS, −2VS, −3VS and −4VS as earlier predicted. For a step
change in the modulation index, the response of the proposed
multilevel inverter circuit topology is demonstrated in Fig. 7.
Considering phase ‘a’ module of the SVS inverter, the switches’
and capacitor voltages and current waveforms are shown in Fig. 6.
This figure shows that the output phase voltage levels of the SVS
inverter are principally determined by the blocking voltages of the
power switches and the capacitor voltage as demonstrated in
Figs. 7 and 11b.
Spectral analysis of the inverter line voltage waveforms in Fig. 5 is
carried out for the varied amplitude modulation index values. The
spectral results are displayed in Fig. 8; wherein THD values of
Fig. 12 Experimental output line currents and capacitor voltage for Ma = 0.9
a Line currents
b Capacitor voltage
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26.20 and 12.28% for Ma = 0.45 and 0.9, respectively, are
obtained in the line voltage waveforms.
5.2 Experimental results
Based on the simulation results, a laboratory prototype of the
improved 3-f, five-level PWM SVS inverter was set up and tested
to verify its validity. Table 4 gives the prototype specifications and
parameters. The aforementioned modulation scheme is
implemented by using basic CMOS logic gates and TL 084 IC
and hence, the 15 gating pulses were generated.
Fig. 9 shows the inverter prototype and experimentally obtained
gating signals of phase ‘a’ leg. Fig. 10 shows the experimental
waveforms of the inverter output voltages for the specified loading
condition in Table 4, where the depth of modulation is 0.45.
Furthermore, increasing the amplitude modulation index to 0.9
results in the synthesis of higher level of inverter output voltages,
as experimentally depicted in Fig. 11. In Fig. 12, the
corresponding line currents and one of the capacitor voltage were
shown.
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6 Conclusions
Presented in this paper is a new configuration for 3-f SVS multilevel
inverter. The operational principles, modulation scheme and
switching functions have been analysed in detail. The proposed
multilevel inverter exhibited the behaviours of three-level inverters
earlier reported; in addition to the five-level characteristics herein.
By controlling the modulation index, the desired number of levels
of the inverter’s output voltage has been achieved. Also, it has
been shown from the FFT analysis of the experimental output
voltage waveforms that the proposed improved 3-f, five-level
PWM SVS inverter topology possesses a better harmonic profile
than the lower level voltage source inverters. For typical
modulation indices of 0.45 and 0.9, THD values of 26.20 and
12.28% have been achieved in the synthesised output line voltage
waveforms of the proposed inverter configuration. Also, a good
approximation for the average power loss in the active and passive
power switches is given in simple expressions in terms of current
amplitude, depth of modulation and power factor for typical
conditions prevailing in PWM inverters. The performance of the
proposed inverter topology has been presented through simulations
and experiments on a 3.46 kW rated prototype of the proposed
inverter for an R–L load; results have been adequately presented.
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