1.1 Define Boolean algebra?

State and explain De-Morgan’s laws and draw the equivalent circuits representing
them.
1.2 Minimize the following function using K-map and realize using NOR and NAND gates.
F=∑m[0,2,4,5,6,7,8,10,14,17,18,21,29,31] +∑d[11,20,22].
1.3 Reduce the following function using K-map and realize it using basic gates.
F[A,B,C,D]=ABC’D’+ABCD+A’B’C’D’+A’BC’D’+A’BCD+ A’B’CD+ ABCD’ .
1.4 Solve the following conversions. (a) [1010110101]2 to [ ]8 (b) [257]8 to [ ]16
1.5 Solve the following arithmetic operations.
a. 1100111-1010101 using 1’s complement method and 2’s complement method
b. 691B – CA14 using 15’s complement method and 16’s complement method
c. Solve BCD addition between 3729 and 2903.
1.6 Using suitable examples explain in detail about representation of signed binary numbers also give its
advantages and disadvantages.
1.7 Realize 2 input Ex-OR and Ex-NOR gates using NAND and NOR gates.
1.8 Solve the following conversions [binary to Gray]. (a) 1010111011 (b) 01001010101110
1.9 Draw and explain basic gates and universal gates using truth tables.
1.10 Solve r’s & r-1’s complement of the following. (a) [256]8 (b) [A6D]16
1.11 Implement the function F[A,B,C,D]=AB’C+ ACD’+BCD using logic gates realization.
1.12 Explain in detail about weighted and Non-weighted codes.
2.1 What is an Encoder? Explain about Priority Encoder in detail.
2.2 What is meant by decoder? And design full adder using suitable decoder.
2.3 Write short notes on multiplexer & Demultiplexer and Implement 2x1 MUX using logic gates.
2.4 Explain in detail about adder/subtractor.
2.5 Implement 32x1 multiplexer with 8x1 multiplexer and 2 to 4 decoder.
2.6 Explain in detail about BCD adder.
2.7 Implement the following combinational logic circuit using a 4 to 16 line decoder.
F=∑m [0,2,4,5,6,7,8,10,14,17,18,21,29,31]
2.8 Write Short notes on Combinational logic Circuit & realize a 4-Bit Comparator.
2.9 Explain full adder and full subtractor using relevant diagrams.
2.10 Draw and explain 3*8 Decoder with the help of Truth Table.
2.11 Solve the following conversion. (a) T-flip flop to S-R flip-flop (b) S-R flip flop to J-K flip flop
3.1 Write short notes on Sequential logic circuits and Explain the operation of NAND and NOR latches.
3.2 What is meant race around condition and how it is eliminated using JK flip flop.
3.3 Explain the operation of SR flip-flop & T flip-flop using timing diagram.
3.4 Explain about the realization of JK flip-flop & D flip-flop?
3.5 Compare Latch and Flip-Flop and Explain Different triggering methods used in Flip-Flops.