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    FPGA ML Skills

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    jayesh_1686
    The document discusses the author's experience developing FPGA-based acceleration platforms for machine learning and deep learning workloads using FPGAs from Intel and Xilinx. Specifically, it mentions experience with: - Developing a platform called SIRA that uses DMA to offload workloads from Intel Xeon CPUs to FPGAs over PCIe and integrate with Spark Streaming. - Designing multi-channel DMA cores, memory controllers, and clock crossing domains for high-speed data transfer and low latency memory access. - Porting solutions to run on Intel PAC, Xilinx Alveo, AWS F1, Microsoft Azure, and optimizing memory access for machine learning algorithms.

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    FPGA ML Skills

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    jayesh_1686
    27 views1 page
    The document discusses the author's experience developing FPGA-based acceleration platforms for machine learning and deep learning workloads using FPGAs from Intel and Xilinx. Specifically, it mentions experience with: - Developing a platform called SIRA that uses DMA to offload workloads from Intel Xeon CPUs to FPGAs over PCIe and integrate with Spark Streaming. - Designing multi-channel DMA cores, memory controllers, and clock crossing domains for high-speed data transfer and low latency memory access. - Porting solutions to run on Intel PAC, Xilinx Alveo, AWS F1, Microsoft Azure, and optimizing memory access for machine learning algorithms.

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    The document discusses the author's experience developing FPGA-based acceleration platforms for machine learning and deep learning workloads using FPGAs from Intel and Xilinx. Specifically, it mentions experience with: - Developing a platform called SIRA that uses DMA to offload workloads from Intel Xeon CPUs to FPGAs over PCIe and integrate with Spark Streaming. - Designing multi-channel DMA cores, memory controllers, and clock crossing domains for high-speed data transfer and low latency memory access. - Porting solutions to run on Intel PAC, Xilinx Alveo, AWS F1, Microsoft Azure, and optimizing memory access for machine learning algorithms.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    27 views1 page

    FPGA ML Skills

    Uploaded by

    jayesh_1686
    The document discusses the author's experience developing FPGA-based acceleration platforms for machine learning and deep learning workloads using FPGAs from Intel and Xilinx. Specifically, it mentions experience with: - Developing a platform called SIRA that uses DMA to offload workloads from Intel Xeon CPUs to FPGAs over PCIe and integrate with Spark Streaming. - Designing multi-channel DMA cores, memory controllers, and clock crossing domains for high-speed data transfer and low latency memory access. - Porting solutions to run on Intel PAC, Xilinx Alveo, AWS F1, Microsoft Azure, and optimizing memory access for machine learning algorithms.

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    © All Rights Reserved
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    of 1

    About 5 years of experience as Architect/Designer for FPGA based Heterogeneous Computing

    (Video Analytics with Machine Learning and Deep Learning libraries, Financial trading, Embedded
    Sytems) with Intel and Xilinx FPGAs. Worked on Intel Xeon CPU-FPGA Acceleration Platforms,
    Xilinx SDAccel with U200, AWS EC2 F1. Expertise in Architecture, Modelling, Design, Verification in
    System Verilog, VHDL, On-Board Debugging, Validation. Working knowledge of various standard
    protocols like 40G/10G Ethernet MAC, UDP, DDR4/3, PCIe, DMA, Cache Controller, DSP
    Algorithms, Multi-Clock Designs. 

    Architecture, Development of Acceleration platform for Real-Time Analytics on Spark Streaming


    with Machine Learning and Deep Learning libraries on Intel Xeon+FPGA 

    -> Development of SIRA (Infrastructure for running ML/DL algorithms, UDP Offload) 
    -> Involved in the Architecture of SIRA, Memory Map description, Test Plans
    -> Design, Verification and Validation of Multi-Channel DMA (Integrated Intel Scatter-Gather
    DMA IP) with CCIP interface, using the full PCIe 8x Bandwidth (~6 GB/Sec) 
    -> Created Unit tests using SV Unit.
    -> Integrating the full stack with DMA, DDR4, 10G/40G Ethernet and Profiling
    -> Clock Crossing domains designs, Configurable Pipeline with FIFO's, Timing Closure
    -> Google-test suit for on-board validation on Intel Arria 10 PAC
    -> Created OPAE test applications for DMA, Memory Map Snooping.
    -> Worked closely with Software team to integrate the solution with Host Application.
    -> Generic Arbiter to allow multiple modules to access DDR4 on-board memory
    -> Porting the solution to Xilinx Alveo, Amazon AWS.
    -> Creating Specs and Execution plan based on requirements from SIRA SDK team
    -> Agile Workflow

    Leading SIRA Shell Development for AWS EC2, Xilinx Vitis, Intel PAC
    -> Architecture, Development of FPGA based Acceleration platform for Real-Time Video, Text
    Analytics with Machine Learning and Deep Learning hardware libraries.
    -> Port the solution on Intel PAC, Xilinx Alveo, AWS F1, Microsoft Azure
    -> Development for an optimized memory access (VRAM - Cache Controller) for Machine
    Learning and Deep Learning algorithms.
    -> Design of Virtual FIFO, RAM, Pre-fetcher for low latency memory access
    -> Muti-Channel Memory controller for SIRA
    -> Work with Software team for System Integration
    -> Agile Workflow, CI, git.

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