Experimental Study on the Influence of Dead-time

on IGBT Turn-off Characteristics in an Inverter Leg

at High and Low Currents
Kapil Upamanyu, D. Venkatramanan, Anil Adapa, G. Narayanan
Department of Electrical Engineering, Indian Institute of Science, Bangalore, India
Email: kapil.upamanyu@gmail.com, venkat86ram@ee.iisc.ernet.in, aniladapa@ee.iisc.ernet.in, gnar@ee.iisc.ernet.in

Abstract—For safe operation of voltage source converters,
dead-time is provided to the IGBTs that belong to a single
leg. While a large value of dead-time prevents dc-bus shoot-
through, it also causes error in the output voltage of the power
converter, leading to distortion of line currents and increased
harmonic content in them. The problem is more severe in case
of high switching frequency operation of the power converter.
IGBT turn-off time is an important factor for the selection
of appropriate dead-time. In this paper, turn-off characteristics
of IGBT are studied for two different orders of magnitude of
switching current. IGBT voltage transition time is observed to
be significantly higher at low switching currents. The low rate
of rise of device voltage at low currents is shown to be due
to the parasitic capacitance of the IGBT. The influence of the
dead-time on the turn-off characteristics is also studied. For
switching transitions at high current, dead-time does not affect
the transition characteristics. But for low current switchings, the
device voltage rise time decreases with the decrease in dead-time.
The turning-on of the other IGBT of the same leg accelerates
the rate of voltage transition. If dead-time is reduced to such
an extent that the gate voltages of both the IGBTs are above
the respective thresholds, shoot-through is observed. The value
of dead-time for which the actual shoot-through is observed is
the same for high and low currents.
I. I NTRODUCTION
Voltage Source Converters (VSCs) have found wide spread
applications in the field of power electronics and power sys-
tems. Insulated-gate bipolar transistors, IGBTs are extensively
used in VSCs due to their superior switching characteristics
and ease of control. A phase leg of the VSC consists of two
series connected IGBTs with anti-parallel diodes. The two
IGBTs are switched in a complementary fashion. Due to finite
switching transition times present in practical power semicon-
ductor switches, a dead-time is given between switching-off of
one device and switching-on of the complementary device to
avoid shoot-through of the dc link [1]. Dead-time introduces
low-order harmonics at the converter pole voltages, and results
in distortion of the load currents which is more pronounced
at high switching frequencies [2], [3]. When operating an
electrical machine powered from a VSC, instability in the
operation can take place [3], [4]. To counter these problems,
This work was supported by CPRI, Ministry of Power, Government of India,
under the project Power conversion, control, and protection technologies for
microgrid.
978-1-5090-4530-3/16/$31.00 2016
c IEEE
various dead time compensation techniques are used [2],
[3]. Advent of the semiconductor technology enables fast
transition of the switching device. This helps in decreasing the
switching loss and size of the converter, resulting in overall
cost reduction. But higher dv/dt across the switching device
results in problems of insulation failure and deterioration of
machine life in converter-fed motor drives [5], [6]. Also higher
switching speeds increase the EMI problem in the converter
system [7]. In addition to these problems, high frequency
operation increases severity of the dead-time issues. The ratio
of dead-time to switching period increases at high frequencies
if dead-time is not changed accordingly.
Keeping the dead-time at minimum while ensuring safe
operation of VSC is essential to limit the adverse effects due to
dead-time [1]. Switching current strongly affects the turn-off
characteristics of the IGBT. Circuit parasitics plays a major
role in these characteristics, especially at low currents [1],
[8], [10]. Hence, turn-off characteristic are extensively studied
in this work. Turn-off characteristics are studied for various
reasons like calculations of switching losses and designing of
EMI filters in addition to selection of dead-time [1], [8], [9].
Double pulse test is a standard test procedure to obtain the
switching characteristics of the IGBT [8], [9].
An IGBT based three phase voltage source converter pre-
sented in [11] is assembled, and is used for studying the
turn-off characteristics of the state-of-the-art 1200 V, 40 A
rated IGBT, IKW40N120H3 [10] (Fig.1a). To measure the
(a) (b)
Fig. 1: Photograph of (a) the IGBT, IKW40N120H3, and (b)
the Rogowski coil current transducer.

Fig. 2: Circuit diagram for double pulse test set-up.
device current, a Rogowski coil current transducer is used
(Fig. 1b). Section II details the double pulse test conducted
for the characterization of the IGBT. Section III discusses the
experimental results. Section IV presents the conclusions.
II. D OUBLE P ULSE T EST
A schematic of the double-pulse test setup is shown in Fig.
2. In the test setup the IGBT, S1 , is the device under test
(DUT). An inductive load is connected across the IGBT, S2 .
The dc link voltage, Vdc and duration of pulses in the test can
be controlled to obtain the turn-on and turn-off characteristics
of the DUT at desired voltage and current levels. Anti-parallel
diodes and collector-emitter parasitic capacitances, Cp , of the
IGBTs are also indicated in the circuit schematic.
Input gate pulses to the IGBTs S1 and S2 are shown in
Fig. 3a for the suggesting test procedure. The switching signal
to the IGBT, S1 , consists of two pulses of duration T1 and T3 ,
separated by a time duration of T2 . In the traditional version
of double pulse test, no pulse is given to the second IGBT, S2 .
But in the present case, a single pulse to IGBT S2 is given.
This pulse is applied during the time duration, T2 . Hence,
when S1 is switched on, S2 is kept off and when S1 is turned
off, S2 is made to turn on. This condition is the same as that
during the operation of IGBTs on the same leg of a voltage
source converter. At the end of T1 and T2 , both the IGBTs are
gated low during the time durations, t12 and t23 , signifying
dead-time.
The expected current through the load (Il ), IGBT S1 (Is )
and the anti-parallel diode of IGBT S2 (Id ) are as shown
in Fig. 3b. At the rising edge of the first pulse to S1 , load
current starts rising linearly from zero at a rate determined by
the values of dc bus voltage Vdc and the load inductance. At
the end of time duration T1 , S1 is switched OFF. The load
current starts freewheeling through the anti-parallel diode of
S2 . This condition exists for time duration T2 . During this
time interval the current decays due to the voltage drop across
the diode. At the starting of second pulse to S1 freewheeling
of load current ends and S1 starts conducting again. Current
increases for the time duration T3 after which S1 turns OFF.
Load current freewheels through the anti-parallel diode of S2
until it becomes zero.
In this complete process, there are two turn-on transitions
and two turn-off transitions. The first turn-on is at zero current


 




 

 
(a)

 
 






(b)
Fig. 3: (a) Switching pulses for IGBT under test, S1 and
complementary IGBT, S2 and (b) the corresponding current
through load (Il ), IGBT under test (Is ) and anti-parallel diode
of complementary IGBT (Id ) for double pulse test
and the second one is at a current level dependent on the values
of T1 and T2 . The first turn-off takes place at a current level
dependent on T1 and the current level at the second turn-off
depends on T1 , T2 and T3 . In this paper, we are interested in
the turn-off, which takes place at the end of the first pulse.
The current level, at which the turn-off characteristics are
to be observed, can be changed by changing the width T1 . For
low values of T1 , switching characteristics are obtained at low
current level. If the value of T1 is kept high, the switching
characteristics at high current levels can be obtained.
III. E XPERIMENTAL R ESULTS AND D ISCUSSIONS
Two sets of tests are conducted: one at current level com-
parable to the rated current (i.e. high current) and other at
current level negligible compared to the rated current (i.e. low
current). Test at high current level is conducted for turn-off
switching characteristics at 18 A (about 45 % of the rated
current) while test at low current level is conducted for turn-
off switching characteristics at 0.17 A (less than 0.5 % of
the rated current). Both sets of tests are conducted with four
different values of dead-time t12 (i.e. 760 ns, 240 ns, 150 ns
and 60 ns). The dead-time t23 is kept constant at 760 ns. The
tests are conducted with a dc bus voltage of 600 V and a load
inductance of 8.5 mH.
















(a) Time Scale: 4 us/div Time Scale: 400 ns/div















(b) Time Scale: 4 us/div Time Scale: 400 ns/div















(c) Time Scale: 4 us/div Time Scale: 400 ns/div















(d) Time Scale: 4 us/div Time Scale: 400 ns/div

Fig. 4: Results of double pulse test at high device current (left-hand side figures) and corresponding turn-off characteristics
(right-hand side figures) with dead time of (a) 760 ns, (b) 240 ns, (c) 150 ns, and (d) 60 ns.
CH1 (Blue): Gate voltage, Vgs1 (20V/div), CH2 (Red): Device voltage, Vds (500V/div), CH3 (Green): Device current, Is
(10A/div), CH4 (Pink): Gate voltage, Vgs2 (25V/div)

A. Turn-off characteristics at high current levels respectively.

Fig. 4 shows the results of double pulse test conducted at
high current level. Trace 1 (blue) and trace 4 (pink) show the
gate voltages, Vgs1 & Vgs2 to the IGBTs S1 & S2 , respectively.
Voltage, Vds across the IGBT S1 and the current, Is through
it are shown by trace 2 (red) and trace 3 (green), respectively.
Fig. 4a, 4b, 4c and 4d show the results of the double pulse
test and the corresponding turn-off switching characteristics
for dead time, t12 equal to 760 ns, 240 ns, 150 ns and 60 ns,
As shown in Fig. 4a, during the turn-off transition, the
gate voltage to S1 , Vgs1 , takes certain time to decay from
the positive steady initial value to the final negative steady
value. During this transition the device voltage, Vds goes
from fully conducting state to fully blocking state. Only after
the voltage reaches its steady value, the device current, Is ,
starts decreasing. The gate voltage to the device S2 , Vgs2 ,
starts rising few hundreds of ns after the turning-off of S1 is
completed. In this case, the turn-off characteristics of S1 are






 








(a) Time Scale: 2 us/div Time Scale: 400 ns/div





 








(b) Time Scale: 2 us/div Time Scale: 400 ns/div





 








(c) Time Scale: 2 us/div Time Scale: 400 ns/div





 








(d) Time Scale: 2 us/div Time Scale: 200 ns/div

Fig. 5: Results of double pulse test at low device current (left-hand side figures) and corresponding turn-off characteristics
(right-hand side figures) with dead time of (a) 760 ns, (b) 240 ns, (c) 150 ns, and (d) 60 ns.
CH1 (Blue): Gate voltage, Vgs1 (20V/div), CH2 (Red): Device voltage, Vds (500V/div), CH3 (Green): Device current, Is
(2.5A/div), CH4 (Pink): Gate voltage, Vgs2 (25V/div)

unaffected by the switching of S2 .
For a dead time of 240 ns, Vgs2 starts increasing before
Vgs1 reaches its steady state (Fig. 4b). But still both the
voltages are not positive at any instant of time. The switching
characteristics are same as those for a dead time of 760 ns.
In the case of dead-time equal to 150 ns (Fig. 4c), turn-
off characteristics are similar to the previous two cases. Here,
during the device voltage transition, both the gate voltages,
Vgs1 and Vgs2 are positive, but are below the threshold value.
For a dead-time of 60 ns, both the devices are ON for a small
duration of time (Fig. 4d). Because of this a notch in the device
current is observed just before the fall of the current. This
represents the momentary shorting of the dc bus. Here, the
two gate voltages. Vgs1 and Vgs2 are more than the threshold
value at the instant of shoot-through.
B. Turn-off characteristics at low current levels
The results of double pulse test conducted at low current
level for different dead times are shown in Fig. 5. Trace 1
(blue) and trace 4 (pink) show the gate voltages, Vgs1 &
Vgs2 , to the IGBTs S1 & S2 , respectively. Voltage, Vds , across
the IGBT S1 and the current, Is , through it are shown by
trace 2 (red) and trace 3 (green), respectively. Results of the
double pulse test are shown in Fig. 5a, 5b, 5c and 5d. These
correspond to dead-time values of 760 ns, 240 ns, 150 ns and
60 ns respectively.
For 760 ns dead-time (Fig. 5a), the gate voltage to S1 ,
Vgs1 , takes almost the same amount of time for its complete
transition as that at high current. The device voltage, Vds , starts
rising from its initial value during the gate voltage transition.
But it does not reach its new steady state before the completion
of the gate voltage transition unlike the case at high current.
The rate of rise of the device voltage, Vds , is so small that gate
voltage to S2 , Vgs2 , starts rising before the device voltage, Vds ,
can complete its transition. When Vgs2 crosses its threshold
level, Vds reaches its final steady state value abruptly. At the
instant of this sudden transition, a spike in the current Is is
observed, which is due to charging and discarging of device
drain-source capacitances Cp across S1 and S2 . In this case,
the complete turn-off of S1 is achieved only at the turn-on of
S2 , after the completion of the dead time of 760 ns. The slow
voltage transition at the turn-off of the IGBT at low current
levels is attributed to the slow charging and discharging of
the parasitic capacitances, Cp , indicated in Fig. 2. At such
a low value of current, this process continues even after the
complete transition of Vgs1 . When the device S2 is turned
on, it discharges the capacitance across S2 , and capacitance
across S1 gets charged from the dc bus. Hence, this abrupt
charging of Cp across S1 results in completion of the voltage
transition of Vds . In this case, the voltage rise time of the
IGBT is dependent on the dead time.
In case of dead time equal to 240 ns, transition of the device
voltage, Vds , is advanced (Fig. 5b). The sudden transition is
initiated by the switching ON of S2 . In this case, magnitude
of the spike in device current, Is , is higher than that for 760
ns dead-time. This is because the device voltage before the
transition has a lower magnitude, and more current is required
to charge the parasitic capacitance, Cp . Vgs2 starts increasing
before Vgs1 reaches its steady state (Fig. 4b), similar to the
case for the same dead-time at high current. At no instant,
both the voltages are positive.
Switching characteristics for a dead-time of 150 ns (Fig. 5c)
are almost similar to those with 240 ns dead-time, except the
voltage transition is further advanced due to lower value of
dead-time. Both the gate voltages are lower than the threshold
voltages at all the instants.
But in case of dead-time equal to 60 ns (Fig. 5d), the
spike in the current is significantly higher. Since both Vgs1 &
Vgs2 are positive and above the threshold value at this instant,
an actual shoot-through occurs, and thus, a large magnitude
current spike occurs.
IV. C ONCLUSION
The turn-off characteristics of IGBT in an inverter leg
are studied experimemtally for a wide range dead-time. The
characteristics are studied while switching at high as well as
low device currents. The turn-off characteistics are found to
be significantly different at high and low currents. The device
voltage transition is fast during turn-off at high current, while
the same is rather slow when the current switched is low. This
can be attributed to the slow rate of charging of the device
capacitance when the load current is low.
This study shows that the turning-on of the complementary
device need not be deferred until the device voltage rise is
completed, while switching at low currents. Shoot-through is
observed only when the gate voltages of both the IGBTs are
above their respective threshold values. It is safe to turn on the
complementary device once the transition of the gate voltage
of the device under consideration is complete.
Hence, the dead time of the IGBTs of an inverter leg can
be designed considering the turn-off time corresponding to the
rated current rather than turn-off time at low current levels.
This results in lower values of dead-time, which is generally
desired, and more so, for high frequency operation of the
power converter.
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