COLLEGE OF COMPUTING AND INFORMATION SCIENCES

Final Assessment Spring 2020 Semester

Class Id 103336-38 Course Title Digital Logic Design
Program BSCS Campus / Shift NN Campus / Morning
Date 21st – May 2020 KIET LMS Upload Slot 6pm – 7pm
Total Marks 50 Faculty Name Sana Zafar
Student Id Student Name

Ques 1:

A large tank stores synthetic liquid formula and uses a sensor to monitor its pressure and
temperature. When the liquid formula surpasses a maximum value, a HIGH is generated by the
sensor. When either the pressure or temperature is excessive, an alarm requiring a LOW voltage
input must be activated. Design a circuit for this application.

Ques 2:

An orbiting spacecraft has a dc voltage of 12-V storage battery, which is being monitored by an ADC.
The output of an ADC is a four bit binary number, PQRS, related to the battery voltage in steps of
1V, with P as MSB. The outputs of an ADC are fed to the inputs of a logic circuit which will produce a
HIGH output as long as the binary value is greater is 0110= 6. Design the logic circuit.

Ques 3:

(a) Implement this using only NAND Gates:

PR’+ PRT + PRT’+ P’ST’ + P’S’T’
(b) Two 7485 (4 bit comparator) are used to produce inequalities (>,=, <). An external logic is
required to cascade them. Draw the logic circuit required. (use AND and OR gate)
(c) Implement the function
F(S0, S1, S2, S3) = D (D0, D1, D5, D7, D8, D10, D13, D14, D15)
Using two 8-way multiplexers with an active low enable, plus an OR gate
Ques 4:

To select 1*32 devices, four 74138 (1*8) decoder is needed. If the address bits are p, q, r, s, t then r,
s, t would be the inputs (to R, Q, P in order) for each of the four decoders and p,q would be used to
enable the appropriate one. So, that the first decoder is enable when p=q=0, the second when p=0,
and q=1 and the third when p=1 and q=0 and the fourth when p=q=1.

Since we have two active low enable inputs and one active high enable, only the fourth decoder
would require a NOT gate for the enable input assuming p’ and q’ are not available. Deisgn the logic
circuit for above.

----OR-----

A 2*4 decoder is used to select 1*16 devices. Let’s say an extra decoder is used to enable other
decoders. This extra decoder is basically used as a selector decoder for other devices (four decoders
with 2 inputs). The first two inputs are utilized in such a way: 0-3, 4-7, 8-11, 12-15. So for each
group, one decoder is used to select among the four devices in that group. Show the arrangement
of a circuit.

Ques 5:
a) Design an Asynchronous Counter which works in the range of 0-11 using J-K Flip flop
b) Design a Synchronous counter using J-K Flip Flop which will produce the following Sequence ,
1, 4, 3, 5, 7, 6, 2

Ques 6:

Design a binary synchronous counter as shown in the state diagram.

Use JK Flip flop. (0000, 0011, 0101, 0111, 1001, 1011)

UP

DOWN
Ques 7:

a) The management of a university conducted a poll where students from two different
sections are asked to either take a course or not. Suppose there are 6 students in each
section, design a circuit for 12 position polling system using adder modules and display the
result on seven segment display.

b) For the Serial-in/Parallel out Shift register, show a complete block diagram and timing
diagram. Use the waveform given below with the register initially clear.

Ques 8:

a) For the following ring counter derive the truth table.

The initial state of the counter is 1010, determine the waveform for each of the Q outputs.

b) Develop a 5-bit SISO register for the specified data input 11011. Assume that the register in
initially cleared (all 0s).