IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO.

5, MAY 2015 1433

Vertical GAAFETs for the Ultimate CMOS Scaling

Dmitry Yakimets, Student Member, IEEE, Geert Eneman, Pieter Schuddinck, Member, IEEE,
Trong Huynh Bao, Student Member, IEEE, Marie Garcia Bardon, Member, IEEE,
Praveen Raghavan, Member, IEEE, Anabela Veloso, Nadine Collaert,
Abdelkarim Mercha, Diederik Verkest, Member, IEEE,
Aaron Voon-Yew Thean, and Kristin De Meyer, Fellow, IEEE

Abstract— In this paper, we compare the performances of

FinFETs, lateral gate-all-around (GAA) FETs, and vertical
GAAFETs (VFETs) at 7-nm node dimensions and beyond.
Comparison is done at ring oscillator level accounting not only
for front-end of line devices but also for interconnects. It is
demonstrated that FinFETs fail to maintain the performance
at scaled dimensions, while VFETs demonstrate good scalability
and eventually outperform lateral devices both in speed and
power consumption. Lateral GAAFETs show better scalability
with respect to FinFETs but still consume 35% more energy per
switch than VFETs if made under 5-nm node design rules.
Index Terms— Design technology cooptimization, FinFET,
nanowire (NW), scaling, vertical gate-all-around FET (VFET). Fig. 1. 3-D sketches of different devices considered in this paper.

I. I NTRODUCTION In contrast, vertical GAAFETs (VFETs) are less constrained

C ONTINUOUS scaling suggests endless reduction of
contacted gate pitch (CGP). This results in a tradeoff
between gate length (L G ), S/D spacer thickness, and
S/D contact size in a typical lateral device. Gate should be long
enough to maintain short-channel effects (SCEs). Minimum
spacer thickness is defined by reliability requirements and/or
by capacitance between gate and S/D electrodes. Narrow
S/D contacts result in high access resistance.
CMOS scaling has been enabled by FinFETs. However, to
maintain SCE control, fin thickness should be scaled together
with gate length, which may result in too strong threshold
voltage (VT ) variability [1]. Lateral gate-all-around (GAA)
FETs made of nanowires (NWs) allow relaxed channel dimen-
sions with respect to fin thicknesses while providing similar
SCE control [2]. This suggests their better scalability and
puts off the problem of CGP budgeting but does not solve it.
Manuscript received December 18, 2014; revised February 5, 2015 and
March 13, 2015; accepted March 16, 2015. Date of publication April 2, 2015;
date of current version April 20, 2015. The review of this paper was arranged
by Editor H. Jaouen.
D. Yakimets and K. De Meyer are with imec, Leuven 3001, Belgium,
and also with the Department of Electrical Engineering, Katholieke
Universiteit Leuven, Leuven 3001, Belgium (e-mail: dmitry.yakimets@
imec.be; kristin.demeyer@imec.be).
G. Eneman, P. Schuddinck, M. G. Bardon, P. Raghavan, A. Veloso,
N. Collaert, A. Mercha, and A. V.-Y. Thean are with imec, Leuven 3001,
Belgium (e-mail: geert.eneman@imec.be; pieter.schuddinck@imec.be;
bardon@imec.be; praveen.raghavan@imec.be; anabela.veloso@imec.be;
nadine.collaert@imec.be; abdelkarim.mercha@imec.be; aaron.thean@
imec.be).
T. Huynh Bao and D. Verkest are with the imec, Leuven 3001, Belgium,
and also with Vrije Universiteit Brussel, Brussels 1050, Belgium (e-mail:
trong.huynhbao@imec.be; verkest@imec.be).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2015.2414924
0018-9383 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
on gate length and spacer thickness as they are oriented
vertically and thus should demonstrate even better scalability.
All the above-mentioned devices are sketched in Fig. 1 for
clearness.
Our previous comparison of lateral and VFETs revealed
that vertical devices may perform better than lateral ones [3].
However, vertical devices were only compared with lateral
devices made of single layer of NWs. In addition, it was
not clear if GAAFETs may compete at all with performance
provided by standard FinFETs. The aim of this paper is to
identify crossover points where VFETs start to outperform
FinFETs and lateral GAAFETs. In addition, as vertical
architecture is quite disruptive, it should demonstrate good
scalability with a perspective for further nodes.
This paper is organized as follows. Section II presents
the description of lateral and vertical layouts along with the
assumptions on key design rules. Section III describes the
modeling methodology of the intrinsic device performance
and related device RC parasitics. We discuss the results of
our benchmarking study between FinFETs, lateral GAAFETs,
and VFETs on ring oscillator (RO) level in Section IV.
The advantages and limits of the different technologies are
quantified, providing insight on their relative performance.
II. D EVICE L AYOUTS D ESCRIPTION
Three device types are compared in this paper (Fig. 1).
Layouts of standard cells depend on the device choice and,
in turn, define device dimensions. FinFETs and lateral
GAAFETs result in identical layouts as from the top-down
view they see the same footprint. The cells height is assumed
to be nine tracks [a single track corresponding to a one metal
pitch (MP)]. The fin pitch (FP) is set to 3/4 of the MP to

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1434
Fig. 2. Layouts of lateral (left) and vertical (right) devices. VFETs-based
cells are taller than lateral FETs-based cells but do not require dummy gates,
which results in the similar cells area.
provide the best fins utilization within a cell: both nMOS and
pMOS consist of four fins each. The rest of the cell is used
to enable power supply connection and gate access (Fig. 2).
Layouts of VFETs-based standard cells are different. They
are difficult to interpret, because from the top-down view all
the electrodes (top, gate, and bottom) overlap. It is natural to
drive power rails above the top electrodes to ease contacting.
This choice implies a need for extra routing tracks resulting in
taller standard cells with respect to lateral devices. We assume
13 tracks designs for the vertical architecture. Such an increase
of the height of the VFETs-based cells is possible as they do
not require dummy gates at the edges of the cells. Lateral
devices use them to separate fins between cells (Fig. 2).
To ensure comparison under the same footprint, the vertical
device pitch (VDP) should be linked with the CGP of lateral
devices with
Hl N + 1
VDP = CGP (1)
Hv N
where Hl = 9 and Hv = 13 for lateral and vertical standard
cell’s height expressed in number of tracks, respectively;
and N is a cell’s width in a number of stacked devices.
The extra unity in the numerator accounts for dummy gates
in lateral devices. N = 2 for a NAND 2 cell and thus
VDP = 1.04 CGP, so VDP and CGP are almost equal. In [4],
we have already demonstrated that VFETs are beneficial for
complex designs (e.g., a VFETs-based 32-bit multiplier
is 19% smaller compared with its lateral version) while still
starting with an assumption of equal lateral and vertical
NAND 2 cell area.
Analysis is done for 7- and 5-nm technological nodes with
an assumption of standard 0.7× scaling. Key ground rules
assumed for these nodes are summarized in Table I. All the
layouts exploit unidirectional metal routing in case the 193-nm
immersion lithography would be used [5]. Yet, designs are
compatible with an extreme ultraviolet lithography, which
might reduce a number of lithography masks needed. The
NW pitch in a VFET may be tighter than the lateral
FP if a directed self-assembly is used for NWs patterning
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 5, MAY 2015
TABLE I
K EY S CALING TARGETS FOR D IFFERENT T ECHNOLOGICAL N ODES
Fig. 3. Device modeling flow from TCAD to SPICE simulations.
Fig. 4. Fitting of SS and DIBL from CM to the TCAD data for FinFETs
(fin width is 5 nm) and GAAFETs (NW diameters are 7 and 10 nm).
CM data are lines and TCAD data are symbols.
as it allows both critical dimensions shrinking and pattern
multiplication [6].
We may calculate how many NWs a VFET consists of,
assuming that the NWs are placed in a single line to ease
gate-stack processing (Fig. 2). The number of NWs is limited,
because the zone where NWs should be placed is only four
MP long (Fig. 2). For both 7- and 5-nm technologies, we
assume a physical oxide thickness to be 2 nm. In this case,
seven NWs per device can be used for both nodes if NW pitch
is equal to 0.58× of the MP. For the 5-nm technology,
NW pitch results in ∼14 nm. The minimum NW diameter
was assumed to be 7 nm and the maximum possible
NW diameters (Dmax ) depend on the technology and are given
in Table I.
III. D EVICE M ODELING D ETAILS
A. General Overview
TCAD data were used to calibrate the Berkeley Spice Com-
mon Multi-gate FET (BSIM-CMG) compact model (CM) [7],
which was used afterward in the SPICE simulations. The over-
all flow is schematically shown in Fig. 3. Synopsys Sentaurus
Device [8] was used to obtain subthreshold characteristics
(Fig. 4). However, TCAD drift-diffusion (DD) models fail to
accurately predict drive because they do not take the quasi-
ballistic (QB) transport into account. Therefore, Synopsys
Sentaurus Band Structure [9] top of the barrier simulations
YAKIMETS et al.: VERTICAL GAAFETs FOR THE ULTIMATE CMOS SCALING
Fig. 5. Ninv and v inj as function of gate voltage (left) and applied
stress (right) for a nMOS FinFET. Fin height is 30 nm and fin width is 5 nm.
IOFF = 3.5 nA, S/D resistances, and SCEs are ignored.
were carried for different device structures to determine bal-
listic currents. Device RC parasitics up to Metal 1 level were
calculated analytically and were included in the analysis as
lumped components.
B. Drive Strength
The BSIM-CMG CM is a DD model. Extending it toward
the QB transport is done by the adjustment of low-field
mobility and saturation velocity values [10], [11]. This section
discusses how these adjustments may be implemented.
If parasitic S/D resistances and SCEs are ignored, the fully
ballistic current may be expressed as
IDS = q Ninv v inj
where q is a charge, Ninv is a number of inversion carriers,
and v inj is an injection velocity. Synopsys Sentaurus Band
Structure simulations provide data on Ninv and v inj as a
function of the applied voltage and stress in the channel.
In case of silicon, Ninv weakly depends on the applied
stress and is defined by the gate voltage, while v inj is rather
insensitive to a device bias, but is a strong function of
stress (Fig. 5).
First, the CM should be tuned to operate with the same
charge as TCAD predicts. This may be done by adjusting
the position of the charge centroid (this affects W and COX
calculations). Proper VT is set by work-function adjustment.
The second step is to reproduce current predicted by TCAD.
Synopsys Sentaurus Band Structure provides information on
the full ballistic current only. To calculate the realistic satu-
ration current, the ballistic ratio (BR) may be used. BR is a
function of a gate length, and so is the device current
IDS (L G ) = BR(L G )Ibal .
Moroz et al. [12] provide data on BR(L G ) for both
stressed (2 GPa) and relaxed devices. We assume lateral
devices to be well stressed to boost mobility and injection
velocity (2 GPa for nMOS and −2 GPa for pMOS). However,
there is no known way to introduce stress into the channel of
a VFET.
The CM may be fitted for the IDS (L G ) by setting the
saturation velocity parameter to be a function of the gate
length. However, to capture both saturation and linear currents,
the carriers mobility should be adjusted as well. The long-
channel mobility should be replaced by the apparent mobility
due to ballistic mobility reduction and additional scattering
mechanisms [13]. We assumed a moderate [14] mobility
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1435
Fig. 6. Sketches of different devices showing parasitics considered in
this paper. Left: source side of a FinFET and drain side of a lateral GAAFET.
Right: VFET.
reduction by setting αμ = 0.07 nm V s cm−2 for relaxed
devices [15] and a bit lower αμ = 0.05 nm V s cm−2 for
stressed devices [10]. This parameter is used in (4) to calculate
apparent mobility with the Mathiessen’s rule
1 1 αμ
= + (4)
μapp μlch LG
where μapp is an apparent mobility and μlch is a
long-channel mobility. For the lateral devices, μlch is
300 and 400 cm2 V−1 s−1 for electrons and holes, respec-
(2) tively [16]. For the VFETs, the mobility is twice lower for
both electrons and holes due to the absence of stress in the
channel.
In addition, SCEs should be captured by the CM. Data on
electrostatics were obtained through simulations in Synopsys
Sentaurus Device using recommended leakage and quantiza-
tion models for 10-nm technological node Si bulk FinFETs [8].
The equivalent oxide thickness (EOT) was kept constant across
the technologies and equal to 0.765 nm, which corresponds to
the gate dielectric composed of 0.5-nm thick SiO2 and 1.5-
nm-thick HfO2 . The obtained data on subthreshold slope (SS),
threshold voltage roll-off, and drain-induced barrier lowering
(DIBL) were fitted for different devices (Fig. 4).
C. Device Parasitics
Device RC parasitics up to Metal 1 level were modeled ana-
lytically, as shown in Fig. 6. The analytical models were based
on the published data [17]–[20] and partially calibrated with
the numerical analysis. Junction capacitances in lateral devices
(3)
were handled by the BSIM-CMG CM. For the vertical devices,
junction capacitances were neglected as the bottom electrode
is separated from the substrate by the insulator (Fig. 6) and
hence junctions are only formed at the small interface between
the NW and the substrate.
For the lateral devices, we assumed diamond-shaped
epitaxial SiGe and SiC S/D structures with 70° top angle
for pMOS and nMOS, respectively. The doping inside the
extension regions was assumed conformal, due to its narrow
cross section. The optimistic assumption of equally high
doping level (3 × 1020 cm−3 ) in the extensions and the
epitaxial S/D structures was made to reduce their resistivity.
The same high doping was also used for the VFETs extensions.
To maximize contacting area for lateral devices, we assumed
1436
Fig. 7. Parasitics comparison for different device architectures for 5-nm
technological node. Resistances at the top (for lateral devices R S = R D )
and capacitances at the bottom (both channel and Miller gate to drain
capacitances). Assumed gate length is 14 nm and spacer thickness is 5 nm.
For lateral NWFETs, three options are reported with different number (N ) of
stacked NWs (labeled as 4 × N ).
that S/D epitaxial structures were grown just until they touched
each other but did not merge. Specific contact resistivity
between silicon and metal was 5 × 10−9  cm2 [21]. For the
VFETs, we assumed the electrodes to be made of tungsten
with a thickness set to MP. Thick electrodes helped to reduce
contact resistance with NWs (RCB and RCT in Fig. 6).
Vertical pitch between the NWs in lateral GAAFETs
was 14 nm as these devices are normally fabricated from
Si/SiGe superlattice, which can enable very tight pitches.
For lateral devices, gate height above the top of a fin/NW
was 25 nm. We assumed that the same spacer material
was used for all the devices with an effective dielectric
permittivity of 5.5.
Vertical devices are asymmetric: R S = R D . The bottom
electrode is only accessible through the narrow and deep
(thus highly resistive) via. On top of that, as the contacting
to the bottom electrode is done from its short side, there is
a highly resistive path between the first and the last NW in
the line. The top electrode is free of these issues: we assumed
that the current flows uniformly though the entire top electrode
surface as a contact is placed on top of it (inbound power
rails, Fig. 2). Therefore, to capitalize VGS in VFETs, source is
placed at the top electrode and drain is at the bottom electrode.
Parasitics comparison between the devices at 5-nm
technological node is shown in Fig. 7. Gate length here was
set to 14 nm and spacer thickness to 5 nm. For lateral devices,
access resistance is limited by S/D contacts. Contact resistance
together with tungsten plugs resistance (RC and R S/D cont
in Fig. 6, respectively) account for 70% of the total resistance.
Contact resistance does not improve if extra NWs are added
to a stack in lateral NWFETs. However, with every extra
stacked NW, gate capacitance increases linearly, which may
severely degrade RO performance (Section IV-B).
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 5, MAY 2015
Fig. 8. Saturation current versus gate length for different devices at 5-nm
technological node. VDD = 0.6 V. For all the devices, S/D spacer thickness
is set to 5 nm. Lateral NWFETs are made of a single layer of NWs.
(a) Ideal situation, when SCEs are neglected and S/D access resistance is
zero. (b) S/D access resistance is zero, but the SCEs from Fig. 4 are used.
(c) Both SCEs and S/D access resistance are considered.
D. Total Device Performance
Using the obtained CMs, we now compare the devices
at two different leakage levels: 10 and 0.1 nA. Gate
work-function is adjusted to achieve same leakage for any
device geometry. SCEs and parasitics resistances are added
successively on the initial ideal devices to understand their
relative impacts (Fig. 8). VFETs are made of seven NWs,
FinFETs have four fins, and lateral GAAFETs have four fins,
which are split into several stacked NWs. First, lateral
GAAFETs are assumed to have just a single layer of NWs.
For the ideal case, FinFETs outperform NWFETs, because
of almost four times larger channel cross-sectional area.
As VFETs are not strained, current from them is comparable
with the one from lateral GAAFETs despite the different
number of NWs [Fig. 8(a)]. At low leakage, steep SS is
important and that is why FinFETs performance at short gate
lengths is degraded [Fig. 8(b)]. For long gates, current drops
because of S/D parasitic resistances [Fig. 8(c)]. The higher the
initial current, the higher the degradation, because of larger
voltage drop at these resistances and thus lower effective
device biasing. Thus, FinFET currents in a low-leakage regime
are similar to NWFET currents.
For the high-performance regime, FinFETs still deliver
more current than NWFETs. A possible solution for lateral
GAAFETs is to stack NWs on top of each other (Fig. 9).
Eight layers of NWs were stacked, but the current was boosted
by three times only with respect to an initial case. This limited
increase happens due to a high S/D contact resistance.
YAKIMETS et al.: VERTICAL GAAFETs FOR THE ULTIMATE CMOS SCALING
Fig. 9. Saturation current of the lateral GAAFET as a function of a
number of stacked NWs. Leakage is constant because of work-function
adjustments.
TABLE II
RC -D ELAY OF THE 100 CGP L ONG W IRE I NCREASES W ITH S CALING
IV. R ING O SCILLATOR L EVEL B ENCHMARKING
A. General Overview
As the benchmark, we used the 15 stages fan-out = 1
inverter-based RO with an RC load between the adjacent
stages to imitate the back-end of line (BEOL). Simulations
were made in SPICE. Within every technological node, devices
geometrical configurations were optimized to have a minimum
delay. To maintain desired leakage constant, the work-function
was adjusted prior to the simulations. Optimization was
performed with the Nelder–Mead simplex method [22]. For
FinFETs, fin thickness was fixed at 5 nm. NW diameter
for lateral GAAFETs was fixed at 7 nm. For the VFETs,
NW diameter was varied from 7 nm to Dmax value
from Table I. S/D spacer thickness was varied from 4 to 10 nm.
Gate length was varied from 10 to 30 nm for VFETs. For
lateral devices, the upper limit on gate length was set by CGP,
assuming the minimum S/D contact width to be 5 nm.
Simulations in Sections IV-B and IV-C consider load from
100 CGP long interconnects, and Section IV-D discusses the
impact of the wire length on the RO performance. We assumed
interconnects are made with 1/2-MP wide and MP tall copper
wires. Diffusion metal barriers are manganese-based and
1-nm thick. The wire RC parasitics are calculated as proposed
in [21] with an assumption of the uniform dielectric (εr = 2.1)
around the wire. These data are summarized in Table II.
B. Optimization Results for Lateral Devices
Because of the high front-end of line capacitance, the
optimal fin height in FinFETs [Fig. 10(a)] and the optimal
number of stacked NWs in lateral GAAFETs [Fig. 10(b)] tend
to decrease with scaling to maximize the overall performance.
The fine gate length optimization depends on the VDD choice.
At high VDD , requirements for SS are less strict because of
more overdrive available. In addition, high currents at high
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1437
Fig. 10. (a) Optimal (minimum RO delay) fin height and gate length
combinations for different VDD . (b) Impact of a number of stacked NW layers
in lateral GAAFETs on RO delay (L G and spacer thickness are optimized for
minimum RO delay at every point).
Fig. 11. Performance of ROs built with different devices across different
technological nodes. Devices at every point are optimized for minimum
RO delay. Figures on the left demonstrate key figure of merits for the
high-performance flavor (IOFF = 10 nA) as a function of VDD . Figures
on the right show the performance of different devices at different flavors
(10 and 0.1-nA leakage current) for VDD = 0.50 V and VDD = 0.65 V.
VDD make devices more sensitive to a S/D resistance. Shorter
gates allow wider contacts, lowering this resistance.
C. Performance Scaling Across Nodes
At the 7-nm technological node, VFETs cannot reach the
performance of lateral devices (Fig. 11). In case of high
supply voltage (0.65 V), FinFETs provide performance similar
to the lateral stacked GAAFETs. Once the VDD is reduced,
FinFETs start to lag behind especially for the low-leakage
flavor [Fig. 11 (right)]. Yet, lateral stacked GAAFETs
consume less power for both high-performance and
low-leakage regimes. However, lateral GAAFETs made
with the 5-nm design rules fail to keep up 7 nm-like
performance. In turn, VFETs get faster and achieve the best
performance and power consumption at the 5-nm node. This
demonstrates their good scalability.
The performance should be maintained or improved with
scaling. In addition, the power consumption should be reduced
to justify the scaling. In case the nominal VDD for the 7-nm
technological node is 0.6 V, the lateral NWFETs made with
the 5-nm node design rules provide equal performance only
at 0.65 V. Lack of VDD reduction means that area reduction
is the only gain from scaling, but not speed or power.
1438
Fig. 12. (a) Impact of the interconnect wire length on the RO frequency
at 5-nm node. All the devices are optimized for the maximum performance
under 100 CGP long wire load. Wire length is expressed in a number of CGPs.
VDD = 0.6 V and leakage current is 10 nA. (b) RO effective capacitance
increases by 10–15 times with wire length increase from 10 to 1200 CGP.
(c) However, the RO effective resistance increases by only 1.7–2 times for
the same wire length increase. RO Ceff and Reff data are normalized to the
Ceff and Reff values of the RO loaded with the shortest (10 CGP long) wire.
VFETs provide both area (50% smaller cells) and power
reduction (∼37%) maintaining the performance of the 7-nm
technology. This power reduction comes not from the
VDD reduction, but from the device architecture: 5-nm VFETs
provide sufficient performance only at 0.6 V.
However, beyond 5-nm technological node it gets difficult to
place NWs within a device, which is four MP long (Fig. 2).
MP keeps scaling, while NW diameter is unlikely to scale
much. To maintain the performance, we propose slab-like
structures where NWs are merged to increase the conducting
volume. Inevitably electrostatics gets degraded but it may
be recovered with longer gates. Probably, alternative channel
materials will allow to maintain the performance with fewer
NWs per device. Though high-mobility materials is a possible
path for VFETs, they might turn out to be inefficient for
lateral devices, as their poor scaling is mostly related to a high
S/D access resistance. Alternative channel materials have
similar to silicon specific contact resistivity [23] and thus
benefits from their potentially high mobility and injection
velocity are expected to be limited.
D. Interconnect Wire Length Impact on RO
Length of 90% wiring is <1250 CGP [24]. However,
the RO performance drops dramatically for such long wires
[Fig. 12(a)] meaning that these wires should be fragmented
and be driven by intermediate buffers. Fig. 12(a) also gives an
insight on how long an interconnect wire can be depending
on the device architecture. VFETs are most suited for
short wires, and their benefits diminish for long wires. Due
to low VFETs device parasitic capacitances and limited
drive, these devices are most sensitive to the interconnect
capacitance [Fig. 12(b)]. The relative impact of the resistive
component of the BEOL load is less than that of the capacitive
component [Fig. 12(c)]. As such, VFETs fail to provide a suf-
ficient current to drive a long interconnect wire. RO effective
capacitance and resistance were calculated from the RO delay
(τ ), active (PAct ), and leakage (PLeak ) power consumptions as
Ceff = 2τ (PAct − PLeak )/VDD 2 , and R
eff = τ/Ceff .
V. C ONCLUSION
Lateral stacked GAAFETs may provide 10%–15%
power savings with respect to FinFETs already at the
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 5, MAY 2015
7-nm technology node. However, further scaling of lateral
devices is strongly limited by access resistance. Even though
NWs allow aggressive gate length scaling, contact resistance
still limits the performance. Lateral devices fail to deliver
sufficient performance at 5-nm technological node together
with power reduction. In contrast, VFETs demonstrate good
node-to-node scalability and enable power, performance,
and area gains beyond 7-nm technologies. As such, VFETs
should be considered as a prominent option for the ultimate
CMOS scaling.
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Dmitry Yakimets (S’12) received the B.Eng. degree
in electronics design and manufacturing from
Bauman Moscow State Technical University,
Moscow, Russia, in 2010, and the M.Sc. degree
in nanotechnologies for ICT engineering from the
Institut Polytechnique de Grenoble, France, in 2012.
He is currently pursuing the Ph.D. degree with the
Department of Electrical Engineering, Katholieke
Universiteit Leuven, and imec, Leuven, Belgium.
Geert Eneman received the B.S., M.S., and
Ph.D. degrees from the Katholieke Universiteit
Leuven, Leuven, Belgium, in 1999, 2002, and
2006, respectively, and the Ph.D. degree from imec,
Leuven.
He has been with imec since 2011. His current
research interests include characterization of
Ge and III–V MOSFETs, and modeling of
alternative device structures.
Pieter Schuddinck (M’12) received the
M.Sc. degree in electrotechnical engineering
from Ghent University, Ghent, Belgium, in 2005.
He has been involved in electronics research in
both private and academic institutions. He joined
imec, Leuven, Belgium, as a Design Engineer,
in 2011, where he has focused on modeling and
evaluation of FE/MOL parasitic impedances in
advanced technology nodes.
Trong Huynh Bao (S’13) received the M.Sc. degree
from the Politecnico di Torino, Turin, Italy, in 2012.
He is currently pursuing the Ph.D. degree with imec,
Leuven, Belgium, and the Department of Electronics
and Informatics, Vrije Universiteit Brussel, Brussels,
Belgium.
His current research interests include circuit design
techniques in the nanoscale CMOS era and design
technology co-optimization.
Marie Garcia Bardon (M’14) received the
M.Sc. degree in electromechanical engineering
from the Université Catholique de Louvain,
Louvain-la-Neuve, Belgium, in 2004, and the
Ph.D. degree in microelectronics from the
Katholieke Universiteit Leuven, Leuven,
Belgium, in 2010, in collaboration with imec,
Leuven, Belgium.
She is currently with imec.
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Praveen Raghavan (M’04) received the bachelor’s
degree in electrical engineering from National
Institute of Technology, Tiruchirappalli,
Tiruchirappalli, India, the master’s degree
in electrical engineering from Arizona State
University, Tempe, AZ, USA, and the Ph.D. degree
from the Katholieke Universiteit Leuven, Leuven,
Belgium, in 2009.
He is currently a Principal Scientist with the
Design-Enabled Technology Exploration Group,
imec, Leuven.
Anabela Veloso received the B.S. and M.S. degrees
in applied physics engineering from the Instituto
Superior Técnico, Technical University of Lisbon,
Lisbon, Portugal, in 1996, and the Ph.D. degree
in advanced magnetic read heads from the
Instituto Superior Técnico, Instituto de Engenharia
de Sistemas e Computadores, Lisbon, in 2002.
She has been with imec, Leuven, Belgium, since
2001, where she is currently a Principal Engineer.
Nadine Collaert received the M.S. and Ph.D. degrees in electrical engineer-
ing from the Department of Electrical Engineering, Katholieke Universiteit
Leuven, Leuven, Belgium, in 1995 and 2000, respectively.
She has been a Program Manager of the Logic Program with imec, Leuven,
Belgium, since 2012, where she has been focusing on 10-nm technology
nodes.
Abdelkarim Mercha received the M.Sc. degree
in electrical engineering from the École Nationale
Supérieure d’Ingenieurs de Caen, Caen, France, in
1997, and the Ph.D. degree in microelectronics from
the University of Caen, Caen, in 2000.
He joined imec, Leuven, Belgium, in 2001, where
he is currently a Program Manager of the Integrated
Solution for Technology Exploration Program.
Diederik Verkest received the Ph.D. degree in
applied sciences from the Katholieke Universiteit
Leuven, Leuven, Belgium, in 1994.
He has been the Director of INSITE Program,
imec, Leuven, since 2010, where he has been focus-
ing on co-optimization of design and process tech-
nology for sub-20-nm nodes. He has authored and
presented over 150 articles in international journals
and international conferences.
Dr. Verkest is a Golden Core Member of the IEEE
Computer Society.
Aaron Voon-Yew Thean received the B.Sc., M.Sc.,
and Ph.D. degrees in electrical engineering from the
University of Illinois at Urbana-Champaign, Urbana,
IL, USA.
He is currently the Director of the Logic Program
with imec, Leuven, Belgium.
Kristin De Meyer (S’73–M’79–SM’00–F’11)
received the Ph.D. degree from the Katholieke
Universiteit Leuven, Leuven, Belgium, in 1979.
She is currently the Director of Doctoral Research
and was a Coordinator of several EEC projects at
imec, Leuven, Belgium. She has co-authored over
500 publications.