IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO.
4, DECEMBER 2003
A Novel Multibridge-Channel MOSFET (MBCFET):
Fabrication Technologies and Characteristics
Sung-Young Lee, Sung-Min Kim, Eun-Jung Yoon, Chang-Woo Oh, Ilsub Chung, Donggun Park, and
Kinam Kim, Fellow, IEEE
Abstract—We have demonstrated a novel three-dimensional
multibridge-channel metal–oxide–semiconductor field-effect
transistor (MBCFET). This transistor was successfully fabricated
using a conventional complementary metal–oxide–semiconductor
process. We introduce the fabrication technologies and electrical
characteristics of MBCFET in comparison with a conventional
planar MOSFET. The MBCFET has more benefits than a con-
ventional MOSFET. It shows 4.6 times larger current drivability
than a planar MOSFET. This is due to the vertically stacked
multibridge channels. The subthreshold swing of MBCFET is
61 mV/dec, which is almost an ideal value due to the thin body
surrounded by gate. Based on a simulation result, we show that
the MBCFET will have a large on–off state current ratio at short
channel transistors.
Index Terms—Multibridge-channel metal–oxide–semicon-
ductor field-effect transistor (MBCFET), vertically stacked
multibridge channels.
I. INTRODUCTION
T O ACHIEVE THE high-density device with high perfor-
mance and low power dissipation, the transistor has been
scaled down aggressively in its size and operating voltage. Inter-
national Technology Roadmap for Semiconductor (ITRS) 2002
predicts that the transistor gate length is expected to be reduced
by 15% every year, while the current drivability requirement
remains the same for the reduced operating voltage.
Since improving the performance and scaling down the gate
length of the transistor have faced many technological barriers
to overcome, many alternative solutions have been investigated.
One of the solutions is a novel process technology, such as
the damascene process [1], which overcomes the lithography
limit. Another solution is using the new gate electrodes and
dielectrics to reduce the gate poly depletion and gate leakage
current. Recently, three-dimensional (3-D) transistor structures
such as FinFET, double-gate ultra-thin body (UTB) FET, and
gate-all-around (GAA) FET have been proposed and exten-
sively studied [2]–[5] as a promising solution to reduce short
channel effect (SCE) and performance degradation. Alternative
materials will be the long-term solutions to circumventing
the scaling issues because of their integration difficulties
Manuscript received July 17, 2003; revised August 15, 2003. This work was
presented in part at the Silicon Nanoelectronics Workshop, Kyoto, Japan, June
2003.
S.-Y. Lee, S.-M. Kim, E.-J. Yoon, C.-W. Oh, D. Park, and K. Kim are with
the Samsung Electronics Company, Kyungki-Do 449-711, Korea (e-mail:
afc.lee@samsung.com).
I. Chung is with the School of Information and Computer Engineering,
SungKyunKwan University, Kyungki-Do 440-746, Korea.
Digital Object Identifier 10.1109/TNANO.2003.820777
1536-125X/03$17.00 © 2003 IEEE
253
and reliabilities. However, the combinations of new process
technology and novel transistor structure with complementary
metal–oxide–semiconductor (CMOS) compatibility can be
both short-term and long-term solutions to proceed with the
CMOS scaling.
So, several researchers have reported and presented tran-
sistor performance improvements, thanks to the 3-D transistor
structures [2]–[5]. However, their fabrication processes were
very difficult to manufacture and it is hard to control the
process parameters. Also, further performance improvements
are required in their characteristics such as current drivability,
off-state leakage current, and so on.
Therefore, in this paper, we propose a novel and manufac-
turable multibridge-channel metal–oxide–semiconductor field-
effect transistor (MBCFET) structure fabricated on bulk Si sub-
strate. And we describe the detailed processes to fabricate the
MBCFET, including epitaxial growth of the SiGe/Si multilayer.
Transistor characteristics and simulation results are also pre-
sented.
II. TRANSISTOR FABRICATION TECHNOLOGIES
The MBCFET fabrication processes are schematically illus-
trated in Fig. 1. To prevent the parasitic transistor operation
at the bulk Si substrate, channel isolation ion implantation is
applied before the epitaxial growth of multiple Si Ge and
Si layers [Fig. 1(a)]. With the UTB silicon-on-insulator (SOI)
wafers, this process can be eliminated and simplified. Besides,
the additional UTB transistor can be formed on the bulk Si.
The epitaxial layer thickness of Si Ge , alternately grown
with Si on (100) Si substrate, should be controlled below a crit-
ical thickness that starts to generate defects such as misfit dis-
locations or other crystal defects. If we control the number of
SiGe/Si alternating epitaxial layers, we can control the number
of channels, i.e., the inversion charges that determine the cur-
rent drivability of MOSFETs.
An oxide dummy gate is used as a hard mask to etch the epi-
taxial layers at the source/drain (S/D) region. After etching the
S/D region, a thin source drain extension (SDE) layer is formed
by Si selective epitaxial growth (SEG) as shown in Fig. 1(d) and
Fig. 2. The SDE layer is doped by tilted ion implantation.
After a poly-Si deposition to fill the S/D region, chemical
mechanical polishing (CMP) and etchback of poly-Si are per-
formed to planarize the S/D poly-Si, as shown in Fig. 1(e). Then,
thick SiN is deposited and planarized by CMP. After the re-
moval of dummy gate, the multibridge channel (MBC) region is
implanted with multiple energy to adjust the threshold voltage
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Fig. 1. Schematic diagrams for MBCFET fabrication.
Fig. 2. Scanning electron microscope photograph after Si SEG of Fig. 1(d).
Fig. 3. Bird’s-eye view of Fig. 1(g).
, as shown in Fig. 1(f). We anisotropically etched the oxide
of shallow trench isolation (STI) using SiN and Si hard masks,
which is followed by the selective Si Ge removal to form
the structure of Fig. 1(g). Fig. 3 shows the bird’s-eye view after
the completion of this process.
One of the key technologies to form this MBCFET is highly
selective Si Ge removal over Si. As shown in Fig. 4, the
Si Ge layers were selectively removed against Si with the
selectivity higher than 300 : 1 [6].
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
Fig. 4. Highly selective etching profile of SiGe over Si has been successfully
achieved.
Fig. 5. Final profile of MBCFET. Si body (channel) thickness is 32 nm.
Gate oxidation 2.5 nm thick, using N O, N + doped poly-Si
deposition, CMP, and SiN strip, are successively performed to
form the gate of -channel MBCFET. Thereafter, conventional
CMOS processes are applied to finish the transistor fabrication.
Fig. 5 shows the final profile of the MBCFET. Floating Si body
thickness is 32 nm.
The implantation processes of a planar MOSFET are the
same as those of the MBCFET, except for channel-isolation
LEE et al.: NOVEL MULTIBRIDGE-CHANNEL MOSFET (MBCFET): FABRICATION TECHNOLOGIES AND CHARACTERISTICS 255

Fig. 8. Since the channels are all floating and surrounded by gate, no body-bias
Fig. 6. characteristics of MBCFET. The of MBCFET is effects are observed in the MBCFET.
38 at , while the planar MOSFET shows the
of 2.9 .

Fig. 7. characteristics of MBCFET. of MBCFET is lowered due

to the thin body surrounded by gate as well as the lightly doped channel. Fig. 9. Simulation result of of MBCFET and planar MOSFET.

implantation and SDE implantation. Both a planar MOSFET
and the MBCFET have no halo implantation in fabrication, but
a planar MOSFET only has a halo implantation process in case
of simulation.
III. TRANSISTOR CHARACTERISTICS AND DISCUSSION
Figs. 6 and 7 show the and the character-
istics of the -channel MBCFET with L m, W m tors have low subthreshold swing because of long channel, the
comparing with those of the -channel planar MOSFET.
The threshold voltage of MBCFET is 0.1 V, while the
of planar MOSFET is 0.45 V. The current drivability of
MBCFET is 38 at , while planar
MOSFET shows 2.9 . MBCFET shows 13 times larger
current drivability than planar MOSFET. When we consider
the difference between MBCFET and planar MOSFET,
the MBCFET shows a 4.6 times larger current drivability than
that of planar MOSFET, according to the simple mathematical
calculations of current drivability. Although the actual transistor
width was increased four times due to the vertically stacked
multiple channels of the MBCFET, mobility enhancement
thanks to the thin-body double-gate structure of the MBCFET
resulted in a 4.6 times larger current drivability in compar-
ison with that of planar MOSFET. Since depletion charge is
small enough in thin-body MBCFET, carriers in the inversion
layer encounter a smaller vertical electric field in thin-body
MBCFET than in planar bulk MOSFET with relatively heavy
channel doping. This reduction in vertical field is expected to
improve carrier mobility [7].
We think that the low of MBCFET is due to thin body
surrounded by gate. The subthreshold swing of MBCFET is
61 mV/dec, that is, almost ideal value, while planar MOSFET
shows 87 mV/dec, as shown in Fig. 7. Even though both transis-
ideal value of MBCFET is remarkable. We think that this comes
from the thin body surrounded by gate as well as lightly doped
channel.
In Fig. 8, we show that MBCFET has no body-bias depen-
dency. It means that MBCs of MBCFET are electrically all
floating and fully depleted by the surrounding gate. It can be
a clear evidence for current flow in the floating channels of
MBCFET, not body.
Fig. 9 shows the simulation result of on–off current charac-
teristics for planar MOSFET and MBCFET. From that result,
we know that MBCFET has much less off-state current at the
same on-state current. The kink in planar MOSFET shown in
Fig. 9 is due to halo implantation. High due to halo im-
plantation in planar MOSFET reduces off-leakage currents with
decreasing gate length for a few points in Fig. 9. When we
compare on–off current characteristics between MBCFETs, the
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MBCFET having a thin Si body shows superior characteristics
to another one. Therefore, if we are thinning down the epitaxial
Si layers surrounded by gate, we can maximize the on–off state
current ratio. The simulation result in Fig. 9 also shows the ben-
efits of MBCFET with short channel transistors that we are fo-
cusing as a further study.
IV. CONCLUSIONS
We proposed a novel 3-D MOSFET, MBCFET, and success-
fully fabricated it using a conventional CMOS process. The
MBCFET shows a 4.6 times larger current drivability than a
conventional planar MOSFET at the same threshold voltage,
due to the vertically stacked double-bridge channels. The sub-
threshold swing of MBCFET is 61 mV/dec, that is, almost ideal
value, due to a thin body surrounded by gate. Since the number
of channels can be controlled by a simple process modification,
we expect that the MBCFET will be a promising candidate tran-
sistor for the future nanoscale CMOS technology era.
REFERENCES
[1] C.-W. Oh, S.-H. Kim, C.-S. Lee, J.-D. Choe, S.-A. Lee, S.-Y. Lee, K.-H.
Yeo, H.-J. Jo, E.-J. Yoon, S.-J. Hyun, D. Park, and K. Kim, “Highly man-
ufacturable sub-50 nm high-performance CMOSFET using real dama-
scene gate process,” in Symp. VLSI Technology, 2003, p. 147.
[2] Y. K. Choi, T.-J. King, and C. Hu, “Nanoscale CMOS spacer FinFET for
the terabit era,” IEEE Electron Device Lett., vol. 23, p. 25, Jan. 2002.
[3] S. Monfray and T. Skotnick et al., “50 nm-gate all around (GAA)-sil-
icon on nothing (SON) devices: A simple way to co-integration of GAA
transistors within bulk MOSFET process,” VLSI Technol., p. 108, 2002.
[4] M. Kumar, H. Liu, and J. K. O. Sin, “A high-performance five-channel
NMOSFET using selective epitaxial growth and lateral solid phase epi-
taxy,” IEEE Electron Device Lett., vol. 23, p. 261, May 2002.
[5] S. Cristoloveanu, F. Allibert, and A. Zaslavsky, “Double-gate MOS-
FETs: performance and technology options,” in Proc. Semiconductor
Device Research Symp., 2001, p. 459.
[6] S. M. Kim, C.-W. Oh, J.-D. Choe, C.-S. Lee, and D. Park, “A study
on selective Si Ge etch using polysilicon etchant diluted by H2O
for three-dimensional Si structure application,” presented at the Proc.
Electrochemical Society Meeting, Paris, France, Apr. 2003.
[7] L. Chang, K. J. Yang, Y.-C. Yeo, I. Polishchuk, T.-J. King, and C. Hu,
“Direct-tunneling gate leakage current in double-gate and ultrathin body
MOSFETs,” IEEE Trans. Electron Devices, vol. 49, pp. 2288–2295,
Dec. 2002.
Sung-Young Lee received the B.S. and M.S. degrees
in materials science and engineering from Korea Uni-
versity, Seoul, Korea, in 1990 and 1992, respectively.
He is currently working towards the Ph.D. degree in
electrical engineering at SungKyunKwan University,
Kyungki-Do, Korea.
Since 1993, he has been with Samsung Electronics
Company, Ltd., Kyungki-Do, Korea. His research
interests include nano-CMOS structure and tech-
nology, memory devices, and nanocharacterization
using scanning probe microscopy.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003
Sung-Min Kim received the B.S. degree in 1998 and
the M.S. degree in 2000 from Kyung Hee University,
Seoul, Korea.
Since 2000, he has been with the Semiconductor
R&D Center, Samsung Electronics Company, Ltd.,
Kyungki-Do, Korea, where he is an Engineer with the
Technology Development Team.
Eun-Jung Yoon received the B.S. degree in chemical
engineering from Yonsei University, Seoul, Korea, in
2001.
Since 2001, she has been with the Samsung
Electronics Company, Ltd., Kyungki-Do, Korea. Her
research interests include nano-CMOS structure and
technology, and memory devices.
Chang-Woo Oh was born in Youngyang, Kyung-
pook, Korea, on January 27, 1971. He received the
B.S. degree in electronics from Kyungpook National
University, Kyungpook, Korea, in 1996 and the M.S.
and Ph. D. degrees in electrical engineering from
Seoul National University, Seoul, Korea, in 1998
and 2002, respectively.
Since 2002, he has been a Senior Engineer with
Samsung Electronics Company, Ltd., Kyungki-Do,
Korea. His research interests include nano-CMOS
structure and technology, memory devices, and field
emission display.
Ilsub Chung was born in Jinju, Korea, in 1957. He
received the B.S. degree in electronic engineering
from SungKyunKwan University, Kyungki-Do,
Korea, in 1981, and the M.S. and Ph.D. degrees
in electrical and computer engineering from the
University of Texas at Austin in 1988 and 1992,
respectively.
In 1993, he joined the FRAM project team of
the Samsung Advanced Institute of Technology,
Giheung, Korea. In 2001, he joined SungKyunKwan
University, where he is currently an Associate
Professor in the School of Electrical and Computer Engineering, In addition,
he currently serves as a secretary of TC47/IEC. His main research area is
the characterization of nonvolatile memories such as FRAM, MRAM, and
SONOS.
Donggun Park received the B.S. and M.S. degrees
from Sogang University, Seoul, Korea, and the Ph.D.
degree from the University of California, Berkeley
(UC Berkeley), all in electrical engineering. His
Ph.D. study involved plasma charging damage and
reliability of thin gate oxides.
Since he joined Samsung Electronics Company,
Ltd., Kyungki-Do, Korea, in 1983, he has been
involved in the diffusion process development of 64
K and 256 K DRAM, and process integration of 1
Mega, 4 Mega, and 16 Mega DRAM development
until 1993. After his Ph.D. study at UC Berkeley, in 1998, he rejoined Samsung
Electronics, where he is now a Vice President of the R&D Center. After the
successful development of 0.15 m and 0.13 m 256M DRAMs, 90 nm NAND
Flash, and 100 nm high-speed 72 M SRAM, in 1999, 2001, 2002, and 2003,
respectively, he is leading the development projects of nano-CMOS transistor,
memory cell transistors, and the advanced technologies for mobile/graphic
DRAMs.
LEE et al.: NOVEL MULTIBRIDGE-CHANNEL MOSFET (MBCFET): FABRICATION TECHNOLOGIES AND CHARACTERISTICS 257

Kinam Kim (S’90–M’97–SM’01–F’03) received

the B.Sc. degree in electronic engineering in 1981
from Seoul National University, Seoul, Korea, the
M.Sc. degree in electrical engineering from the
Korea Advanced Institute of Science and Technology
(KAIST), Daejeon, Korea, in 1983, and the Ph.D.
degree in electrical engineering from the University
of California, Los Angeles, in 1994.
In 1983, he joined Samsung Electronics Com-
pany, Ltd., Kyungki-Do, Korea, where he has been
involved in the development of DRAMs, ranging
from 64 Kb to l Gb densities. Currently, he is a Vice President responsible
for the research and development of future memory technologies for DRAM,
nonvolatile memory, SRAM, and emerging new memories. His current major
activity is focused on the development of technologies for low power and high
performance multi-gigabit density DRAMs. He serves as a committee member
of the international electron device meeting (IEDM), and he is a member of the
editorial advisory board of Microelectronics Reliability.
Dr. Kim is listed in Who’s Who in the World and nominated for IBC’s 21st
Century Award for Achievement. He will be listed in The Asia 500-Leaders for
the New Century. He is a recipient of ISI’s Citation Award for a highly cited
paper.