COMPUTER ORGANIZATION AND

ARCHITECTURE
EET 2211
4TH SEM(CSE & CSIT)

ASSIGNMENT-1

1. What, in general terms, is the distinction between computer organization

and computer architecture?

2. Explain Moore’s law.

3. Consider three different processors P1,P2 and P3 executing the same

instruction set with the clock rates and CPIs given in the following table.

Processor Clock rate CPI

P1 2GHz 1.5
P2 1.5GHz 1.0
P3 3GHz 2.5

(a) Which processor has the highest performance?

(b) If the processors each execute a program in 10seconds, find the
number of cycles and number of instructions.
(c) We are trying to reduce the time by 30% but this leads to an increase
of 20% in the CPI. What clock rate should we have to get this time
reduction?

Processor Clock rate CPI Time

P1 2GHz 1.5 7s
P2 1.5GHz 1.0 10s
P3 3GHz 2.5 9s

(d) Find the IPC (instructions per cycle) for each processor.
(e) Find the clock rate for P2 that reduces its execution time to that of P1.
(f) Find the number of instructions for P2 that reduces its execution time
to that of P3.

4. Consider two different implementations of the same instruction set

architecture. There are four classes of instructions A, B, C and D. The clock
rate and CPI of each implementation are given in the following table.

Process Clock CPI Class CPI Class CPI Class CPI Class D
or rate A B C
P1 1.5GHz 1 2 3 4
 P2 2GHz 2 2 2 2

(a) Given a program with 106 instructions divided into classes as follows:
10% class A,20% class B ,20% class C and 20% class D, which
implementation is faster?
(b) What is the global CPI for each implementation?
(c) Find the clock cycles required in both cases.
The following table shows the number of instructions for a program.

Arith Store Load Branch Total

500 50 100 50 700

(d) Assuming that arith instructions take 1cycle, load and store 5 cycles
and branch 2 cycles, what is the execution time of the program in a
2GHz processor?
(e) Find the CPI for the program.
(f) If the number of load instructions can be reduced by one-half, what is
the speed-up and the CPI?

5. The table below shows the instruction type breakdown of a given

application executed on 1,2,4 and 8 processors. Using this data, you will
be exploring the speed-up of applications on parrel processors.

Process # Instructions per CPI

ors processor
Arithme Load/Sto Branc Arithme Load/Sto Branc
tic re h tic re h
a. 1 2560 1280 256 1 4 2
2 1280 640 128 1 4 2
3 640 320 64 1 4 2
4 320 160 32 1 4 2

Process # Instructions per CPI

ors processor
Arithme Load/Sto Branc Arithme Load/Sto Branc
tic re h tic re h
b. 1 2560 1280 256 1 4 2
2 1350 800 128 1 6 2
3 800 600 64 1 9 2
4 600 500 32 1 13 2

(a) The table above shows the number of instructions required per processor
to complete a program on a multiprocessor with 1,2,4 or 8 processors.
What is the total number of instructions executed across all processors?
(b) Given CPI values on the right of the table above, find the total execution
time for this program on 1,2,4 and 8 processors. Assume that each
processor has a 2GHz clock frequency.
(c) If the CPI of arithmetic instructions was doubled, what would the impact be
on the execution time of the program on 1,2,4 or 8 processors?

6. Consider a computer running programs with CPU times shown in the

following table.

FP instr. INT instr. L/S instr. Branch Total time

instr.
a 35s 85s 50s 30s 200s
b 50s 80s 50s 30s 210s

(a) By how much is the total time reduced if the time for FP operations is
reduced by 20%?
(b) By hoe much is the time for INT operations reduced if the total time is
reduced by 20%?
(c) Can be the total time can be reduced by 20% by reducing only the time for
branch instructions?

The following table shows the instruction type breakdown per processor of
a given application application executed in different numbers of
processors.

# FP instr. INT instr. L/S instr. Branch CP CPI CPI CPI

Process instr. I (IN (L/ (Branc
ors (F T) S) h)
P)
a 1 560*10 2000*10 1280*10 256*10 1 1 4 2
^6 ^6 ^6 ^6
b 8 80*10^ 240*10 160*10 32*10^ 1 1 4 2
6 ^6 ^6 6
Assume that each processor has a 2GHz clock rate.
(a) By how much must we improve the CPI of FP instructions if we want the
program to run two times faster?
(b) By how much must we improve the CPI of L/S instructions if we want the
program run two times faster?
(c) By how much is the execution time of the program improved if the CPI of
INT and FP instructions is reduced by 40% and the CPI of L/S and branch is
reduced by 30%?

7. The following table shows the execution time of five routines of a program
running on different numbers of processors.

#Processo Routine A Routine B Routine C Routine Routine E

rs (ms) (ms) (ms) D (ms)
(ms)
a. 2 20 80 10 70 5
b. 16 4 14 2 12 2
(a) Find the total execution time and by how much it is reduced if the time of
routines A,C and E is improved by 15%.
(b) By how much the time reduced if routine B is improved by 10%?
(c) By how much is the total time reduced if routine D is improved by 10%?
Execution time in a multiprocessor system can be split into computing time
for the routines plus routing time spent sending data from one processor to
another. Consider the execution time and routing time given in the following
table. In this case, the routing time is an important component of the total
time.

# Routine Routine Routine Routine Routine Routing

Processors A B C D E (ms)
(ms) (ms) (ms) (ms) (ms)
2 20 78 9 65 4 11
4 12 44 4 34 2 13
8 1 23 3 19 3 17
16 4 13 1 10 2 22
32 2 5 1 5 1 23
64 1 3 0.5 1 1 26

(d) For each doubling of the number of processors, determine the ratio of
new to old computing time and the ratio of new to old routing time.
(e) Using the geometric means of the ratios, extrapolate to find the
computing time and routing time in a 128-processor system.
(f) Find the computing time and routing time for a system with one
processor.

8. Convert the following hexadecimal numbers to their decimal equivalents:

(a) C.8 (b) A9.A

9. Convert the following hexadecimal numbers to their decimal equivalents:

(a) 5D (b) B32

10.Convert the following binary numbers to their hexadecimal equivalents:

(a) 101101.1001 (b) 1100.1101

11.Simplify the following expressions according to the commutative law:

(a) (A+B’) (B’+A) (A’+C)
(b) (A’+B’+C) (A+B’+C’) (B’+A’+C) (A+B+C’) (C’+B’+A)

12.Simplify the following expressions:

(a) A= (D’. D’E)’
(b) A= Y.(W+X+(Y’+Z’)). Z

13.Consider the graphic symbol for the S-R Flipflop. Add additional lines to
depict a D flip-flop wired from the S-R flip-flop.

14.Show the structure of a PLA with three inputs (C, B, A) and four outputs
(O0, O1, O2, O3) with the outputs defined as follows:

O0 = A’B’C+AB’+ ABC’
O1 = A’B’C+ ABC’
 O2 = C
O3 = AB’+ ABC’
15.Design a 5x32 decoder using four 3x 8 decoders (with enable inputs) and
one 2X4 decoder.

16.Consider a hypothetical 32-bit microprocessor having 32-bit instructions

composed of two fields: the first byte contains the opcode and the remainder
the immediate operand or an operand address.
a. What is the maximum directly addressable memory capacity (in bytes)?
b. Discuss the impact on the system speed if the microprocessor bus has:
1. 32-bit local address bus and a 16-bit local data bus, or
2. 16-bit local address bus and a 16-bit local data bus.
c. How many bits are needed for the program counter and the instruction
register?

17. Consider a 32-bit microprocessor whose bus cycle is the same duration as
that of a 16-bit microprocessor. Assume that, on average, 20% of the operands
and instructions are 32 bits long, 40% are 16 bits long, and 40% are only 8 bits
long. Calculate the improvement achieved when fetching instructions and
operands with the 32-bit microprocessor.

18. A set-associative cache consists of 64 lines, or slots, divided into four-line

sets. Main memory contains 4K blocks of 128 words each. Show the format of
main memory addresses.

19. For the cache design of the preceding problem, suppose that increasing
the line size from one word to four words results in a decrease of the read miss
rate from 3.2% to 1.1%. For both the nonburst transfer and the burst transfer
case, what is the average miss penalty, averaged over all reads, for the two
different line sizes?

20. WAP to perform the following operation on bytes data given in the
memory location 4000h, and 4002h and store the results of the given operation
[{(data1 + 5)and(data2 − 5)}or(data1 ∗ 2)']
in the memory location 4004h.