1 2 3 4 5

A A

Compal Confidential
ZI VY2/ ZI VY3 M/ B Schemat i cs Document
I nt el Shar k Bay + N15P- GX
B B

( Cr escent Bay + N15P- GX)

C
LA- B111P C

2013- 10- 30 B
REV:0.2

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Sheet
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 1 of 59
1 2 3 4 5
 1 2 3 4 5

Compal Confidential
Shark Bay/Crescent Bay
nVidia Intel
PEG 16X DDR3-SO-DIMM X 2
A
N15P-GX Processor DDR3L 1600MHz 1.35V BANK 0, 1, 2, 3
A

VRAM GDDR5 2G/4G +1.35V, +0.675VS

Page 35~44 Dual Channel Page 11, 12

Haswell H
Broadwell H
LCD conn eDP
Page 22
BGA
37.5mmX32mm

HDMI HDMI, DDC Page 4~10

Page 23
+CPU_CORE, +1.35V_CPU_VDDQ

port 8

DMI x4 Touch Panel

Page 22
5GB/s

port 10

BT (NGFF)
B Page 27 B
USB2.0

PCI-e Intel port 4

USB conn x1
(WLAN) Lynx-Point Right USB Board Page 33
port 2 port 5 port 3
PCH
NGFF Card Reader LAN port 0,1
2230 Conn. Realtek GbE port 1,2
USB conn x2
Realtek RTS5249
WLAN/BT USB3.0 Left USB Board Page 29
Page 27 Page 33
RTL8111GUL
Page 24 port 3
USB Board 3D Camera
Reserve Page 60
USB 2.0(BT)
port 9
Camera
FCBGA 695 Balls DMIC
HM86 Digital Array MIC Page 22

SPI ROM SPI 20mmX20mm

8MB
C Page 16 C

S/PDIF
Page 33

Azalia Audio Codec

Realtek ALC283 Page 25 Combo Jack
Page 33
Page 13 ~ 21
port 4 SATA +1.05VS, +1.5VS, +3VS,
2.5" SATA HDD/SDD GEN3 +3V_PCH, +RTCVCC
Speaker Connector
Page 28
Page 25

LPC BUS Subwoofer AMP. Subwoofer

APA2619RI-TR Page 26 Page 26

Fan Control Touch Pad CONN. ENE KB9022 Int. KBD

Page 31 Page 31
Page 33 +3VLP
DC/DC Interface CKT.
Thermal Sensor page 30 LID switch Page 34
D
ZZZ1 SMSC 1403-2 Page 31 Page 32
D

PCB-MB

www.vinafix.com
PCB P/N for Load BOM
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagram
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 2 of 59
1 2 3 4 5
 1

Voltage Rails ( O MEANS ON X MEANS OFF ) BOM Structure Table

USB Port Table BTO Item BOM Structure
B+ +5VALW +3V_PCH +1.35V +5VS
45 LEVEL 45@
5 External
USB 2.0 Port USB 3.0 Port Connector CONN@
+3VALW +3VS USB Port
+12VS_PANEL +1.5VS
For ZIVY2 (15") 15@
power
0 XHCI 1 Left USB3.0
+1.05VS
UHCI0 For ZIVY3 (17") 17@
plane 1 XHCI 2 Left USB3.0
+VCC_CORE
LAN LDO Mode LDO@
2
+0.675VS
UHCI1 LAN Switch mode SWR@
3
+12VS
EHCI1 10/100 LAN(RTL8106) 8106@
4 Right USB2.0
UHCI2 1000 LAN(RTL8111G) 8111@
5
Green clock(DIS sku) GCLKDIS@
6
State
UHCI3 Green clock(UMA sku) GCLKUMA@
7
Green clk support GCLK@
8 Touch screen
UHCI4 NOGCLK@
9 Camera No Green clk support
NOGCLKDIS@
10 WLAN
S0
EHCI2 UHCI5 Nvidia GC6 state SW@/NOSW@
O O O O O 11
UMA SKU UMA@
12
S3
UHCI6 Unpop @
O O O O X 13
Deep S3 DS3@
DeepS3
NO Deep S3 NODS3@
O O X O X EMI Pop EMI@
Board ID Table for AD channel
S5 S4/AC
EMI unpop @EMI@
O O X X X Vcc 3.3V
ESD Pop ESD@
Ra / Rc 100K +/- 1%
S5 S4/ Battery only Board ID ESD unpop @ESD@
O X X X X Rb / Rd V AD_BID min V AD_BID typ V AD_BID max
Haswell HW@
0 0 0 V 0 V 0 V
S5 S4/AC & Battery
Broadwell BW@
don't exist X X X X X 1 12K +/- 1% 0.347 V 0.354 V 0.360 V
Subwoofer WF@
2 15K +/- 1% 0.423 V 0.430 V 0.438 V
Camera CCD3@
3 20K +/- 1% 0.541 V 0.550 V 0.559 V
4 27K +/- 1% 0.691 V 0.702 V 0.713 V
5 33K +/- 1% 0.807 V 0.819 V 0.831 V
A 6 43K +/- 1% 0.978 V 0.992 V 1.006 V A

EC SM Bus1 address EC SM Bus2 address Symbol Note :

Device Address Device Address
Smart Battery Thermal Sensor EMC1403-2-AIZL-TR 1001_101xb
Charger 0b 0001 0010 (0x12H) PCH SML1 Bus address
: means Digital Ground : means Analog Ground
Install below 43 level BOM structure for ver. 0.1
nVidia N15P-GX 0x9E

PCH SM Bus address PCH SML0 Bus address CPU part

Device Address Device Address CPU1@ CPU3@ CPU4@ CPU5@
I7-4712HQ
DDR DIMM0 1010 000x A0h
I7-4710HQ U1 R1 U1 R1 U1 R1 U1 R1
DDR DIMM1 1010 010x A4h I7-4760HQ
Click Pad I5-4200H
I5_4200H 2.8G I7_4750HQ 2G I7_4702HQ 2.2G I7_4700HQ 2.4G
SA000071N00 SA00007A900 SA00006TQ00 SA00006TP00

4319S138L03 V2G 4319S138L04 V4G 4319S138L05 V4G

SMBUS Control Table

Touch Thermal
SOURCE BATT KB9022 SODIMM Pad sensor VGA

SMB_EC_CK1
SMB_EC_DA1
KB9022
+3VLP_EC V X X X X X
SMBCLK
SMBDATA
PCH
+3V_PCH X X V
+3VS
V+3VS
X X
SML0CLK
SML0DATA
PCH
+3V_PCH
X X X X X X
Security Classification Compal Secret Data Compal Electronics, Inc.
SML1CLK
SML1DATA
PCH
+3V_PCH
X V
+3VS
X X V
+3VS
V
+3VS_DGPU
Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title
Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 3 of 59
1
 5 4 3 2 1

+VCOMP_OUT

PEG_RCOMP 2 1
24.9_0402_1% R1

D D
Note:
Trace width=12 mils ,Spacing=15mils
Max length= 400 mils.

U1A @
HASWELL_BGA_E

AH6 PEG_RCOMP
PEG_RCOMP PEG_CRX_GTX_N[0..15] (36)
E10 PEG_CRX_GTX_N15
DMI_CRX_PTX_N0 AB2 PEG_RXN0 C10 PEG_CRX_GTX_N14
(14) DMI_CRX_PTX_N0 DMI_RXN0 PEG_RXN1
(14) DMI_CRX_PTX_N1 DMI_CRX_PTX_N1 AB3 B10 PEG_CRX_GTX_N13
DMI_CRX_PTX_N2 AC3 DMI_RXN1 PEG_RXN2 E9 PEG_CRX_GTX_N12
(14) DMI_CRX_PTX_N2 DMI_RXN2 PEG_RXN3
(14) DMI_CRX_PTX_N3 DMI_CRX_PTX_N3 AC1 D9 PEG_CRX_GTX_N11
DMI_RXN3 PEG_RXN4 B9 PEG_CRX_GTX_N10
DMI_CRX_PTX_P0 AB1 PEG_RXN5 L5 PEG_CRX_GTX_N9
(14) DMI_CRX_PTX_P0 DMI_RXP0 PEG_RXN6
(14) DMI_CRX_PTX_P1 DMI_CRX_PTX_P1 AB4 L2 PEG_CRX_GTX_N8
DMI_CRX_PTX_P2 AC4 DMI_RXP1 PEG_RXN7 M4 PEG_CRX_GTX_N7
(14) DMI_CRX_PTX_P2 DMI_RXP2 PEG_RXN8
DMI_CRX_PTX_P3 AC2 L4 PEG_CRX_GTX_N6

DMI
(14) DMI_CRX_PTX_P3 DMI_RXP3 PEG_RXN9 M2 PEG_CRX_GTX_N5
DMI_CTX_PRX_N0 AF2 PEG_RXN10 V5 PEG_CRX_GTX_N4
(14) DMI_CTX_PRX_N0 DMI_TXN0 PEG_RXN11
DMI_CTX_PRX_N1 AF4 V4 PEG_CRX_GTX_N3
(14) DMI_CTX_PRX_N1 DMI_TXN1 PEG_RXN12
DMI_CTX_PRX_N2 AG4 V1 PEG_CRX_GTX_N2
(14) DMI_CTX_PRX_N2 DMI_TXN2 PEG_RXN13
DMI_CTX_PRX_N3 AG2 Y3 PEG_CRX_GTX_N1
(14) DMI_CTX_PRX_N3 DMI_TXN3 PEG_RXN14 Y2 PEG_CRX_GTX_N0
PEG_RXN15 PEG_CRX_GTX_P[0..15] (36)
DMI_CTX_PRX_P0 AF1 F10 PEG_CRX_GTX_P15
(14) DMI_CTX_PRX_P0 DMI_TXP0 PEG_RXP0
DMI_CTX_PRX_P1 AF3 D10 PEG_CRX_GTX_P14
(14) DMI_CTX_PRX_P1 DMI_TXP1 PEG_RXP1
DMI_CTX_PRX_P2 AG3 A10 PEG_CRX_GTX_P13
(14) DMI_CTX_PRX_P2 DMI_TXP2 PEG_RXP2
DMI_CTX_PRX_P3 AG1 F9 PEG_CRX_GTX_P12
(14) DMI_CTX_PRX_P3 DMI_TXP3 PEG_RXP3 C9 PEG_CRX_GTX_P11
C PEG_RXP4 A9 PEG_CRX_GTX_P10 C
PEG_RXP5 M5 PEG_CRX_GTX_P9
PEG_RXP6 L1 PEG_CRX_GTX_P8
PEG_RXP7 M3 PEG_CRX_GTX_P7
FDI_CSYMC F11 PEG_RXP8 L3 PEG_CRX_GTX_P6
(14) FDI_CSYMC FDI_CSYNC PEG_RXP9
FDI_INT F12 M1 PEG_CRX_GTX_P5
(14) FDI_INT DISP_INT PEG_RXP10 Y5 PEG_CRX_GTX_P4

PEG
PEG_RXP11 V3 PEG_CRX_GTX_P3
PEG_RXP12 V2 PEG_CRX_GTX_P2
PEG_RXP13 Y4 PEG_CRX_GTX_P1
PEG_RXP14 Y1 PEG_CRX_GTX_P0
PEG_RXP15 PEG_PTX_C_DRX_N[0..15] (36)
B6 PEG_PTX_DRX_N15 0.22U_0402_10V6K 2 1DIS@ C1 PEG_PTX_C_DRX_N15
PEG_TXN0 C5 PEG_PTX_DRX_N14 0.22U_0402_10V6K 2 1DIS@ C2 PEG_PTX_C_DRX_N14
FDI PEG_TXN1 DGPU
E6 PEG_PTX_DRX_N13 0.22U_0402_10V6K 2 1DIS@ C3 PEG_PTX_C_DRX_N13
PEG_TXN2 D4 PEG_PTX_DRX_N12 0.22U_0402_10V6K 2 1DIS@ C4 PEG_PTX_C_DRX_N12
PEG_TXN3 G4 PEG_PTX_DRX_N11 0.22U_0402_10V6K 2 1DIS@ C5 PEG_PTX_C_DRX_N11
PEG_TXN4 E3 PEG_PTX_DRX_N10 0.22U_0402_10V6K 2 1DIS@ C6 PEG_PTX_C_DRX_N10
PEG_TXN5 J5 PEG_PTX_DRX_N9 0.22U_0402_10V6K 2 1DIS@ C7 PEG_PTX_C_DRX_N9
PEG_TXN6 G3 PEG_PTX_DRX_N8 0.22U_0402_10V6K 2 1DIS@ C8 PEG_PTX_C_DRX_N8
PEG_TXN7 J3 PEG_PTX_DRX_N7 0.22U_0402_10V6K 2 1DIS@ C9 PEG_PTX_C_DRX_N7
PEG_TXN8 J2 PEG_PTX_DRX_N6 0.22U_0402_10V6K 2 1DIS@ C10 PEG_PTX_C_DRX_N6
PEG_TXN9 T6 PEG_PTX_DRX_N5 0.22U_0402_10V6K 2 1DIS@ C11 PEG_PTX_C_DRX_N5
PEG_TXN10 R6 PEG_PTX_DRX_N4 0.22U_0402_10V6K 2 1DIS@ C12 PEG_PTX_C_DRX_N4
PEG_TXN11 R2 PEG_PTX_DRX_N3 0.22U_0402_10V6K 2 1DIS@ C13 PEG_PTX_C_DRX_N3
PEG_TXN12 R4 PEG_PTX_DRX_N2 0.22U_0402_10V6K 2 1DIS@ C14 PEG_PTX_C_DRX_N2
PEG_TXN13 T4 PEG_PTX_DRX_N1 0.22U_0402_10V6K 2 1DIS@ C15 PEG_PTX_C_DRX_N1
PEG_TXN14 T1 PEG_PTX_DRX_N0 0.22U_0402_10V6K 2 1DIS@ C16 PEG_PTX_C_DRX_N0
PEG_TXN15 PEG_PTX_C_DRX_P[0..15] (36)
C6 PEG_PTX_DRX_P15 0.22U_0402_10V6K 2 1DIS@ C17 PEG_PTX_C_DRX_P15
PEG_TXP0 B5 PEG_PTX_DRX_P14 0.22U_0402_10V6K 2 1DIS@ C18 PEG_PTX_C_DRX_P14
PEG_TXP1 D6 PEG_PTX_DRX_P13 0.22U_0402_10V6K 2 1DIS@ C19 PEG_PTX_C_DRX_P13
PEG_TXP2 E4 PEG_PTX_DRX_P12 0.22U_0402_10V6K 2 1DIS@ C20 PEG_PTX_C_DRX_P12
PEG_TXP3 G5 PEG_PTX_DRX_P11 0.22U_0402_10V6K 2 1DIS@ C21 PEG_PTX_C_DRX_P11
B PEG_TXP4 E2 PEG_PTX_DRX_P10 0.22U_0402_10V6K 2 1DIS@ C22 PEG_PTX_C_DRX_P10 B
PEG_TXP5 J6 PEG_PTX_DRX_P9 0.22U_0402_10V6K 2 1DIS@ C23 PEG_PTX_C_DRX_P9
PEG_TXP6 G2 PEG_PTX_DRX_P8 0.22U_0402_10V6K 2 1DIS@ C24 PEG_PTX_C_DRX_P8
PEG_TXP7 J4 PEG_PTX_DRX_P7 0.22U_0402_10V6K 2 1DIS@ C25 PEG_PTX_C_DRX_P7
PEG_TXP8 J1 PEG_PTX_DRX_P6 0.22U_0402_10V6K 2 1DIS@ C26 PEG_PTX_C_DRX_P6
PEG_TXP9 T5 PEG_PTX_DRX_P5 0.22U_0402_10V6K 2 1DIS@ C27 PEG_PTX_C_DRX_P5
PEG_TXP10 R5 PEG_PTX_DRX_P4 0.22U_0402_10V6K 2 1DIS@ C28 PEG_PTX_C_DRX_P4
PEG_TXP11 R1 PEG_PTX_DRX_P3 0.22U_0402_10V6K 2 1DIS@ C29 PEG_PTX_C_DRX_P3
PEG_TXP12 R3 PEG_PTX_DRX_P2 0.22U_0402_10V6K 2 1DIS@ C30 PEG_PTX_C_DRX_P2
PEG_TXP13 T3 PEG_PTX_DRX_P1 0.22U_0402_10V6K 2 1DIS@ C31 PEG_PTX_C_DRX_P1
PEG_TXP14 T2 PEG_PTX_DRX_P0 0.22U_0402_10V6K 2 1DIS@ C32 PEG_PTX_C_DRX_P0
PEG_TXP15

1 OF 12
HSW-QUAD-CORE-GT2_BGA1364

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(1/7) DMI,FDI,PEG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 4 of 59
5 4 3 2 1
 5 4 3 2 1

+VCCIO_OUT
Follow Intel schematic
review‐0930 +1.35V

Note:

2
U1B @ HASWELL_BGA_E
R3 PECI/THERMTRIP: MISC R174
62_0402_5% C51 BB51 SM_RCOMP0 470_0402_5%
Trace width=4 mils ,Spacing=18mil PROC_DETECT SM_RCOMP0 BB53 SM_RCOMP1

DDR3
SM_RCOMP1
Zo=50 ohm T1 H_CATERR# G50 BB52 SM_RCOMP2

THERMAL
CATERR SM_RCOMP2

1
G51 BE51 H_DRAMRST# 1 R2 2
D (31) H_PECI PECI SM_DRAMRST DDR3_DRAMRST# (11,12) D
0_0402_5% 1 0.1U_0402_16V7K
(31) H_PROCHOT# H_PROCHOT# R4 1 2 H_PROCHOT#_R E50 N53 XDP_PRDY#
PROCHOT PRDY T3 C33
56_0402_5% D53 N52 XDP_PREQ# 1 @ESD@
(18,45) H_THRMTRIP# THERMTRIP PREQ T2
N54 XDP_TCLK @ESD@
TCK M51 XDP_TMS C187 2
TMS M53 XDP_TRST#

JTAG
TRST 100P_0402_50V8J
H_PM_SYNC D52 N49 XDP_TDI 2
(14) H_PM_SYNC PM_SYNC TDI
H_CPUPWRGD F50 M49 XDP_TDO

PWR
(18) H_CPUPWRGD PWRGOOD TDO
PM_SYS_PWRGD_BUF AP48 F53 XDP_DBRESET# ESD 9/5
CPU_PLTRST# L54 SM_DRAMPWROK DBR
1 (18) CPU_PLTRST# PLTRSTIN Place near SODIMM side,

2
R51 XDP_BPM#0
BPM#0 T4
R5 C188 R50 XDP_BPM#1
BPM#1 T5
100P_0402_50V8J (15) CLK_CPU_DPLL# CLK_CPU_DPLL# AC6 P49 XDP_BPM#2
2 @ESD@ DPLL_REF_CLKN BPM#2 T6
10K_0402_5% (15) CLK_CPU_DPLL CLK_CPU_DPLL AE6 N50 XDP_BPM#3
DPLL_REF_CLKP BPM#3 T7
CLK_CPU_SSC_DPLL# V6 R49 XDP_BPM#4

CLOCK
(15) CLK_CPU_SSC_DPLL# SSC_DPLL_REF_CLKN BPM#4 T8

1
(15) CLK_CPU_SSC_DPLL CLK_CPU_SSC_DPLL Y6 P53 XDP_BPM#5
SSC_DPLL_REF_CLKP BPM#5 T9
(15) CLK_CPU_DMI# CLK_CPU_DMI# AB6 U51 XDP_BPM#6
ESD 9/5 BCLKN BPM#6 T10
(15) CLK_CPU_DMI CLK_CPU_DMI AA6 P51 XDP_BPM#7
BCLKP BPM#7 T11

2 OF 12
HSW-QUAD-CORE-GT2_BGA1364

C HASWELL_BGA_E C
U1L @

DC_TEST_B3_A3 A3
A4 DAISY_CHAIN_NCTF_A3
DAISY_CHAIN_NCTF_A4
BF51
DAISY_CHAIN_NCTF_BF51 BF52 DC_TEST_BE52_BF52
A51 DAISY_CHAIN_NCTF_BF52 BF53 DC_TEST_BE53_BF53
DC_TEST_A52_B52 A52 DAISY_CHAIN_NCTF_A51 DAISY_CHAIN_NCTF_BF53
DC_TEST_A53_B53 A53 DAISY_CHAIN_NCTF_A52 C1 DC_TEST_C1_C2
DAISY_CHAIN_NCTF_A53 DAISY_CHAIN_NCTF_C1 C2 DC_TEST_C1_C2
DAISY_CHAIN_NCTF_C2 C3 DC_TEST_C3_B2
DC_TEST_C3_B2 B2 DAISY_CHAIN_NCTF_C3
DC_TEST_B3_A3 B3 DAISY_CHAIN_NCTF_B2 C54 DC_TEST_B54_C54
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_C54 D1
DC_TEST_A52_B52 B52 DAISY_CHAIN_NCTF_D1
DC_TEST_A53_B53 B53 DAISY_CHAIN_NCTF_B52 D54
DC_TEST_B54_C54 B54 DAISY_CHAIN_NCTF_B53 DAISY_CHAIN_NCTF_D54
DAISY_CHAIN_NCTF_B54

BC1
BC54 DAISY_CHAIN_NCTF_BC1
DC_TEST_BE1_BD1 BD1 DAISY_CHAIN_NCTF_BC54
DAISY_CHAIN_NCTF_BD1 DDR3 COMPENSATION SIGNALS
DC_TEST_BE54_BD54 BD54
DC_TEST_BE1_BD1 BE1 DAISY_CHAIN_NCTF_BD54 AN35 SM_RCOMP0 R6 1 2 100_0402_1%
DC_TEST_BE2_BF2 BE2 DAISY_CHAIN_NCTF_BE1 RSVD AN37
B DC_TEST_BE3_BF3 BE3 DAISY_CHAIN_NCTF_BE2 RSVD AF9 SM_RCOMP1 R8 1 2 75_0402_1% B
SM_DRAMPWROK with DDR Power Gating Topology DC_TEST_BE52_BF52 BE52 DAISY_CHAIN_NCTF_BE3
DAISY_CHAIN_NCTF_BE52
RSVD
RSVD
AE9
DC_TEST_BE53_BF53 BE53 G14 SM_RCOMP2 R9 1 2 100_0402_1%
DC_TEST_BE54_BD54 BE54 DAISY_CHAIN_NCTF_BE53 RSVD G17
DC_TEST_BE2_BF2 BF2 DAISY_CHAIN_NCTF_BE54 RSVD AD45
+3V_PCH +3V_PCH DC_TEST_BE3_BF3 BF3 DAISY_CHAIN_NCTF_BF2 RSVD AG45
BF4 DAISY_CHAIN_NCTF_BF3 RSVD Note:
DAISY_CHAIN_NCTF_BF4 Trace width=12~15 mil, Spcing=20 mils
@ +1.35V_CPU_VDDQ Max trace length= 500 mils
1
C192
1

0.1U_0402_16V7K
1

DS3@ DS3@
R153 R152 2 R7
100K_0402_5% 100K_0402_5% 1.8K_0402_1% 12 OF 12
U6 HSW-QUAD-CORE-GT2_BGA1364 PU/PD for JTAG signals
2

DS3@
2

(14,31) SYS_PWROK 1
P

B 4 PM_SYS_PWRGD_BUF +3VS
2 O
(14) PM_DRAM_PWRGD A
G

XDP_DBRESET# R11 2 1 1K_0402_5%

1

1 74AHC1G09GW_TSSOP5
3

DS3@ R10 +1.05VS

C191 3.3K_0402_1%
0.01U_0402_16V7K XDP_TMS R12 2 @ 1 51_0402_5%
2 XDP_TDI R13 2 @ 1 51_0402_5%
2

OK RP1
R70 1 2 0_0402_5% XDP_TDO 1 8
XDP_TCLK 2 7
NODS3@ XDP_TRST# 3 6
4 5

A 51_0804_8P4R_5% A

TMS/TDI no require pull high on Check list

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(2/7) PM,XDP,CLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 5 of 59
5 4 3 2 1
 5 4 3 2 1

D HASWELL_BGA_E D
U1C @ @
HASWELL_BGA_E
U1D
(11) DDR_A_D[0..63] (12) DDR_B_D[0..63]
DDR_A_D0 AH54 BD31
DDR_A_D1 AH52 SA_DQ0 RSVD BE25 M_CLK_DDR#0 DDR_B_D0 AC54 AY36
SA_DQ1 SA_CKN0 M_CLK_DDR#0 (11) SB_DQ0 RSVD
DDR_A_D2 AK51 BF25 M_CLK_DDR0 DDR_B_D1 AC52 AW27 M_CLK_DDR#2
SA_DQ2 SA_CK0 M_CLK_DDR0 (11) SB_DQ1 SB_CKN0 M_CLK_DDR#2 (12)
DDR_A_D3 AK54 BE34 DDR_CKE0_DIMMA DDR_B_D2 AE51 AV27 M_CLK_DDR2
SA_DQ3 SA_CKE0 DDR_CKE0_DIMMA (11) SB_DQ2 SB_CK0 M_CLK_DDR2 (12)
DDR_A_D4 AH53 BD25 M_CLK_DDR#1 DDR_B_D3 AE54 AU36 DDR_CKE2_DIMMB
SA_DQ4 SA_CKN1 M_CLK_DDR#1 (11) SB_DQ3 SB_CKE0 DDR_CKE2_DIMMB (12)
DDR_A_D5 AH51 BC25 M_CLK_DDR1 DDR_B_D4 AC53 AW26 M_CLK_DDR#3
SA_DQ5 SA_CK1 M_CLK_DDR1 (11) SB_DQ4 SB_CKN1 M_CLK_DDR#3 (12)
DDR_A_D6 AK52 BF34 DDR_CKE1_DIMMA DDR_B_D5 AC51 AV26 M_CLK_DDR3
SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA (11) SB_DQ5 SB_CK1 M_CLK_DDR3 (12)
DDR_A_D7 AK53 BE23 DDR_B_D6 AE52 AU35 DDR_CKE3_DIMMB
SA_DQ7 SA_CKN2 SB_DQ6 SB_CKE1 DDR_CKE3_DIMMB (12)
DDR_A_D8 AN54 BF23 DDR_B_D7 AE53 BA26
DDR_A_D9 AN52 SA_DQ8 SA_CK2 BC34 DDR_B_D8 AU47 SB_DQ7 SB_CKN2 AY26
DDR_A_D10 AR51 SA_DQ9 SA_CKE2 BD23 DDR_B_D9 AU49 SB_DQ8 SB_CK2 AV35
DDR_A_D11 AR53 SA_DQ10 SA_CKN3 BC23 DDR_B_D10 AV43 SB_DQ9 SB_CKE2 BA27
DDR_A_D12 AN53 SA_DQ11 SA_CK3 BD34 DDR_B_D11 AV45 SB_DQ10 SB_CKN3 AY27
DDR_A_D13 AN51 SA_DQ12 SA_CKE3 DDR_B_D12 AU43 SB_DQ11 SB_CK3 AV36
DDR_A_D14 AR52 SA_DQ13 BE16 DDR_CS0_DIMMA# DDR_B_D13 AU45 SB_DQ12 SB_CKE3
SA_DQ14 SA_CS#0 DDR_CS0_DIMMA# (11) SB_DQ13
DDR_A_D15 AR54 BC17 DDR_CS1_DIMMA# DDR_B_D14 AV47 BA20 DDR_CS2_DIMMB#
SA_DQ15 SA_CS#1 DDR_CS1_DIMMA# (11) SB_DQ14 SB_CS#0 DDR_CS2_DIMMB# (12)
DDR_A_D16 AV52 BE17 DDR_B_D15 AV49 AY19 DDR_CS3_DIMMB#
SA_DQ16 SA_CS#2 SB_DQ15 SB_CS#1 DDR_CS3_DIMMB# (12)
DDR_A_D17 AV53 BD16 DDR_B_D16 BC49 AU19
DDR_A_D18 AY52 SA_DQ17 SA_CS#3 BC16 M_ODT0 DDR_B_D17 BE49 SB_DQ16 SB_CS#2 AW20
SA_DQ18 SA_ODT0 M_ODT0 (11) SB_DQ17 SB_CS#3
DDR_A_D19 AY51 BF16 M_ODT1 DDR_B_D18 BD47
SA_DQ19 SA_ODT1 M_ODT1 (11) SB_DQ18
DDR_A_D20 AV51 BF17 DDR_B_D19 BC47 AY20 M_ODT2
SA_DQ20 SA_ODT2 SB_DQ19 SB_ODT0 M_ODT2 (12)
DDR_A_D21 AV54 BD17 DDR_B_D20 BD49 BA19 M_ODT3
SA_DQ21 SA_ODT3 SB_DQ20 SB_ODT1 M_ODT3 (12)
DDR_A_D22 AY54 BC20 DDR_A_BS0 DDR_B_D21 BD50 AV19
SA_DQ22 SA_BS0 DDR_A_BS0 (11) SB_DQ21 SB_ODT2
DDR_A_D23 AY53 BD21 DDR_A_BS1 DDR_B_D22 BE47 AW19
SA_DQ23 SA_BS1 DDR_A_BS1 (11) SB_DQ22 SB_ODT3
DDR_A_D24 AY47 BD32 DDR_A_BS2 DDR_B_D23 BF47 AY23 DDR_B_BS0
SA_DQ24 SA_BS2 DDR_A_BS2 (11) SB_DQ23 SB_BS0 DDR_B_BS0 (12)
DDR_A_D25 AY49 DDR_B_D24 BE44 BA23 DDR_B_BS1
SA_DQ25 SB_DQ24 SB_BS1 DDR_B_BS1 (12)
DDR_A_D26 BA47 BC21 DDR_B_D25 BD44 BA36 DDR_B_BS2
SA_DQ26 VSS SB_DQ25 SB_BS2 DDR_B_BS2 (12)
DDR_A_D27 BA45 BF20 DDR_A_RAS# DDR_B_D26 BC42 AU30
SA_DQ27 SA_RAS DDR_A_RAS# (11) SB_DQ26 VSS
DDR_A_D28 AY45 BF21 DDR_A_WE# DDR_B_D27 BF42 AV23 DDR_B_RAS#
SA_DQ28 SA_WE DDR_A_WE# (11) SB_DQ27 SB_RAS DDR_B_RAS# (12)
DDR_A_D29 AY43 BE21 DDR_A_CAS# DDR_B_D28 BF44 AW23 DDR_B_WE#
SA_DQ29 SA_CAS DDR_A_CAS# (11) SB_DQ28 SB_WE DDR_B_WE# (12)
C DDR_A_D30 BA49 DDR_B_D29 BC44 AV20 DDR_B_CAS# C
SA_DQ30 DDR_A_MA[0..15] (11) SB_DQ29 SB_CAS DDR_B_CAS# (12)
DDR_A_D31 BA43 BD28 DDR_A_MA0 DDR_B_D30 BD42
SA_DQ31 SA_MA0 SB_DQ30 DDR_B_MA[0..15] (12)
DDR_A_D32 BF14 BD27 DDR_A_MA1 DDR_B_D31 BE42 BA30 DDR_B_MA0
DDR_A_D33 BC14 SA_DQ32 SA_MA1 BF28 DDR_A_MA2 DDR_B_D32 BA16 SB_DQ31 SB_MA0 AW30 DDR_B_MA1
DDR_A_D34 BC11 SA_DQ33 SA_MA2 BE28 DDR_A_MA3 DDR_B_D33 AU16 SB_DQ32 SB_MA1 AY30 DDR_B_MA2
DDR_A_D35 BF11 SA_DQ34 SA_MA3 BF32 DDR_A_MA4 DDR_B_D34 BA15 SB_DQ33 SB_MA2 AV30 DDR_B_MA3
DDR_A_D36 BE14 SA_DQ35 SA_MA4 BC27 DDR_A_MA5 DDR_B_D35 AV15 SB_DQ34 SB_MA3 AW32 DDR_B_MA4
DDR_A_D37 BD14 SA_DQ36 SA_MA5 BF27 DDR_A_MA6 DDR_B_D36 AY16 SB_DQ35 SB_MA4 AY32 DDR_B_MA5
DDR_A_D38 BD11 SA_DQ37 SA_MA6 BC28 DDR_A_MA7 DDR_B_D37 AV16 SB_DQ36 SB_MA5 AT30 DDR_B_MA6
DDR_A_D39 BE11 SA_DQ38 SA_MA7 BE27 DDR_A_MA8 DDR_B_D38 AY15 SB_DQ37 SB_MA6 AV32 DDR_B_MA7
DDR_A_D40 BC9 SA_DQ39 SA_MA8 BC32 DDR_A_MA9 DDR_B_D39 AU15 SB_DQ38 SB_MA7 BA32 DDR_B_MA8
DDR_A_D41 BE9 SA_DQ40 SA_MA9 BD20 DDR_A_MA10 DDR_B_D40 AU12 SB_DQ39 SB_MA8 AU32 DDR_B_MA9
DDR_A_D42 BE6 SA_DQ41 SA_MA10 BF31 DDR_A_MA11 DDR_B_D41 AY12 SB_DQ40 SB_MA9 AU23 DDR_B_MA10
DDR_A_D43 BC6 SA_DQ42 SA_MA11 BC31 DDR_A_MA12 DDR_B_D42 BA10 SB_DQ41 SB_MA10 AY35 DDR_B_MA11
DDR_A_D44 BD9 SA_DQ43 SA_MA12 BE20 DDR_A_MA13 DDR_B_D43 AU10 SB_DQ42 SB_MA11 AW35 DDR_B_MA12
DDR_A_D45 BF9 SA_DQ44 SA_MA13 BE32 DDR_A_MA14 DDR_B_D44 AV12 SB_DQ43 SB_MA12 AU20 DDR_B_MA13
DDR_A_D46 BE5 SA_DQ45 SA_MA14 BE31 DDR_A_MA15 DDR_B_D45 BA12 SB_DQ44 SB_MA13 AW36 DDR_B_MA14
DDR_A_D47 BD6 SA_DQ46 SA_MA15 DDR_B_D46 AY10 SB_DQ45 SB_MA14 BA35 DDR_B_MA15
SA_DQ47 DDR_A_DQS#[0..7] (11) SB_DQ46 SB_MA15
DDR_A_D48 BB4 AJ52 DDR_A_DQS#0 DDR_B_D47 AV10
SA_DQ48 SA_DQSN0 SB_DQ47 DDR_B_DQS#[0..7] (12)
DDR_A_D49 BC2 AP53 DDR_A_DQS#1 DDR_B_D48 AU8 AD52 DDR_B_DQS#0
DDR_A_D50 AW3 SA_DQ49 SA_DQSN1 AW52 DDR_A_DQS#2 DDR_B_D49 BA8 SB_DQ48 SB_DQSN0 AU46 DDR_B_DQS#1
DDR_A_D51 AW2 SA_DQ50 SA_DQSN2 AY46 DDR_A_DQS#3 DDR_B_D50 AV6 SB_DQ49 SB_DQSN1 BD48 DDR_B_DQS#2
DDR_A_D52 BB3 SA_DQ51 SA_DQSN3 BD12 DDR_A_DQS#4 DDR_B_D51 BA6 SB_DQ50 SB_DQSN2 BD43 DDR_B_DQS#3
DDR_A_D53 BB2 SA_DQ52 SA_DQSN4 BE7 DDR_A_DQS#5 DDR_B_D52 AV8 SB_DQ51 SB_DQSN3 AW16 DDR_B_DQS#4
DDR_A_D54 AW4 SA_DQ53 SA_DQSN5 BA3 DDR_A_DQS#6 DDR_B_D53 AY8 SB_DQ52 SB_DQSN4 AW10 DDR_B_DQS#5
DDR_A_D55 AW1 SA_DQ54 SA_DQSN6 AT2 DDR_A_DQS#7 DDR_B_D54 AU6 SB_DQ53 SB_DQSN5 AW8 DDR_B_DQS#6
DDR_A_D56 AU3 SA_DQ55 SA_DQSN7 AW39 DDR_B_D55 AY6 SB_DQ54 SB_DQSN6 AL2 DDR_B_DQS#7
SA_DQ56 RSVD DDR_A_DQS[0..7] (11) SB_DQ55 SB_DQSN7
DDR_A_D57 AU1 AJ53 DDR_A_DQS0 DDR_B_D56 AM2 BE38
SA_DQ57 SA_DQS0 SB_DQ56 RSVD DDR_B_DQS[0..7] (12)
DDR_A_D58 AR1 AP52 DDR_A_DQS1 DDR_B_D57 AM3 AD53 DDR_B_DQS0
DDR_A_D59 AR4 SA_DQ58 SA_DQS1 AW53 DDR_A_DQS2 DDR_B_D58 AK1 SB_DQ57 SB_DQS0 AV46 DDR_B_DQS1
DDR_A_D60 AU2 SA_DQ59 SA_DQS2 BA46 DDR_A_DQS3 DDR_B_D59 AK4 SB_DQ58 SB_DQS1 BE48 DDR_B_DQS2
DDR_A_D61 AU4 SA_DQ60 SA_DQS3 BE12 DDR_A_DQS4 DDR_B_D60 AM1 SB_DQ59 SB_DQS2 BE43 DDR_B_DQS3
B DDR_A_D62 AR2 SA_DQ61 SA_DQS4 BD7 DDR_A_DQS5 DDR_B_D61 AM4 SB_DQ60 SB_DQS3 AW15 DDR_B_DQS4 B
DDR_A_D63 AR3 SA_DQ62 SA_DQS5 BA2 DDR_A_DQS6 DDR_B_D62 AK2 SB_DQ61 SB_DQS4 AW12 DDR_B_DQS5
SA_DQ63 SA_DQS6 AT3 DDR_A_DQS7 DDR_B_D63 AK3 SB_DQ62 SB_DQS5 AW6 DDR_B_DQS6
+SM_VREF AM6 SA_DQS7 AW40 SB_DQ63 SB_DQS6 AL3 DDR_B_DQS7
(11) +SM_VREF SM_VREF RSVD SB_DQS7
+SA_DIMM_VREFDQ AR6 BD38
(11) +SA_DIMM_VREFDQ SA_DIMM_VREFDQ RSVD
+SB_DIMM_VREFDQ AN6 BA40
(12) +SB_DIMM_VREFDQ SB_DIMM_VREFDQ RSVD AY40 BF39
BC53 RSVD BA39 RSVD BE39
RSVD RSVD AY39 RSVD BF37
RSVD AV40 RSVD BE37
RSVD AU40 RSVD BD39
RSVD AV39 RSVD BC39
RSVD AU39 RSVD BC37
RSVD RSVD BD37
RSVD
3 OF 12
HSW-QUAD-CORE-GT2_BGA1364 4 OF 12
HSW-QUAD-CORE-GT2_BGA1364

A A

Security Classification Compal Secret Data

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(3/7) DDRIII
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 6 of 59
5 4 3 2 1
 5 4 3 2 1

D D

COMPENSATION PU FOR eDP
+VCOMP_OUT

EDP_COMP 2 1
24.9_0402_1% R14

Note:
HASWELL_BGA_E
Trace width=20 mils ,Spacing=25mil, 
U1J @
Max length=100 mils.

TMDS_B_DATA2#_PCH C25 F15 EDP_CPU_AUX#

(24) TMDS_B_DATA2#_PCH DDIB_TXN0 EDP_AUXN EDP_CPU_AUX# (22)
HDMI D2 TMDS_B_DATA2_PCH D25 F14 EDP_CPU_AUX
(24) TMDS_B_DATA2_PCH DDIB_TXP0 EDP_AUXP EDP_CPU_AUX (22)
TMDS_B_DATA1#_PCH A25 E14 EDP_HPD#
(24) TMDS_B_DATA1#_PCH DDIB_TXN1 EDP_HPD
HDMI D1 TMDS_B_DATA1_PCH B25
(24) TMDS_B_DATA1_PCH DDIB_TXP1
HDMI TMDS_B_DATA0#_PCH C24 C14 EDP_CPU_LANE_N0
(24) TMDS_B_DATA0#_PCH DDIB_TXN2 EDP_TXN0 EDP_CPU_LANE_N0 (22)
HDMI D0 (24) TMDS_B_DATA0_PCH
TMDS_B_DATA0_PCH D24
A24 DDIB_TXP2 EDP_TXN1
A12
D14
EDP_CPU_LANE_N1
EDP_CPU_LANE_N1 (22)
TMDS_B_CLK#_PCH EDP_CPU_LANE_P0
(24) TMDS_B_CLK#_PCH DDIB_TXN3 EDP_TXP0 EDP_CPU_LANE_P0 (22)
C
HDMI CLK (24) TMDS_B_CLK_PCH
TMDS_B_CLK_PCH B24
DDIB_TXP3 EDP_TXP1
B12 EDP_CPU_LANE_P1
EDP_CPU_LANE_P1 (22) C
C21 AG6 EDP_COMP
D21 DDIC_TXN0 EDP_RCOMP E12 T14
A21 DDIC_TXP0 EDP_DISP_UTIL
B21 DDIC_TXN1 C12 EDP_CPU_LANE_N2
DDIC_TXP1 FDI_TXN0 EDP_CPU_LANE_N2 (22)
C20 D12 EDP_CPU_LANE_P2
DDIC_TXN2 FDI_TXP0 EDP_CPU_LANE_P2 (22)
D20 A14 EDP_CPU_LANE_N3
DDIC_TXP2 FDI_TXN1 EDP_CPU_LANE_N3 (22)
A20 B14 EDP_CPU_LANE_P3
DDIC_TXN3 FDI_TXP1 EDP_CPU_LANE_P3 (22)
B20
DDIC_TXP3
C16
D16 DDID_TXN2
A16 DDID_TXP2
B16 DDID_TXN3
DDID_TXP3

C17
D17 DDID_TXN0
A17 DDID_TXP0
DDID_TXN1
HPD INVERSION FOR EDP
B17
DDID_TXP1 +VCCIO_OUT

10K_0402_5%
2
10 OF 12

R15
HSW-QUAD-CORE-GT2_BGA1364

1
B EDP_HPD# B

Q1
D

1
LBSS138LT1G_SOT-23-3 2 EDP_HPD (22)
G

1 R16
S

100K_0402_5%
2
HPD is a active-high signal from device. The HPD processor input is
active-low signal.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(4/7) eDP,DP and HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 7 of 59
5 4 3 2 1
 5 4 3 2 1

CFG Straps for Processor

CFG2

2
R17
1K_0402_1%
D D

1
PEG Static Lane Reversal - CFG2 is for the 16x

1: Normal Operation; Lane # definition matches

CFG2 socket pin map definition
0:Lane Reversed
U1K @ HASWELL_BGA_E *
CFG4
F1
RSVD_TP

1
E1
BE4 RSVD_TP A5
BD3 RSVD_TP RSVD_TP A6 R18
RSVD_TP RSVD_TP 1K_0402_1%
F6 R54 CFG_RCOMP
RSVD_TP CFG_RCOMP

2
G6 Y52 CFG16 T15
RSVD_TP CFG16 V53
G21 CFG18 Y51
G24 RSVD_TP CFG17 V52
H_CPU_RSVD F21 RSVD_TP CFG19
G19 TESTLO_F21 B50
F51 VSS RSVD AH49
VSS RSVD Embedded Display Port Presence Strap
F52 AM48
F22 VSS RSVD AU27
+VCC_CORE VCC RSVD
C 1 2 H_CPU_TESTLO AU26 1 : Disabled; No Physical Display Port C
RSVD
R19 49.9_0402_1% L52
RSVD_TP RSVD
BD4 CFG4 attached to Embedded Display Port
1 2 CFG_RCOMP L53 BC4
R20 49.9_0402_1% RSVD_TP RSVD AL6
RSVD
1 2 H_CPU_RSVD L51 F8 0 : Enabled; An external Display Port device is
R21 49.9_0402_1%
F24
RSVD_TP

RSVD_TP
RSVD
* connected to the Embedded Display Port
F25
H_CPU_TESTLO F20 RSVD_TP
TESTLO_F20
CFG0 AG49 F16
T16 CFG0 RSVD
CFG1 AD49
T17 CFG1
CFG2 AC49
CFG3 AE49 CFG2 CFG5
T18 CFG3
CFG4 Y50
CFG5 AB49 CFG4 CFG6
CFG6 V51 CFG5 G12
CFG6 RSVD_TP

2
CFG7 W51 G10
Y49 CFG7 RSVD_TP @ R22 R23 @
Y54 CFG8 H54 1K_0402_1% 1K_0402_1%
T19 CFG9 VSS
Y53 H53
W53 CFG10 VSS
CFG11

1
U53 H51
V54 CFG12 VSS H52
R53 CFG13 VSS
R52 CFG14 N51
CFG15 RSVD G53
L50 RSVD H50
RSVD RSVD PCIE Port Bifurcation Straps
L49
E5 RSVD
RSVD
11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
11 OF 12
HSW-QUAD-CORE-GT2_BGA1364 CFG[6:5] *10: x8, x8 - Device 1 function 1 enabled ; function 2 B

disabled
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled

CFG7

2
@ R24
1K_0402_1%

1
PEG DEFER TRAINING

1: (Default) PEG Train immediately following xxRESETB

CFG7 * de assertion

A
0: PEG Wait for BIOS for training A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(5/7) RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 8 of 59
5 4 3 2 1
 5 4 3 2 1

+1.35V_CPU_VDDQ Source +1.35V +1.35V_CPU_VDDQ

+1.35V
Note: @ +1.35V_CPU_VDDQ
JP1
Intel Shark Bay 2 1 C37 @
0.1U_0402_16V7K
Removed the S3 power reduction circuit. JUMP_43X118 1 2
@
JP2
C36
2 1 0.1U_0402_16V7K
1 2
JUMP_43X118
@

D D

@ +VCC_CORE
HASWELL_BGA_E +VCC_CORE +VCC_CORE
U1E
U1F @ HASWELL_BGA_E
J17 B43
+1.35V_CPU_VDDQ J21 RSVD VCC B45 AB45 H33
+VCC_CORE J26 RSVD VCC B46 AB46 VCC VCC H34
VCC_SENSE J31 RSVD
RSVD
VCC
VCC
B48 AB8 VCC
VCC
VCC
VCC
H36
C27 AC46 H37
AR29 VCC C28 AC47 VCC VCC H38
100_0402_1%

Note: VDDQ VCC VCC VCC

1

AR31 C31 AC8 H39

0 ohm Resistor should be placed AR33 VDDQ VCC C32 AC9 VCC VCC H40
R27

AT13 VDDQ VCC C34 AD46 VCC VCC H42

cloose to CPU AT19 VDDQ VCC C36 AD8 VCC VCC H43
AT23 VDDQ VCC C38 AE46 VCC VCC H45
VDDQ VCC VCC VCC
2

AT27 C39 AE47 H46

AT32 VDDQ VCC C42 AE8 VCC VCC H48
VCCSENSE 1 2 VCCSENSE_R AT36 VDDQ VCC C43 AF8 VCC VCC H8
(55) VCCSENSE VDDQ VCC VCC VCC
R25 0_0402_5% AV37 C45 AG46 H9
AW22 VDDQ VCC C46 AG8 VCC VCC J10
AW25 VDDQ VCC C48 AH46 VCC VCC J14
VSSSENSE 1 2 VSSSENSE_R AW29 VDDQ VCC D27 AH47 VCC VCC J19
(55) VSSSENSE VSSSENSE_R (10) VDDQ VCC VCC VCC
R28 0_0402_5% AW33 D28 AH8 J24
AY18 VDDQ VCC D31 AJ45 VCC VCC J29
VDDQ VCC VCC VCC
1

BB21 D32 AJ46 J33

100_0402_1%

BB22 VDDQ VCC D34 AK46 VCC VCC J36

+VCCIO_OUT BB26 VDDQ VCC D36 AK47 VCC VCC J37
R26

BB27 VDDQ VCC D38 AK8 VCC VCC J38

BB30 VDDQ VCC D39 AL45 VCC VCC J39
VDDQ VCC VCC VCC
2

BB31 D42 AL46 J40

BB34 VDDQ VCC D43 AL8 VCC VCC J42
BB36 VDDQ VCC D45 AL9 VCC VCC J43

2.2U_0603_10V6K
BD22 VDDQ VCC D46 AM46 VCC VCC J45

C38
1 VDDQ VCC VCC VCC
BD26 D48 AM47 J46
BD30 VDDQ VCC E27 AM8 VCC VCC J48
BD33 VDDQ VCC E28 AM9 VCC VCC J8
2 BE18 VDDQ VCC E31 AN10 VCC VCC J9
C C
BE22 VDDQ VCC E32 AN12 VCC VCC K38
BE26 VDDQ VCC E34 AN13 VCC VCC K40
BE30 VDDQ VCC E36 AN14 VCC VCC K43
BE33 VDDQ VCC E38 AN15 VCC VCC K44
VDDQ VCC E39 AN16 VCC VCC K45
AN31 VCC E42 AN17 VCC VCC K46
L6 RSVD VCC E43 AN19 VCC VCC K48
+VCC_CORE VCC VCC VCC VCC
M6 E45 AN20 K8
AN22 VCC VCC E46 AN21 VCC VCC K9
AN18 RSVD VCC E48 AN23 VCC VCC L37
RSVD VCC F27 AN24 VCC VCC L38
Broadwell/Haswell VCCSENSE_R C50 VCC F28 AN25 VCC VCC L39
+VCCIO_OUT 0_0805_5% AH9 VCC_SENSE VCC F31 AN26 VCC VCC L40
2 R29 1 +VCCIO_OUT_R D51 RSVD VCC F32 AN27 VCC VCC L42
+VCCIO_OUT VCCIO_OUT VCC VCC VCC
Note: +PCH_VPROC F17 F34 AN29 L43
AK6 FC_F17 VCC F36 AN30 VCC VCC L44
+VCOMP_OUT VCOMP_OUT VCC VCC VCC
1

Place the UP resistor close to CPU AN33
RSVD VCC
F38 AN32
VCC VCC
L46
R30 W9 F39 AN34 L47
75_0402_1% J12 RSVD VCC F42 AN36 VCC VCC L8
AR49 RSVD VCC F43 AN38 VCC VCC M37
RSVD VCC F45 AN39 VCC VCC M38
VCC VCC VCC
2

R31 1 2 43_0402_5% H_CPU_SVIDALRT# J53 F46 AN40 M39

(55) VR_SVID_ALRT# VIDALERT VCC VCC VCC
VR_SVID_CLK J52 F48 AN41 M40
(55) VR_SVID_CLK VIDSCLK VCC VCC VCC
VR_SVID_DAT J50 G27 AN42 M42
(55) VR_SVID_DAT VIDSOUT VCC VCC VCC
G29 AN43 M43
B51 VCC G31 AN44 VCC VCC M44
VSS VCC VCC VCC
1

Note: +1.05VS 2 R33 1 F19 G32 AN45 M45

R32 150_0402_1% E52 PWR_DEBUG VCC G34 AN46 VCC VCC M46
VSS VCC VCC VCC
2

Place the UP resistor close to CPU 130_0402_1% V49

RSVD_TP VCC
G36 AN8
VCC VCC
M8
U49 G38 AN9 M9
R34 AM49 RSVD_TP VCC G39 AP10 VCC VCC N37
RSVD_TP VCC VCC VCC
2

10K_0402_5% W49 G42 AP12 N38

@ V50 RSVD_TP VCC G43 AP13 VCC VCC N39
VSS VCC VCC VCC
1

+VCCIO_OUT AN49 G45 AP14 N40

AJ49 VSS VCC G46 AP15 VCC VCC N42
AG50 VSS VCC G48 AP16 VCC VCC N43
AK49 VSS VCC H11 +1.05VS Broadwell/Haswell AP17 VCC VCC N44
B
AJ50 VSS VCC H12 AP18 VCC VCC N46 B
AP49 VSS VCC H13 AP19 VCC VCC N47
AB50 VSS VCC H14 AP20 VCC VCC N8
VSS VCC VCC VCC

1
AP50 H16 AP21 N9
AD50 VSS VCC H17 R35 AP22 VCC VCC P45
AM50 VSS VCC H18 AP23 VCC VCC P46
VSS VCC 0_0805_5% VCC VCC
H19 BW@ AP24 P8
A36 VCC H20 AP25 VCC VCC R46

0.1U_0402_16V7K
+VCC_CORE VCC VCC VCC VCC

2
A38 H21 FC_D5 AP26 R47

C39
A39 VCC VCC H23 AP27 VCC VCC R8

10U_0603_6.3V6M
VCC VCC 1 1 VCC VCC
A42 H24 AP29 R9

C40
A43 VCC VCC H25 AP30 VCC VCC T45

BW@
@
A45 VCC VCC H26 AP31 VCC VCC T46
A46 VCC VCC H27 2 2 AP32 VCC VCC U46
A48 VCC VCC H29 AP33 VCC VCC U47
AA46 VCC VCC
VCCST AP34 VCC VCC U8
AA47 VCC AP35 VCC VCC U9
VDDQ DECOUPLING (Follow INTEL DG) AA8 VCC
VCC FC_D5
D5 AP36 VCC
VCC
VCC
VCC
V45
AA9 D3 FC_D3 2 R36 BW@
1 AP37 V46
VCC FC_D3 1.05V PCH_PWROK (14,31) VCC VCC
+1.35V_CPU_VDDQ AP38 V8
VCC VCC

1
Close to CPU Close to CPU Close to CPU 5 OF 12 2K_0402_1% AP39 W46
HSW-QUAD-CORE-GT2_BGA1364 R37 BW@ AP40 VCC VCC W47
1K_0402_1% AP41 VCC VCC W8
AP42 VCC VCC Y45
AP43 VCC VCC Y46
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

VCC VCC

2
AP44 Y8
330U_D2_2V_Y

330U_D2_2V_Y

1 1 1 1 1 1 1 1 1 1 1 1 VCC VCC
AP46 A27
C41

C42

C43

C44

C45

C46

C47

C48

C49

C50

+ + AP47 VCC VCC A28

C51

C52

@ @ @ AP8 VCC VCC A31

2 2 2 2 2 2 2 2 2 2 @ AP9 VCC VCC A32
2 2 AR35 VCC VCC A34
AR37 VCC VCC B27
V0.1A V0.1A AR39 VCC VCC B28
AR41 VCC VCC B31
AR43 VCC VCC B32
AR45 VCC VCC B34
AR46 VCC VCC B36
H30 VCC VCC B38
A A
H31 VCC VCC B39
H32 VCC VCC B42
22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

VCC 6 OF 12 VCC
1 1 1 1 1 1 1 1 1 1 1
C53

C54

C55

C56

C57

C58

C59

C60

C61

C62

C63

HSW-QUAD-CORE-GT2_BGA1364

@ @ @ @ @
2 2 2 2 2 2 2 2 2 2 2

Security Classification Compal Secret Data

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title
V0.1A
Close to CPU Close to CPU
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(6/7) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 9 of 59
5 4 3 2 1
 5 4 3 2 1

HASWELL_BGA_E
U1I @

BC10 G20
BC12 VSS VSS G23 U1H @ HASWELL_BGA_E
BC15 VSS VSS G25 U1G @ HASWELL_BGA_E
BC18 VSS VSS G26 AT40 AY50
BC22 VSS VSS G30 A11 AJ48 AT42 VSS VSS AY9
BC26 VSS VSS G33 A15 VSS VSS AJ51 AT43 VSS VSS B11
BC3 VSS VSS G37 A19 VSS VSS AJ54 AT45 VSS VSS B15
BC30 VSS VSS G40 A22 VSS VSS AK48 AT46 VSS VSS B19
D BC33 VSS VSS G44 A26 VSS VSS AK5 AT47 VSS VSS B22 D
BC36 VSS VSS G49 A30 VSS VSS AK50 AT49 VSS VSS B26
BC38 VSS VSS G52 A33 VSS VSS AK7 AT5 VSS VSS B30
BC41 VSS VSS G54 A37 VSS VSS AK9 AT50 VSS VSS B33
BC43 VSS VSS G7 A40 VSS VSS AL1 AT51 VSS VSS B37
BC46 VSS VSS G8 A44 VSS VSS AL4 AT52 VSS VSS B40
BC48 VSS VSS G9 AA1 VSS VSS AL48 AT53 VSS VSS B44
BC5 VSS VSS H44 AA2 VSS VSS AL5 AT54 VSS VSS B49
BC50 VSS VSS H49 AA3 VSS VSS AL7 AT6 VSS VSS B8
BC52 VSS VSS H7 AA4 VSS VSS AM5 AT8 VSS VSS BA13
BC7 VSS VSS J44 AA48 VSS VSS AM51 AT9 VSS VSS BA18
BD10 VSS VSS J49 AA5 VSS VSS AM52 AU13 VSS VSS BA22
BD15 VSS VSS J51 AA7 VSS VSS AM53 AU18 VSS VSS BA25
BD18 VSS VSS J54 AB5 VSS VSS AM54 AU22 VSS VSS BA29
BD36 VSS VSS J7 AB51 VSS VSS AM7 AU25 VSS VSS BA33
BD41 VSS VSS K1 AB52 VSS VSS AN1 AU29 VSS VSS BA37
BD46 VSS VSS K2 AB53 VSS VSS AN2 AU33 VSS VSS BA4
BD5 VSS VSS K3 AB54 VSS VSS AN3 AU37 VSS VSS BA42
BD51 VSS VSS K4 AB7 VSS VSS AN4 AU42 VSS VSS BA5
BE10 VSS VSS K5 AB9 VSS VSS AN48 AU5 VSS VSS BA50
BE15 VSS VSS K6 AC48 VSS VSS AN5 AU9 VSS VSS BA51
BE36 VSS VSS K7 AC5 VSS VSS AN50 AV1 VSS VSS BA52
BE41 VSS VSS L48 AC50 VSS VSS AN7 AV13 VSS VSS BA53
BE46 VSS VSS L7 AC7 VSS VSS AP51 AV18 VSS VSS BA9
BF10 VSS VSS L9 AD48 VSS VSS AP54 AV2 VSS VSS BB10
BF12 VSS VSS M48 AD51 VSS VSS AP7 AV22 VSS VSS BB11
BF15 VSS VSS M50 AD54 VSS VSS AR12 AV25 VSS VSS BB12
BF18 VSS VSS M52 AD7 VSS VSS AR14 AV29 VSS VSS BB14
BF22 VSS VSS M54 AD9 VSS VSS AR16 AV3 VSS VSS BB15
BF26 VSS VSS M7 AE1 VSS VSS AR18 AV33 VSS VSS BB16
BF30 VSS VSS N48 AE2 VSS VSS AR20 AV4 VSS VSS BB17
BF33 VSS VSS N7 AE3 VSS VSS AR24 AV42 VSS VSS BB18
C BF36 VSS VSS P1 AE4 VSS VSS AR26 AV5 VSS VSS BB20 C
BF38 VSS VSS P2 AE48 VSS VSS AR48 AV50 VSS VSS BB23
BF41 VSS VSS P3 AE5 VSS VSS AR5 AV9 VSS VSS BB25
BF43 VSS VSS P4 AE50 VSS VSS AR50 AW13 VSS VSS BB28
BF46 VSS VSS P48 AE7 VSS VSS AR7 AW18 VSS VSS BB32
BF48 VSS VSS P5 AF5 VSS VSS AR8 AW37 VSS VSS BB33
BF7 VSS VSS P50 AF6 VSS VSS AR9 AW42 VSS VSS BB37
C11 VSS VSS P52 AF7 VSS VSS AT1 AW43 VSS VSS BB38
C15 VSS VSS P54 AG48 VSS VSS AT10 AW45 VSS VSS BB39
C19 VSS VSS P6 AG5 VSS VSS AT12 AW46 VSS VSS BB41
C22 VSS VSS P7 AG51 VSS VSS AT15 AW47 VSS VSS BB42
C26 VSS VSS R48 AG52 VSS VSS AT16 AW49 VSS VSS BB43
C30 VSS VSS R7 AG53 VSS VSS AT18 AW5 VSS VSS BB44
C33 VSS VSS T48 AG54 VSS VSS AT20 AW50 VSS VSS BB46
C37 VSS VSS U1 AG7 VSS VSS AT22 AW51 VSS VSS BB47
C4 VSS VSS U2 AG9 VSS VSS AT25 AW54 VSS VSS BB48
C40 VSS VSS U3 AH1 VSS VSS AT26 AW9 VSS VSS BB49
C44 VSS VSS U4 AH2 VSS VSS AT29 AY13 VSS VSS BB5
C49 VSS VSS U48 AH3 VSS VSS AT33 AY22 VSS VSS BB6
C52 VSS VSS U5 AH4 VSS VSS AT35 AY25 VSS VSS BB7
C8 VSS VSS U50 AH48 VSS VSS AT37 AY29 VSS VSS BB9
D11 VSS VSS U52 AH5 VSS VSS AT39 AY33 VSS VSS
D15 VSS VSS U54 AH50 VSS VSS AT4 AY37 VSS
D19 VSS VSS U6 AH7 VSS VSS AY42 VSS
D22 VSS VSS U7 VSS 7 OF 12 VSS 8 OF 12
D26 VSS VSS V48 HSW-QUAD-CORE-GT2_BGA1364 HSW-QUAD-CORE-GT2_BGA1364
D30 VSS VSS V7
D33 VSS VSS V9
D37 VSS VSS W48
D40 VSS VSS W50
D44 VSS VSS W52
D49 VSS VSS W54
B D8 VSS VSS W7 B
E11 VSS VSS Y48
E15 VSS VSS Y7
E16 VSS VSS Y9
E17 VSS VSS
E19 VSS AR22
E20 VSS VSS AB48
E21 VSS VSS P9
E22 VSS VSS G18
E24 VSS VSS
E25 VSS A49
E26 VSS VSS_NCTF A50
E30 VSS VSS_NCTF A8
E33 VSS VSS_NCTF B4
E37 VSS VSS_NCTF BA1
E40 VSS VSS_NCTF BA54
E44 VSS VSS_NCTF BB1
E49 VSS VSS_NCTF BB54
E51 VSS VSS_NCTF BD2
E53 VSS VSS_NCTF BD53
E8 VSS VSS_NCTF BF49
F2 VSS VSS_NCTF BF5
F26 VSS VSS_NCTF BF50
F3 VSS VSS_NCTF BF6
F30 VSS VSS_NCTF C53
F33 VSS VSS_NCTF D2
F37 VSS VSS_NCTF E54
F4 VSS VSS_NCTF F54
F40 VSS VSS_NCTF G1
F44 VSS VSS_NCTF
F49 VSS D50
VSS VSS_SENSE VSSSENSE_R (9)
F5
A G11 VSS A
G13 VSS
G16 VSS
VSS
9 OF 12
HSW-QUAD-CORE-GT2_BGA1364

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 10 of 59
5 4 3 2 1
 5 4 3 2 1

+1.35V +1.35V
3A@1. 35V
(6) DDR_A_D[0..63]
DDR3 SO-DIMM A (6) DDR_A_DQS[0..7]
JDIMM1 CONN@
(6) DDR_A_DQS#[0..7]
+VREF_DQ_DIMMA 1 2
3 VREF_DQ VSS 4 DDR_A_D4
VSS DQ4 (6) DDR_A_MA[0..15]
DDR_A_D0 5 6 DDR_A_D5

2.2U_0603_10V6K

0.1U_0402_16V7K
DDR_A_D1 7 DQ0 DQ5 8

C64

C65
1 1 DQ1 VSS
9 10 DDR_A_DQS#0 Layout Note:
11 VSS DQS0# 12 DDR_A_DQS0
13 DM0 DQS0 14
Layout Note: Place near JDIMM1
2 2 DDR_A_D6 15 VSS VSS 16 DDR_A_D3 Place near JDIMM1
D DDR_A_D2 17 DQ2 DQ6 18 DDR_A_D7 D
19 DQ3 DQ7 20
DDR_A_D12 21 VSS VSS 22 DDR_A_D8
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26 +0.675VS
DDR_A_DQS#1 27 VSS VSS 28 +1.35V
DDR_A_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# (12,5)
31 32
DDR_A_D14 33 VSS VSS 34 DDR_A_D11
DDR_A_D10 35 DQ10 DQ14 36 DDR_A_D15

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
37 DQ11 DQ15 38
VSS VSS 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
DDR_A_D16 39 40 DDR_A_D17

C66

C67

C68

C69

C70

C71

C72

C73

C74

C75

C76

C77

C78

C79

C80

C81
DDR_A_D20 41 DQ16 DQ20 42 DDR_A_D21 @ @
43 DQ17 DQ21 44
DDR_A_DQS#2 45 VSS VSS 46 2 @2 2 @2 2 2 2 2 2 2 2 2 2 2 2 2
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS 50 DDR_A_D22
DDR_A_D18 51 VSS DQ22 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54
55 DQ19 VSS 56 DDR_A_D30
DDR_A_D26 57 VSS DQ28 58 DDR_A_D25
DQ24 DQ29 Place near JDIMM1 pin203 pin204
DDR_A_D24 59 60
61 DQ25 VSS 62 DDR_A_DQS#3
63 VSS DQS3# 64 DDR_A_DQS3
65 DM3 DQS3 66
DDR_A_D29 67 VSS VSS 68 DDR_A_D28
DDR_A_D31 69 DQ26
DQ27
DQ30
DQ31
70 DDR_A_D27 CPU DRIVER
71 72
VSS VSS
VREF PATH IS
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA +1.35V *M3+M1:Default Recommendation
(6) DDR_CKE0_DIMMA
75 CKE0 CKE1 76
DDR_CKE1_DIMMA (6) DEFAULT   M1:VREF_DQ driven by a voltage Divider Network during 
C 77 VDD VDD 78 DDR_A_MA15 C
NC A15 Note:           Processor power‐off state.

2
(6) DDR_A_BS2 DDR_A_BS2 79 80 DDR_A_MA14
81 BA2 A14 82 VREF trace width:20 mils at least
VDD VDD
R38   M3:VREF_DQ driven by Processor.
DDR_A_MA12 83 84 DDR_A_MA11 1K_0402_1%
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7 Spacing:20mils to other signal/planes
87 A9 A7 88
VDD VDD

1
DDR_A_MA8 89 90 DDR_A_MA6 R39
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4 +SM_VREF 1 2 +VREF_CA
A5 A4 (6) +SM_VREF +VREF_CA (12)
93 94 2.2_0402_1%
VDD VDD

2
DDR_A_MA3 95 96 DDR_A_MA2

0.022U_0402_16V7K
C82
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0 R40
99 A1 A0 100 1K_0402_1%
VDD VDD

1 2
(6) M_CLK_DDR0 M_CLK_DDR0 101 102 M_CLK_DDR1
CK0 CK1 M_CLK_DDR1 (6)
(6) M_CLK_DDR#0 M_CLK_DDR#0 103 104 M_CLK_DDR#1
CK0# CK1# M_CLK_DDR#1 (6)

1
105 106 R41
DDR_A_MA10 107 VDD VDD 108 DDR_A_BS1
A10/AP BA1 DDR_A_BS1 (6) 24.9_0402_1%
(6) DDR_A_BS0 DDR_A_BS0 109 110 DDR_A_RAS#
BA0 RAS# DDR_A_RAS# (6)
111 112
VDD VDD

2
(6) DDR_A_WE# DDR_A_WE# 113 114 DDR_CS0_DIMMA#
WE# S0# DDR_CS0_DIMMA# (6)
(6) DDR_A_CAS# DDR_A_CAS# 115 116 M_ODT0
CAS# ODT0 M_ODT0 (6)
117 118
DDR_A_MA13 119 VDD VDD 120 M_ODT1
A13 ODT1 M_ODT1 (6)
(6) DDR_CS1_DIMMA# DDR_CS1_DIMMA# 121 122
123 S1# NC 124
125 VDD VDD 126 +VREF_CA
127 TEST VREF_CA 128
DDR_A_D33 129 VSS VSS 130 DDR_A_D36 +1.35V

0.1U_0402_16V7K

2.2U_0603_10V6K
DDR_A_D32 131 DQ32 DQ36 132 DDR_A_D37

C83

C84
DQ33 DQ37 1 1
133 134
DDR_A_DQS#4 135 VSS VSS 136
DQS4# DM4

2
DDR_A_DQS4 137 138
139 DQS4 VSS 140 DDR_A_D38 2 2 Note: R42
B DDR_A_D34 141 VSS DQ38 142 DDR_A_D39 VREF trace width:20 mils at least B
DQ34 DQ39 1K_0402_1%
DDR_A_D35 143 144
145 DQ35 VSS 146 DDR_A_D44 Spacing:20mils to other signal/planes
VSS DQ44

1
DDR_A_D45 147 148 DDR_A_D40
DDR_A_D41 149 DQ40 DQ45 150 +SA_DIMM_VREFDQ 1 R43 2 +VREF_DQ_DIMMA
DQ41 VSS (6) +SA_DIMM_VREFDQ
151 152 DDR_A_DQS#5 2.2_0402_1%
VSS DQS5#

2
153 154 DDR_A_DQS5

0.022U_0402_16V7K
C85
155 DM5 DQS5 156 R44
DDR_A_D42 157 VSS VSS 158 DDR_A_D46 1K_0402_1%
DQ42 DQ46

1 2
DDR_A_D43 159 160 DDR_A_D47
161 DQ43 DQ47 162
VSS VSS

1
DDR_A_D48 163 164 DDR_A_D52 R45
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
DQ49 DQ53 24.9_0402_1%
167 168
DDR_A_DQS#6 169 VSS VSS 170
DQS6# DM6

2
DDR_A_DQS6 171 172
173 DQS6 VSS 174 DDR_A_D54
DDR_A_D50 175 VSS DQ54 176 DDR_A_D55
DDR_A_D51 177 DQ50 DQ55 178
179 DQ51 VSS 180 DDR_A_D60
DDR_A_D56 181 VSS DQ60 182 DDR_A_D61
DDR_A_D57 183 DQ56 DQ61 184
185 DQ57 VSS 186 DDR_A_DQS#7
187 VSS DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D62 191 VSS VSS 192 DDR_A_D63
DDR_A_D58 193 DQ58 DQ62 194 DDR_A_D59
195 DQ59 DQ63 196
197 VSS VSS 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 (12,16,32)
201 202 SMB_CLK_S3
2.2U_0603_10V6K

0.1U_0402_16V7K

SA1 SCL SMB_CLK_S3 (12,16,32)

203 204
C86

C87

1 1 VTT VTT +0.675VS

A A
205 206 0. 65A@0. 675V
207 GND1 GND2 208
2 2 BOSS1 BOSS2

LCN_DAN06-K4406-0103

SP07000LT00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 11 of 59
5 4 3 2 1
 5 4 3 2 1

3A@1. 35V
(6) DDR_B_D[0..63]
+1.35V +1.35V
(6) DDR_B_DQS[0..7]
JDIMM2 CONN@
(6) DDR_B_DQS#[0..7]
+VREF_DQ_DIMMB 1 2
3 VREF_DQ VSS1 4 DDR_B_D5
VSS2 DQ4 (6) DDR_B_MA[0..15]
DDR_B_D0 5 6 DDR_B_D1
DDR_B_D4 7 DQ0 DQ5 8
9 DQ1 VSS3 10 DDR_B_DQS#0

2.2U_0603_10V6K

0.1U_0402_16V7K
11 VSS4 DQS#0 12 DDR_B_DQS0

C90

C91
1 1 DM0 DQS0
13 14
DDR_B_D2 15 VSS5 VSS6 16 DDR_B_D6
DDR_B_D3 17 DQ2 DQ6 18 DDR_B_D7
D 2 2 19 DQ3 DQ7 20 D
DDR_B_D15 21 VSS7 VSS8 22 DDR_B_D8
Layout Note:
DDR_B_D9 23 DQ8 DQ12 24 DDR_B_D14 Place near JDIMM2
25 DQ9 DQ13 26
DDR_B_DQS#1 27 VSS9 VSS10 28
DDR_B_DQS1 29 DQS#1 DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# (11,5)
31 32
DDR_B_D12 33 VSS11 VSS12 34 DDR_B_D11 +0.675VS
DDR_B_D10 35 DQ10 DQ14 36 DDR_B_D13
37 DQ11 DQ15 38
DDR_B_D21 39 VSS13 VSS14 40 DDR_B_D16
DDR_B_D17 41 DQ16 DQ20 42 DDR_B_D20
43 DQ17 DQ21 44

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
DDR_B_DQS#2 45 VSS15 VSS16 46
DQS#2 DM2 1 1 1 1
DDR_B_DQS2 47 48

C92

C93

C94

C95
49 DQS2 VSS17 50 DDR_B_D19
DDR_B_D23 51 VSS18 DQ22 52 DDR_B_D18 @
DDR_B_D22 53 DQ18 DQ23 54 2 2 2 @2
55 DQ19 VSS19 56 DDR_B_D25
DDR_B_D28 57 VSS20 DQ28 58 DDR_B_D29
DDR_B_D24 59 DQ24 DQ29 60 +1.35V
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS#3 64 DDR_B_DQS3
DM3 DQS3 Place near JDIMM2 pin203 pin204
65 66
VSS23 VSS24

2
DDR_B_D26 67 68 DDR_B_D30 Note:
DDR_B_D27 69 DQ26 DQ30 70 DDR_B_D31 R46
71 DQ27 DQ31 72 VREF trace width:20 mils at least
VSS25 VSS26 1K_0402_1%
Spacing:20mils to other signal/planes

1
(6) DDR_CKE2_DIMMB DDR_CKE2_DIMMB 73 74 DDR_CKE3_DIMMB +SB_DIMM_VREFDQ 1 R47 2 +VREF_DQ_DIMMB
CKE0 CKE1 DDR_CKE3_DIMMB (6) (6) +SB_DIMM_VREFDQ
75 76 2.2_0402_1%
VDD1 VDD2

1
C 77 78 DDR_B_MA15 C

0.022U_0402_16V7K
C96
NC1 A15

2
(6) DDR_B_BS2 DDR_B_BS2 79 80 DDR_B_MA14
81 BA2 A14 82 R48
VDD3 VDD4

1 2
DDR_B_MA12 83 84 DDR_B_MA11 1K_0402_1%
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88 R49
VDD5 VDD6

1
DDR_B_MA8 89 90 DDR_B_MA6 24.9_0402_1%
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
VDD7 VDD8

2
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
99 A1 A0 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
(6) M_CLK_DDR2 CK0 CK1 M_CLK_DDR3 (6)
(6) M_CLK_DDR#2 M_CLK_DDR#2 103 104 M_CLK_DDR#3
CK0# CK1# M_CLK_DDR#3 (6)
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
A10/AP BA1 DDR_B_BS1 (6)
(6) DDR_B_BS0 DDR_B_BS0 109 110 DDR_B_RAS#
BA0 RAS# DDR_B_RAS# (6)
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS2_DIMMB#
(6) DDR_B_WE# WE# S0# DDR_CS2_DIMMB# (6)
(6) DDR_B_CAS# DDR_B_CAS# 115 116 M_ODT2 Layout Note:
CAS# ODT0 M_ODT2 (6)
117 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3
M_ODT3 (6)
Place near JDIMM2
DDR_CS3_DIMMB# 121 A13 ODT1 122
(6) DDR_CS3_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126
NCTEST VREF_CA +VREF_CA (11)
127 128
DDR_B_D33 129 VSS27 VSS28 130 DDR_B_D36

0.1U_0402_16V7K

2.2U_0603_10V6K
DDR_B_D37 131 DQ32 DQ36 132 DDR_B_D32

C97

C98
DQ33 DQ37 1 1
133 134 +1.35V
DDR_B_DQS#4 135 VSS29 VSS30 136
DDR_B_DQS4 137 DQS#4 DM4 138
139 DQS4 VSS31 140 DDR_B_D35 2 2
B DDR_B_D34 141 VSS32 DQ38 142 DDR_B_D39 B

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
DDR_B_D38 143 DQ34 DQ39 144
DQ35 VSS33 1 1 1 1 1 1 1 1 1 1 1 1
145 146 DDR_B_D41

C99

C100

C101

C102

C103

C104

C105

C106

C108

C109

C110
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D45 @ @

C107
DDR_B_D44 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5 2 2 2 2 2 2 2 2 2 2 2 2
153 VSS36 DQS#5 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D46 157 VSS37 VSS38 158 DDR_B_D47
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D43
161 DQ43 DQ47 162
DDR_B_D52 163 VSS39 VSS40 164 DDR_B_D53
DDR_B_D48 165 DQ48 DQ52 166 DDR_B_D49
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS#6 DM6 172
173 DQS6 VSS43 174 DDR_B_D50
DDR_B_D55 175 VSS44 DQ54 176 DDR_B_D54
DDR_B_D51 177 DQ50 DQ55 178
+3VS 179 DQ51 VSS45 180 DDR_B_D60
DDR_B_D56 181 VSS46 DQ60 182 DDR_B_D61
DDR_B_D57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDR_B_DQS#7
VSS48 DQS#7
2

187 188 DDR_B_DQS7

0_0402_5%

189 DM7 DQS7 190

DDR_B_D62 191 VSS49 VSS50 192 DDR_B_D63
R50

DDR_B_D58 193 DQ58 DQ62 194 DDR_B_D59

195 DQ59 DQ63 196
VSS51 VSS52
1

197 198
199 SA0 EVENT# 200 SMB_DATA_S3
+3VS VDDSPD SDA SMB_DATA_S3 (11,16,32)
201 202 SMB_CLK_S3
SA1 SCL SMB_CLK_S3 (11,16,32)
203 204 +0.675VS
A VTT1 VTT2 0. 65A@0. 675V A
205 206
2.2U_0603_10V6K

0.1U_0402_16V7K

1 1 G1 G2
LCN_DAN06-K4806-0103
C112

C114

SP07000M200
2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDRIII-SODIMM SLOT2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 12 of 59
5 4 3 2 1
 5 4 3 2 1

Note:
PCH_RTCX1/PCHRTCX2 
Trace length <1000 mils
PCH_RTCX1
NOGCLK@
1 2 PCH_RTCX2
R51 10M_0402_5%

Y1 NOGCLK@
1 2
32.768KHZ 12.5PF 9H03200031
Green CLK

15P_0402_50V8J

15P_0402_50V8J
NOGCLK@ C115

NOGCLK@ C116
1 1
D D
V0.2
2 2 PCH_RTCX1 R155 1 GCLK@ 2 0_0402_5%
+RTCVCC CLK_32K_RTC_XIN (27)

R52 1 2 1M_0402_5% SM_INTRUDER#

Note: +RTCVCC
Need to check with PWR update
R53 1 2 330K_0402_5% PCH_INTVRMEN U2A LPT_PCH_M_EDS
+RTCVCC CLRP2
OPEN SAVE ME RTC REGISTER BC8

SHORT PADS
CLRP1
INTVRMEN PCH_RTCX1 B5 SATA_RXN_0 BE8
RTCX1 SATA_RXP_0

1
(INTEGRATED SUS 1.05V VR) C118 SHORT CLEAR ME RTC REGISTER
* H：Integrated VRM enable 1U_0402_6.3V6K PCH_RTCX2 B4
RTCX2 SATA_TXN_0
AW8
L：Integrated VRM disable AY8

RTC
SATA_TXP_0

2
(INTVRMEN should always be pull high.) 1 2 PCH_SRTCRST# B9
R54 20K_0402_5% SRTCRST# BC10
1 2 PCH_RTCRST# SM_INTRUDER# A8 SATA_RXN_1 BE10
R55 20K_0402_5% INTRUDER# SATA_RXP_1 HM86 NA
+3V_PCH

1
C117 CLRP3 PCH_INTVRMEN G10 AV10

SHORT PADS
CLRP2
INTVRMEN SATA_TXN_1 AW10
1U_0402_6.3V6K OPEN SAVE CMOS SATA_TXP_1
R56 2 @ 1 1K_0402_5% HDA_SYNC D9
RTCRST#

2
SHORT CLEAR CMOS BB9
+3VS SATA_RXN_2 BD9
HDA_BIT_CLK B25 SATA_RXP_2
R57 1 @ 2 1K_0402_5% PCH_GPIO33 HDA_BCLK AY13
HDA_SYNC A22 SATA_TXN_2 AW13
HDA_SYNC SATA_TXP_2
HDA_SPKR AL10 BC12
(26) HDA_SPKR SPKR SATA_RXN_3 BE12
+3VS HDA_RST# C24 SATA_RXP_3 HM86 NA
HDA_RST# AR13
C R58 1 @ 2 1K_0402_5% HDA_SPKR HDA_SDIN0 L22 SATA_TXN_3 AT13 C

AZALIA

SATA
(26) HDA_SDIN0 HDA_SDI0 SATA_TXP_3
HIGH= Enable ( No Reboot ) K22
HDA_SDI1 BD13
* LOW= Disable (Default) SATA_RXN4/PERN1
SATA_PRX_DTX_N4 SATA_PRX_DTX_N4 (29)
G22 BB13 SATA_PRX_DTX_P4 SATA_PRX_DTX_P4 (29) HDD
HDA_SDI2 SATA_RXP4/PERP1
F22 AV15 SATA_PTX_DRX_N4 SATA_PTX_DRX_N4 (29)
HDA_SDI3 SATA_TXN4/PETN1 AW15 SATA_PTX_DRX_P4
SATA_TXP4/PETP1 SATA_PTX_DRX_P4 (29)
ME_FLASH A24
+3V_PCH (31) ME_FLASH HDA_SDO BC14
R59 1 @ 2 1K_0402_1% PCH_GPIO33 B17 SATA_RXN5/PERN2 BE14
R60 2 @ 1 1K_0402_5% ME_FLASH DOCKEN#/GPIO33 SATA_RXP5/PERP2

+3V_PCH R61 1 2 10K_0402_5% PCH_GPIO13 C22 AP15

HDA_DOCK_RST#/GPIO13 SATA_TXN5/PETN2 AR15
* Low = Disabled (Default) SATA_TXP5/PETP2
High = Enabled [Flash Descriptor Security Override]
AY5 SATA_COMP
SATA_RCOMP
AP3 SATA_LED#
SATALED# SATA_LED# (33) +3VS
EMI 2 R62 1 PCH_JTAG_TCK AB3
JTAG_TCK SATA0GP/GPIO21
AT1 PCH_GPIO21
RP3
RP2 51_0402_5% PCH_JTAG_TMS AD1 AU2 BBS_BIT0_R (18) PCH_GPIO35 PCH_GPIO35 4 5
8 1 HDA_SYNC JTAG_TMS SATA1GP/GPIO19 SATA_LED# 3 6
(26) HDA_SYNC_AUDIO
7 2 ME_FLASH PCH_JTAG_TDI AE2 BD4 PCH_GPIO21 2 7

JTAG
(26) HDA_SDOUT_AUDIO JTAG_TDI SATA_IREF +1.5VS
6 3 HDA_RST# BBS_BIT0_R 1 8
(26) HDA_RST_AUDIO#
(26) HDA_BITCLK_AUDIO 5 4 HDA_BIT_CLK PCH_JTAG_TDO AD3 BA2
JTAG_TDO TP9 10K_0804_8P4R_5%
33_0804_8P4R_5% F8 BB2
TP25 TP8

EMI@ C26
TP22
B PCH_JTAG_RST#AB6 B

+3V_PCH +3V_PCH +3V_PCH

T20 TP20 SATA Impedance Compensation
1 OF 11 +1.5VS
DH82HM86-SR17E-C2_FCBGA695
1

SATA_COMP 1 2
R63 R64 R65 7.5K_0402_1% R66
200_0402_1% 200_0402_1% 200_0402_1% Note: 
@ @ @
Trace width:4mils
2

PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_TDI Place the resistor to PCH <500 mils, to 1.5V <100 mils.Avoid 

routing next to clock pins. 
1

R67 R68 R69

100_0402_1% 100_0402_1% 100_0402_1%
@ @ @
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (1/9) SATA,HDA,SPI, LPC, XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 13 of 59
5 4 3 2 1
 5 4 3 2 1

LPT_PCH_M_EDS
U2B

(4) DMI_CTX_PRX_N0 DMI_CTX_PRX_N0 AW22 U2E LPT_PCH_M_EDS

DMI_CTX_PRX_N1 AR20 DMI_RXN_0
(4) DMI_CTX_PRX_N1 DMI_RXN_1 AJ35 T45 R40 HDMICLK_NB HDMICLK_NB (16,24)
DMI_CTX_PRX_N2 AP17 FDI_RXN_0 VGA_BLUE DDPB_CTRLCLK
(4) DMI_CTX_PRX_N2 DMI_RXN_2
(4) DMI_CTX_PRX_N3 DMI_CTX_PRX_N3 AV20 AL35 U44 R39 HDMIDAT_NB HDMIDAT_NB (16,24)
DMI_RXN_3 FDI_RXN_1 VGA_GREEN DDPB_CTRLDATA

(4) DMI_CTX_PRX_P0 DMI_CTX_PRX_P0 AY22 AJ36 V45 R35

DMI_CTX_PRX_P1 AP20 DMI_RXP_0 FDI_RXP_0 VGA_RED DDPC_CTRLCLK
(4) DMI_CTX_PRX_P1 DMI_RXP_1 AL36 M43 R36
DMI_CTX_PRX_P2 AR17 FDI_RXP_1 VGA_DDC_CLK DDPC_CTRLDATA
(4) DMI_CTX_PRX_P2 DMI_RXP_2
(4) DMI_CTX_PRX_P3 DMI_CTX_PRX_P3 AW20 AV43 M45 N40

CRT
DMI_RXP_3 TP16 VGA_DDC_DATA DDPD_CTRLCLK
D D
DMI_CRX_PTX_N0 BD21 AY45 N42 N38
(4) DMI_CRX_PTX_N0 DMI_TXN_0 TP5 VGA_HSYNC DDPD_CTRLDATA
DMI_CRX_PTX_N1 BE20
(4) DMI_CRX_PTX_N1 DMI_TXN_1 DMI FDI AV45 N44
DMI_CRX_PTX_N2 BD17 TP15 VGA_VSYNC H45
(4) DMI_CRX_PTX_N2 DMI_TXN_2 DDPB_AUXN
DMI_CRX_PTX_N3 BE18 AW44 U40

DISPLAY
(4) DMI_CRX_PTX_N3 DMI_TXN_3 TP10 DAC_IREF K43
DMI_CRX_PTX_P0 BB21 AL39 U39 DDPC_AUXN
(4) DMI_CRX_PTX_P0 DMI_TXP_0 FDI_CSYNC FDI_CSYMC (4) VGA_IRTN
DMI_CRX_PTX_P1 BC20 J42
(4) DMI_CRX_PTX_P1 DMI_TXP_1 DDPD_AUXN
AL40 FDI_INT (4)
DMI_CRX_PTX_P2 BB17 FDI_INT PCH_PWM N36 H43
(4) DMI_CRX_PTX_P2 DMI_TXP_2 (22) PCH_PWM EDP_BKLTCTL DDPB_AUXP
DMI_CRX_PTX_P3 BC18 AT45

LVDS
(4) DMI_CRX_PTX_P3 DMI_TXP_3 FDI_IREF +1.5VS
ENBKL K36 K45
(31) ENBKL EDP_BKLTEN DDPC_AUXP
+1.5VS BE16 AU42
DMI_IREF TP17 PCH_ENVDD G36 J44
(22) PCH_ENVDD EDP_VDDEN DDPD_AUXP
SUSACK# is only used on platform AW17
TP12 TP13
AU44
that support the Deep Sx state. K40
DDPB_HPD TMDS_B_HPD (18,24)
AV17 AR44 R148 1 2 7.5K_0402_1% PCI_PIRQA# H20
TP7 FDI_RCOMP PIRQA# K38
1 2 DMI_RCOMP AY17 L20 DDPC_HPD
+1.5VS R71
DMI_RCOMP
INTEL Recommend PCI_PIRQB#
PIRQB#
7.5K_0402_1% FDI_IREF and FDI_RCOMP can floating H39
PCI_PIRQC# K17 DDPD_HPD
PIRQC#
SUSWARN#_R 1 DS3@ 2 SUSACK#_R R6 C8 DSWODVREN PCI_PIRQD# M20
R150 0_0402_5% SUSACK# DSWVRMEN PIRQD# G17 PCH_GPIO2
SYS_RST# AM1 L13 PCH_DPWROK 1 NODS3@2 EC_RSMRST# DGPU_HOLD_RST# A12 PIRQE#/GPIO2
(18) SYS_RST# SYS_RESET# DPWROK (36,45) DGPU_HOLD_RST# GPIO50
2 R72 1 R172 0_0402_5% F17 GPU_EVENT#
PIRQF#/GPIO3 GPU_EVENT# (36)
100K_0402_1% @ SYS_PWROK AD7 K3 PCIE_WAKE# PCIE_WAKE# (18,28) PCH_GPIO52 B13 PCI
(31,5) SYS_PWROK SYS_PWROK WAKE# GPIO52 L15 GC6_FB_EN
PIRQG#/GPIO4 GC6_FB_EN (36,38)
PCH_PWROK F10 AN7 PM_CLKRUN# DGPU_PWR_EN C12
(31,9) PCH_PWROK PWROK CLKRUN# (31,45) DGPU_PWR_EN GPIO54
System Power M15 GPU_ALL_PGOOD
PIRQH#/GPIO5 GPU_ALL_PGOOD (45)
2 R73 1 10K_0402_5% AB7 Management U7 SUS_STAT# T21 BBS_BIT1 C10
APWROK SUS_STAT#/GPIO61 GPIO51 AD10
PM_DRAM_PWRGD H3 Y6 SUSCLK PCH_GPIO53 A10 PME#
(5) PM_DRAM_PWRGD DRAMPWROK SUSCLK/GPIO62 SUSCLK (28,31) * T23
GPIO53
PLTRST#
Y11 PCH_PLTRST#
EC_RSMRST# J2 Y7 PCH_GPIO55 AL6 1
(31) EC_RSMRST# RSMRST# SLP_S5#/GPIO63 PM_SLP_S5# (31) GPIO55
1 DS3@ 2 SUSWARN#_R J4 C6 C193
(31) SUSWARN# SUSWARN#/SUSPWRNACK/GPIO30 SLP_S4# PM_SLP_S4# (31)
C R151 0_0402_5% DH82HM86-SR17E-C2_FCBGA695 5 OF 11 100P_0402_50V8J C
PBTN_OUT# K1 H1 2
(31) PBTN_OUT# PWRBTN# SLP_S3# PM_SLP_S3# (31) @ESD@
D1
(31,48) ACIN
1 2 AC_PRESENT_R E6
ACPRESENT/GPIO31 SLP_A#
F3 SLP_A# T24 SLP_A# can be left NC when IAMT is
not support on the platfrom
RB751V-40_SOD323-2 PCH_GPIO72 K7 F1 SLP_SUS#
BATLOW#/GPIO72 SLP_SUS# SLP_SUS# (31,35)
RI# N4 AY3 H_PM_SYNC
(18) RI# RI# PMSYNCH H_PM_SYNC (5)
AB10
TP21 SLP_LAN#
G5 SLP_LAN# can be left NC if no use
integrated LAN.
D2
SLP_WLAN#/GPIO29

DH82HM86-SR17E-C2_FCBGA695 4 OF 11

+RTCVCC PCH_DPWROK 1 DS3@ 2 10K_0402_5% 1 @ 2 R147

DPWROK_EC (31) +3VS
ESD 9/5 R171 0_0402_5%
@ESD@ DSWODVREN R75 2 1 10K_0402_5% 1 DIS@ 2 R146 DGPU_HOLD_RST#
C189 2 1 100P_0402_50V8J SYS_PWROK 330K_0402_5%
R77 1 @ 2 V0.2
C190 2 1 100P_0402_50V8J EC_RSMRST# 330K_0402_5%

@ESD@ +3VS

DSWODVREN - On Die DSW VR Enable BBS_BIT1 2 R76 1 10K_0402_5%

+3VALW * H：Enable (DEFAULT)

L：Disable
R149 1 2 10K_0402_5% PCH_GPIO72

+3VS
Boot BIOS Strap (GPIO51)
B
APWROK can be connect to B
PWROK if iAMT disable RP4 SATA_SLPD
W_DISABLE#1 5 4 V0.2
(18,28) W_DISABLE#1
GATEA20 6 3
BBS_BIT1 (BBS_BIT0) Boot BIOS Location
(18,31) GATEA20
(18,31) KB_RST# KB_RST# 7 2
W_DISABLE#2 8 1
(18,28) W_DISABLE#2 0 0 LPC
SUSACK# and SUSWARN# can be tied together if 10K_0804_8P4R_5%
EC does not want to involve in the handshake 0 1 Reserved (NAND)
mechanism for the Deep Sleep state entry and exit.
+3VS
RP5
1 0 PCI
PCI_PIRQC# 8 1

+3V_PCH
Follow Intel schematic PCI_PIRQB# 7 2
1 1 * SPI
PCI_PIRQA# 6 3
review‐0930
R81
PCI_PIRQD# 5 4 GPIO51 needs pull up 10k to ensure proper behavior.
1 2 AC_PRESENT_R 8.2K_0804_8P4R_5%
200K_0402_5%
V0.2

+3VS
GPIO55 1 @ 2
R74 0_0402_5%
+3VS CLKRUN#: RP6 @ PCH_GPIO55 R79 1 @ 2 1K_0402_5%
External pull up to core well is required.
PCH_GPIO6 1 8
(18) PCH_GPIO6
1 R80 2 8.2K_0402_5% PM_CLKRUN# 2 7
3 6 A16 swap overide Strap/Top-Block +3VS
(18) PCH_GPIO1
PCH_GPIO1 4 5 Swap Override jumper
2 R82 1 10K_0402_5%
@ 10K_0804_8P4R_5% Low=A16 swap MC74VHC1G08DFT2G SC70 5P

5
override/Top-Block U3
PCI_GNT3# Swap Override enabled 2 PCH_PLTRST#

P
B
High=Default 4
+3VS * (25,28,31,34,36) PLT_RST# Y
A
1

G
RP7 @

3
+3V_PCH 1 8 +3VS
A 2 7 A
PCH_GPIO52 3 6
RP15 PCH_GPIO69 4 5 PCH_GPIO55 1 R83 2 10K_0402_5%
(18) PCH_GPIO69

2
R78
8 1 PCH_GPIO28 10K_0804_8P4R_5% 100K_0402_5%
PCH_GPIO28 (18)
7 2 SUSWARN#_R
6 3 DGPU_PWR_EN 10K_0402_5% 1 2 R113
5 4 PCH_GPIO24 PCH_GPIO2 10K_0402_5% 1 2 R117
PCH_GPIO24 (18)
GPU_ALL_PGOOD 10K_0402_5% 1 @ 2 R173
10K_0804_8P4R_5%
Follow Intel schematic Security Classification Compal Secret Data
review‐0930 Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

1 2 R154 EC_RSMRST#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (2/9) PCIE, SMBUS, CLK
10K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 14 of 59
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
+3VS

RP8 4 5 PCH_GPIO73
D 4 5 PCH_GPIO49 3 6 CLKREQ_CR# D
PCH_GPIO49 (18)
3 6 2 7 EC_SMI#
EC_SMI# (18,31)
2 7 PCH_GPIO18 1 8 PCH_GPIO46
1 8 CLKREQ_WLAN#
RP9
10K_0804_8P4R_5%
10K_0804_8P4R_5%

+3V_PCH
LPT_PCH_M_EDS
U2C
R132 1 2 10K_0402_5% PCH_GPIO45

Y43 AB35 CLK_PEG_VGA#

CLKOUT_PCIE_N_0 CLKOUT_PEG_A CLK_PEG_VGA# (36)
Y45 AB36 CLK_PEG_VGA
dGPU
CLKOUT_PCIE_P_0 CLKOUT_PEG_A_P CLK_PEG_VGA (36)
PCH_GPIO73 AB1 AF6 CLK_REQ_VGA# CLK_REQ_VGA# (36)
PCIECLKRQ0#/GPIO73 PEGA_CLKRQ#/GPIO47
AA44 Y39
AA42 CLKOUT_PCIE_N_1 CLKOUT_PEG_B
CLKOUT_PCIE_P_1 Y38 RP10
PCH_GPIO18 AF1 CLKOUT_PEG_B_P CLK_BUF_BCLK# 4 5
PCIECLKRQ1#/GPIO18 U4 PCH_GPIO56 CLK_BUF_BCLK 3 6
PEGB_CLKRQ#/GPIO56 PCH_GPIO56 (17)
CLK_PCIE_WLAN1# AB43 CLK_BUF_DMI 2 7
(28) CLK_PCIE_WLAN1# CLKOUT_PCIE_N_2 AF39 CLK_CPU_DMI# CLK_BUF_DMI# 1 8
CLKOUT_DMI CLK_CPU_DMI# (5)
CLK_PCIE_WLAN1 AB45
(28) CLK_PCIE_WLAN1 CLKOUT_PCIE_P_2
WLAN AF40 CLK_CPU_DMI
CLKOUT_DMI_P CLK_CPU_DMI (5)
(28) CLKREQ_WLAN# CLKREQ_WLAN# AF3 10K_0804_8P4R_5%
PCIECLKRQ2#/GPIO20/SMI# AJ40 CLK_CPU_SSC_DPLL#
CLKOUT_DP CLK_CPU_SSC_DPLL# (5)
C CLK_PCIE_LAN# AD43 AJ39 CLK_CPU_SSC_DPLL CLK_BUF_DOT96# R85 2 1 10K_0402_5% C
(25) CLK_PCIE_LAN# CLKOUT_PCIE_N_3 CLKOUT_DP_P CLK_CPU_SSC_DPLL (5)
CLK_PCIE_LAN AD45 CLK_BUF_DOT96 R86 2 1 10K_0402_5%
(25) CLK_PCIE_LAN CLKOUT_PCIE_P_3
LAN CLKREQ_LAN# T3 AF35 CLK_CPU_DPLL#
(18,25) CLKREQ_LAN# PCIECLKRQ3#/GPIO25 CLKOUT_DPNS CLK_CPU_DPLL# (5)
AF36 CLK_CPU_DPLL RP11
CLKOUT_DPNS_P CLK_CPU_DPLL (5)
AF43 CLK_BUF_CKSSCD# 4 5
AF45 CLKOUT_PCIE_N_4 AY24 CLK_BUF_DMI# CLK_BUF_CKSSCD 3 6
PCH_GPIO26 V3 CLKOUT_PCIE_P_4 CLKIN_DMI AW24 CLK_BUF_DMI 2 7
(17) PCH_GPIO26 PCIECLKRQ4#/GPIO26 CLKIN_DMI_P
CLOCK SIGNAL 1 8
CLK_PCIE_CR# AE44 AR24 CLK_BUF_BCLK#
(34) CLK_PCIE_CR# CLKOUT_PCIE_N5 CLKIN_GND
CR CLK_PCIE_CR AE42 AT24 CLK_BUF_BCLK
(34) CLK_PCIE_CR CLKOUT_PCIE_P_5 CLKIN_GND_P
CLKREQ_CR# AA2 10K_0804_8P4R_5%
(34) CLKREQ_CR# PCIECLKRQ5#/GPIO44 H33 CLK_BUF_DOT96#
AB40 CLKIN_DOT96N G33 CLK_BUF_DOT96
AB39 CLKOUT_PCIE_N_6 CLKIN_DOT96P
PCH_GPIO45 AE4 CLKOUT_PCIE_P_6 BE6 CLK_BUF_CKSSCD#
PCIECLKRQ6#/GPIO45 CLKIN_SATA BC6 CLK_BUF_CKSSCD
AJ44 CLKIN_SATA_P
CLKOUT_PCIE_N_7 F45 CLK_PCH_14M
AJ42 REFCLK14IN D17 CLK_PCI_LPBACK
CLKOUT_PCIE_P_7 CLKIN_33MHZLOOPBACK
PCH_GPIO46 Y3 AM43 XTAL25_IN CLK_PCH_14M R89 2 1 10K_0402_5%
PCIECLKRQ7#/GPIO46 XTAL25_IN AL44 XTAL25_OUT
AH43 XTAL25_OUT
CLKOUT_ITPXDP
EMI CLKOUTFLEX0/GPIO64
C40
AH45
CLKOUT_ITPXDP_P F38
CLK_PCI_LPBACK 22_0402_5% 1 EMI@ 2 R90 CLK_PCI_LPBACK_R D44 CLKOUTFLEX1/GPIO65
CLKOUT_33MHZ0 F36
22_0402_5% 1 EMI@ 2 R91 CLK_PCI_EC_R E44 CLKOUTFLEX2/GPIO66
(31) CLK_PCI_EC CLKOUT_33MHZ1 F39 PCH_GPIO67
CLKOUTFLEX3/GPIO67 PCH_GPIO67 (18)
B42
CLKOUT_33MHZ2 AM45
B F41 ICLK_IREF +1.5VS CLOCK TERMINATION for FCIM and need close to PCH B
CLKOUT_33MHZ3 AD39
A40 TP19 AD38
CLKOUT_33MHZ4 TP18 Green CLK
AN44 PCH_CLK_BIASREF 1 R93 2 +1.5VS
DIFFCLK_BIASREF 7.5K_0402_1%
XTAL25_IN R156 1 GCLK@ 2 0_0402_5% CLK_25M_PCH_XIN (27)
DH82HM86-SR17E-C2_FCBGA695 2 OF 11

XTAL25_IN
NOGCLK@
XTAL25_OUT 1 2
R94 1M_0402_5%

3 4
OSC NC
2 1
NC OSC
Y2
1 25MHZ_10PF_7V25000014 1
C121 NOGCLK@ C122
12P_0402_50V8J 12P_0402_50V8J
NOGCLK@ NOGCLK@
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (3/9) DMI,FDI,PM,
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 15 of 59
5 4 3 2 1
 5 4 3 2 1

LPT_PCH_M_EDS
U2D

+3VS
N7 PCH_GPI011 +3VS
D A20 SMBALERT#/GPIO11 D
(31) LPC_AD0 LAD_0
SMBus R10 PCH_SMBCLK
SMBCLK

1
(31) LPC_AD1 C20
LAD_1 U11 PCH_SMBDATA R99 R100
A18 SMBDATA
(31) LPC_AD2

LPC
LAD_2 N8 PCH_GPIO60 2.2K_0402_5% 2.2K_0402_5%
C18 SML0ALERT#/GPIO60
(31) LPC_AD3 LAD_3

2
2
U8 PCH_SML0CLK
B21 SML0CLK
(31) LPC_FRAME# LFRAME# R7 PCH_SML0DATA PCH_SMBCLK 6 1 SMB_CLK_S3
+3VS D21
LDRQ0#
SML0DATA Q2A 2N7002KDWH_SOT363-6
SMB_CLK_S3 (11,12,32) DIMM1

5
H6 PCH_GPI074
R98 2 1 10K_0402_5% G20
LDRQ1#/GPIO23
SML1ALERT#/PCHHOT#/GPIO74 DIMM2
K6 SML1CLK PCH_SMBDATA 3 4 SMB_DATA_S3
SML1CLK/GPIO58 SMB_DATA_S3 (11,12,32)Click Pad
SERIRQ AL11
(31) SERIRQ SERIRQ N11 SML1DATA Q2B 2N7002KDWH_SOT363-6
SML1DATA/GPIO75

AF11 +3VS
SPI_CLK_PCH_R AJ11 CL_CLK
SPI_CLK AF10
SPI_SB_CS0# AJ7 C-Link CL_DATA
SPI_CS0# AF7
AL7 CL_RST#
SPI_CS1#

5
AJ10
SPI_CS2# BA45

SPI
SPI_SI AH1 TP1 SML1CLK 3 4 EC_SMB_CK2
SPI_MOSI EC_SMB_CK2 (31,32,36)
BC45
Thermal TP2

2
SPI_SO_R AH3 Q3B 2N7002KDWH_SOT363-6
SPI_MISO
TP4
BE43 EC
SPI_IO2 AJ4 SML1DATA 6 1 EC_SMB_DA2
SPI_IO2 EC_SMB_DA2 (31,32,36)
C BE44 Q3A 2N7002KDWH_SOT363-6 C
SPI_IO3 AJ2 TP3
SPI_IO3 AY43 PCH_TD_IREF 1 2
TD_IREF R101 8.2K_0402_1%

DH82HM86-SR17E-C2_FCBGA695 3 OF 11
PCH_SMBCLK R162 1 @ 2 0_0402_5% SMB_CLK_S3

PCH_SMBDATA R160 1 @ 2 0_0402_5% SMB_DATA_S3

SML1CLK R161 1 @ 2 0_0402_5% EC_SMB_CK2

+3V_PCH
SML1DATA R159 1 @ 2 0_0402_5% EC_SMB_DA2
+3V_PCH

2
C125
R102
1 2
1K_0402_5%
+3V_PCH U4 0.1U_0402_16V7K

1
SPI_SB_CS0# 15_0402_5% 1 8
R106 SPI_SO_R R1041 2 SPI_SO_L 2 CS# VCC 7 SPI_IO3_2 R105 1 2 15_0402_5% SPI_IO3
1 2 SPI_IO2 R1071 2 SPI_IO2_2 3 SO
WP#
HOLD#
SCLK
6 SPI_CLK_PCH R108 1 2 15_0402_5% SPI_CLK_PCH_R Follow Intel schematic
1K_0402_5% 15_0402_5% 4 5 SPI_SI_R R109 1 2 15_0402_5% SPI_SI
GND SI
64M W25Q64FVSSIQ SOIC 8P
review‐0930 +3V_PCH

SA000039A30 PCH_SMBDATA R170 2 1 1K_0402_5%

PCH_SMBCLK R168 2 1 1K_0402_5%
SML1CLK R169 2 1 1K_0402_5%
SML1DATA R167 2 1 1K_0402_5%
B B
SPI_CLK_PCH SPI_CLK_PCH (31) PCH_SML0CLK R163 2 1 1K_0402_5%
SPI_CLK_PCH SPI_SI_R SPI_SI_R (31) PCH_SML0DATA R164 2 1 1K_0402_5%
SPI_SO_L
SPI_SB_CS0#
SPI_SO_L (31) EC/BIOS Share ROM
SPI_SB_CS0# (31)
1

R103
33_0402_5%
@EMI@
2

C126 +3VS
22P_0402_50V8J
@EMI@ (14,24) HDMICLK_NB HDMICLK_NB R165 2 1 2.2K_0402_5%
(14,24) HDMIDAT_NB HDMIDAT_NB R166 2 1 2.2K_0402_5%

R237;c120 close
to U4 pin
EMI +3V_PCH

PCH_GPI011 R95 1 2 10K_0402_5%

PCH_GPI074 R96 1 2 10K_0402_5%

PCH_GPIO60 R97 2 1 1K_0402_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (4/9) LVDS,CRT,DP,HDMI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 16 of 59
5 4 3 2 1
 5 4 3 2 1

D D

U2I LPT_PCH_M_EDS
USB DEBUG=PORT1 AND PORT9
(23) USB3_RX3_N USB3_RX3_N AW31 B37 USB20_N0
PERN1/USB3RN3 USB2N0 USB20_N0 (30)
(23) USB3_RX3_P USB3_RX3_P AY31 D37 USB20_P0 Left USB
PERP1/USB3RP3 USB2P0 USB20_P0 (30)
3D Camera A38 USB20_N1 (USB 3.0)
USB2N1 USB20_N1 (30)
USB3_TX3_N BE32 C38 USB20_P1 Left USB
(23) USB3_TX3_N PETN1/USB3TN3 USB2P1 USB20_P1 (30)
USB3_TX3_P BC32 A36
(23) USB3_TX3_P PETP1/USB3TP3 USB2N2 C36
PCIE_PRX_DTX_N2 AT31 USB2P2 A34
(28) PCIE_PRX_DTX_N2 PERN2/USB3RN4 USB2N3
(28) PCIE_PRX_DTX_P2 PCIE_PRX_DTX_P2 AR31 C34
PERP2/USB3RP4 USB2P3 B33 USB20_N4
WLAN USB2N4 USB20_N4 (34) EHCI1
C131 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N2 BD33 D33 USB20_P4 Right USB/B (USB 2.0)
(28) PCIE_PTX_C_DRX_N2 PETN2/USB3TN4 USB2P4 USB20_P4 (34)
C132 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P2 BB33 F31
(28) PCIE_PTX_C_DRX_P2 PETP2/USB3TP4 USB2N5 G31
USB2P5 K31
PCIE_PRX_DTX_N3 AW33 USB2N6 L31
(25) PCIE_PRX_DTX_N3 PERN_3 USB2P6
(25) PCIE_PRX_DTX_P3 PCIE_PRX_DTX_P3 AY33 G29
PERP_3 USB2N7 H29
LAN USB2P7
C127 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_N3 BE34 A32 USB20_N8
(25) PCIE_PTX_C_DRX_N3 PETN_3 USB2N8 USB20_N8 (22)
C128 1 2 0.1U_0402_16V7K PCIE_PTX_DRX_P3 BC34 C32 USB20_P8 Touch panel
(25) PCIE_PTX_C_DRX_P3 PETP_3 USB2P8 USB20_P8 (22)
A30 USB20_N9
USB2N9 USB20_N9 (22)
AT33 C30 USB20_P9 USB Camera
PERN_4 USB2P9 USB20_P9 (22)
AR33 B29 USB20_N10
PERP_4 USB2N10 USB20_N10 (28)
D29 USB20_P10 BT
USB2P10 USB20_P10 (28)
BE36 A28
BC36 PETN_4 USB2N11 C28
PETP_4 USB2P11
USB2N12
G26 EHCI2
PCIE_PRX_DTX_N5 AW36 F26

PCIe

USB
(34) PCIE_PRX_DTX_N5 PERN_5 USB2P12
(34) PCIE_PRX_DTX_P5 PCIE_PRX_DTX_P5 AV36 F24
C PERP_5 USB2N13 G24 C
Card Reader USB2P13
C129 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N5 BD37
(34) PCIE_PTX_C_DRX_N5 PETN_5
C130 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P5 BB37
(34) PCIE_PTX_C_DRX_P5 PETP_5 AR26 USB3_RX1_N USB3_RX1_N (30)
AY38 USB3RN1 AP26 USB3_RX1_P
PERN_6 USB3RP1 USB3_RX1_P (30)
AW38 BE24 USB3_TX1_N Left USB
PERP_6 USB3TN1 USB3_TX1_N (30)
BD23 USB3_TX1_P
USB3TP1 USB3_TX1_P (30)
BC38 AW26 USB3_RX2_N USB3_RX2_N (30)
BE38 PETN_6 USB3RN2 AV26 USB3_RX2_P
PETP_6 USB3RP2 BD25 USB3_TX2_N
USB3_RX2_P (30) Left USB
USB3TN2 USB3_TX2_N (30)
AT40 BC24 USB3_TX2_P
PERN_7 USB3TP2 USB3_TX2_P (30)
AT39 AW29
PERP_7 USB3RN5 AV29
BE40 USB3RP5 BE26 HM86 NA
BC40 PETN_7 USB3TN5 BC26
PETP_7 USB3TP5 AR29
AN38 USB3RN6 AP29 HM86 NA
AN39 PERN_8 USB3RP6 BD27
PERP_8 USB3TN6 BE28
BD42 USB3TP6
PETN_8 CAD NOTE:
BD41 K24 USBRBIAS 1 R110 2
PETP_8 USBRBIAS# K26 22.6_0402_1% Route single‐end 50‐ohms and max 500‐mils length.
USBRBIAS Avoid routing next to clock pins or under stitching capacitors. 
+1.5VS BE30 M33 Recommended minimum spacing to other signal traces is 15 mils.
PCIE_IREF TP24 L33
TP23
BC30 P3 USB_OC0#
TP11 OC0#/GPIO59 USB_OC0# (18,30)
V1 USB_OC#
OC1#/GPIO40 U2 USB_OC2#
OC2#/GPIO41 USB_OC2# (34)
BB29 P1 USB_OC#
TP6 OC3#/GPIO42 M3 USB_OC#
OC4#/GPIO43 T1 USB_OC#
B 1 2 PCH_PCIE_RCOMP BD29 OC5#/GPIO9 N2 USB_OC# B
+1.5VS PCIE_RCOMP OC6#/GPIO10
R111 7.5K_0402_1% M1 USB_OC#
OC7#/GPIO14

DH82HM86-SR17E-C2_FCBGA695 9 OF 11

+3V_PCH

RP14
PCH_GPIO56 4 5
(15) PCH_GPIO56
USB_OC2# 3 6
USB_OC# 2 7
PCH_GPIO26 1 8
(15) PCH_GPIO26
10K_0804_8P4R_5%

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (5/9) PCI, USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 17 of 59
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
Weak internal pull-high
RP17
4 5 CLKREQ_LAN#
CLKREQ_LAN# (15,25)
3 6 USB_OC0# V0.2
USB_OC0# (17,30)
2 7 RI# R175 1 2 0_0402_5%
RI# (14) (14,24) TMDS_B_HPD
1 8 PCIE_WAKE# U2F LPT_PCH_M_EDS
D PCIE_WAKE# (14,28) D
10K_0804_8P4R_5% +3VS R112 1 @ 2 10K_0402_5% HDMI_HPD_R AT8
BMBUSY#/GPIO0
PCH_GPIO1 F13
(14) PCH_GPIO1 TACH1/GPIO1
PCH_GPIO6 A14
(14) PCH_GPIO6 TACH2/GPIO6
+3V_PCH EC_SCI# G15 CPU/Misc
(31) EC_SCI# TACH3/GPIO7
(15,31) EC_SMI# EC_SMI# Y1
GPIO8 +1.05VS
1 R114@ 2 10K_0402_5% PCH_GPIO12 K13 Broadwell/Haswell
+3V_PCH LAN_PHY_PWR_CTRL/GPIO12
R115 2 1 10K_0402_5% PCH_GPIO57 AN10
TP14 GATEA20 (14,31)
1 R116 2 1K_0402_5% EC_LID_OUT# AB11
GPIO15

2
AY1
(31) EC_LID_OUT# PECI
PCH_GPIO16 AN2 R119 BW@
SATA4GP/GPIO16 AT6 KB_RST#
GPIO RCIN# KB_RST# (14,31) 1K_0402_5%
DGPU_PWROK C14
(36,45,54) DGPU_PWROK TACH0/GPIO17 AV3
PROCPWRGD H_CPUPWRGD (5)

1
W_DISABLE#2 BB4
(14,28) W_DISABLE#2 SCLOCK/GPIO22 AV1 H_THRMTRIP#_R 1 2 H_THRMTRIP# (45,5)
PCH_GPIO24 Y10 THRMTRIP# R157 390_0402_5%
(14) PCH_GPIO24 GPIO24 AU4 CPU_PLTRST# HW@
PLTRST_PROC# CPU_PLTRST# (5)
* PCH_GPIO27 (Have internal Pull-High) PCH_GPIO27 R11
GPIO27 N10
High: VCCVRM VR Enable PCH_GPIO28 AD11 VSS
(14) PCH_GPIO28 GPIO28 1
Low: VCCVRM VR Disable
W_DISABLE#1 AN6 C186 R157
(14,28) W_DISABLE#1 GPIO34
1000P_0402_50V7K
+3VALW PCH_GPIO35 AP1 2
(13) PCH_GPIO35 GPIO35/NMI# @ESD@
BW@
R121 1 2 10K_0402_5% PCH_GPIO27 TS_ON AT3
C (22) TS_ON SATA2GP/GPIO36 ESD 9/5 C
PCH_GPIO37 AK1 0_0402_5%
SATA3GP/GPIO37 SD028000080
CMOS_ON# AT7
(22,23) CMOS_ON# SLOAD/GPIO38
PCH_GPIO39 AM3 A2
SDATAOUT0/GPIO39 VSS A41
+3VS +3VS PCH_GPIO48 AN4 VSS A43
SDATAOUT1/GPIO48 VSS A44
PCH_GPIO49 AK3 VSS B1
(15) PCH_GPIO49 SATA5GP/GPIO49 VSS
1

R122 B2
1 2 TS_ON PCH_GPIO57 U12 VSS B44
200K_0402_5% R123 10K_0402_5% GPIO57 VSS B45
@ 1 2 PCH_GPIO68 PCH_GPIO68 C16 VSS BA1
R125 10K_0402_5% TACH4/GPIO68 VSS BC1
VSS
2

PCH_GPIO37 PCH_GPIO69 D13 BD1

(14) PCH_GPIO69 TACH5/GPIO69 VSS
1 @ 2 DGPU_PWROK BD2
VSS
1

R158 10K_0402_5% FW_UPDTA1 G13 BD44

(23) FW_UPDTA1 FW_UPDATE TACH6/GPIO70 VSS BD45
R124 PCH_GPIO71 H15 VSS BE2
10K_0402_5% TACH7/GPIO71 VSS BE3
VSS D1
VSS
2

PCH_GPIO68 Reserve for BIOS BE41

VSS NCTF VSS
E1
BE5 E45
VSS VSS
1

C45 A4
A5 VSS VSS
@ R128 VSS
10K_0402_5%
DH82HM86-SR17E-C2_FCBGA695 6 OF 11
2

B B

+3VS

R127 1 2 10K_0402_5% CMOS_ON# +3VS

RP18
R126 1 2 10K_0402_5% PCH_GPIO67 PCH_GPIO67 (15) 4 5 PCH_GPIO16
3 6 PCH_GPIO48
R130 1 2 10K_0402_5% PCH_GPIO71 2 7 SYS_RST# SYS_RST# (14)
1 8 PCH_GPIO39
R131 1 2 10K_0402_5% FW_UPDTA1
10K_0804_8P4R_5%

A A

Security Classification Compal Secret Data

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (6/9) GPIO, CPU, MISC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 18 of 59
5 4 3 2 1
 5 4 3 2 1

D D

PCH Power Rail Table
U2G LPT_PCH_M_EDS

+1.05VS P45 Voltage Rail Voltage S0 Iccmax Current (A)

VCCADAC1_5 +1.5VS
AA24 P43
AA26 VCC CRT DAC VSS
VCC VCC 1.05V 1.29 A
AD20 M31
10U_0603_6.3V6M

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 VCC VCCADACBG3_3
AD22 +1.05VS
C133

C136

C134

C135
AD24 VCC

10U_0603_6.3V6M
VCC 1 VCCIO 1.05V 3.629 A
AD26 BB44

C137
2 2 2 2 AD28 VCC VCCVRM

1U_0402_6.3V6K
VCC FDI 1
AE18 AN34

C138
VCC VCCIO +3VS 2
VCCADAC1_5 1.5V 0.070 A
AE20 @
AE22 VCC AN35
AE24 VCC VCCIO 2
VCC VCCADAC3_3 3.3V 0.0133 A
AE26 R30
AG18 VCC HVCMOS VCC3_3_R30 R32
AG20 VCC VCC3_3_R32

0.1U_0402_16V7K
VCC 1 VCCCLK 1.05V 0.306 A
AG22 Y12 +PCH_USB_DCPSUS1 +3V_PCH
AG24 VCC DCPSUS1

0.1U_0402_16V7K

C139
Y26 VCC AJ30
VCC VCCSUS3_3 2
VCCCLK3_3 3.3V 0.055 A
C AJ32 C

Core
VCCSUS3_3 1
+1.05VS AJ26 +PCH_USB_DCPSUS3 +1.5VS

C140
USB3 DCPSUS3 VCCVRM 1.5V 0.179 A
+PCH_VCCDSW U14 AJ28
AA18 DCPSUSBYP DCPSUS3 AK20 2
VCCASW VCCIO +1.05VS
U18 AK26 VCC3_3 3.3V 0.133 A
U20 VCCASW VCCVRM AK28 +1.5VS
U22 VCCASW VCCVRM
22U_0805_6.3V6M
C141

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 VCCASW
U24 BE22
C142

C143

VCCASW VCCVRM VCCASW 1.05V 0.67 A

V18 PCIe/DMI
V20 VCCASW AK18 +1.5VS
2 2 2 VCCASW VCCIO +1.05VS
V22 VCCSUSHDA 3.3V 0.01 A
V24 VCCASW AN11
Y18 VCCASW VCCVRM
Y20 VCCASW SATA
AK22
VCCASW VCCIO VCCSPI 3.3V 0.022 A
Y22 +1.05VS
VCCASW AM18
VCCIO AM20
VCCIO VCCSUS3_3 3.3V 0.261 A
AM22
VCCMPHY VCCIO AP22
VCCIO AR22

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M
VCCIO 1 1 1 1 1 VCCDSW3_3 3.3V 0.015 A
AT22

C144

C145

C146

C147

C148
VCCIO

2 2 2 2 2
V_PROC_IO 1.05V 0.004 A
DH82HM86-SR17E-C2_FCBGA695 7 OF 11

1 2 +PCH_VCCDSW
R134 5.1_0402_1% +1.05VS
+PCH_VCCDSW_R

B B
+PCH_USB_DCPSUS1 1 R136 2
0_0402_5%
@

10U_0603_6.3V6M
1

C149
2 @
1U_0402_6.3V6K

1
C150

+1.05VS
2
+PCH_USB_DCPSUS3 2 R137 1
0_0603_5%
@

10U_0603_6.3V6M

10U_0603_6.3V6M
1 1

C151

C152
2 @ 2 @

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (7/9) PWR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 19 of 59
5 4 3 2 1
 5 4 3 2 1

+3V_PCH
+PCH_VCCDSW3_3

1 2

0.1U_0402_16V7K
LPT_PCH_M_EDS +3VALW
U2H R138 0_0402_5%
1
D +3V_PCH D

C156

0.1U_0402_16V7K
1
R24 R20
R26 VCCSUS3_3 VCCSUS3_3 R22 2

C153
R28 VCCSUS3_3 VCCSUS3_3
+1.05VS U26 VCCSUS3_3 GPIO/LPC 2
0.1U_0402_16V7K

1 VCCSUS3_3 A16 +PCH_VCCDSW3_3

M24 VCCDSW3_3 C157 +3VS
C154

VSS AA14 +PCH_VCCSST 1 2 PCH Power Rail Table

2 +3VS U35 DCPSST
VCCUSBPLL AE14 0.1U_0402_16V7K
0.1U_0402_16V7K

USB
L24 VCC3_3 AF12
VCC3_3 VCC3_3 Voltage Rail Voltage S0 Iccmax Current (A)
AG14
C155

U30 VCC3_3 +3V_PCH

0.1U_0402_16V7K
2 VCCIO 1
+1.05VS V28
0.1U_0402_16V7K

1 VCCIO VCC 1.05V 1.29 A

V30 U36

C159
VCCIO VCCIO +1.05VS
Y30
C158

VCCIO +3V_PCH 2
2
VCCIO 1.05V 3.629 A
+1.5VS +PCH_USB_DCPSUS2 Y35 Azalia
DCPSUS2 A26
1U_0402_6.3V6K

0.1U_0402_16V7K
1 VCCSUSHDA 1
AF34
C160

VCCVRM VCCADAC1_5 1.5V 0.070 A

C161
+PCH_VCC AP45 K8 +RTCVCC

10U_0603_6.3V6M

1U_0402_6.3V6K
2 1 VCC VCCSUS3_3 1 2

C162

C163
VCCADAC3_3 3.3V 0.0133 A
+PCH_VCCCLK Y32 A6
VCCCLK VCCRTC
2 M29 RTC
P14 +PCH_DCPRTC C164 2
+PCH_VCCCLK3_3 VCCCLK3_3 DCPRTC VCCCLK 1.05V 0.306 A
P16 1 2

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K
DCPRTC 1 1 1
L29

C167
VCCCLK3_3 0.1U_0402_16V7K

C165

C166
VCCCLK3_3 3.3V 0.055 A
L26 AJ12 +PCH_VPROC
M26 VCCCLK3_3 V_PROC_IO AJ14 +3V_PCH 2 2 2
CPU
C +1.05VS VCCCLK3_3 V_PROC_IO C
VCCVRM 1.5V 0.179 A
U32
1 R139 2 +PCH_USB_DCPSUS2 V32 VCCCLK3_3 AD12

ICC
0_0402_5% VCCCLK3_3 SPI VCCSPI
VCC3_3 3.3V 0.133 A
@ AD34

1U_0402_6.3V6K
+PCH_VCCCLK VCCCLK 1
P18 +PCH_VCCCFUSE
1U_0402_6.3V6K

C169
1 VCC
AA30 P20
C168

VCCCLK VCC VCCASW 1.05V 0.67 A

AA32
VCCCLK L17 2
2 VCCASW +1.05VS
@ AD35 VCCSUSHDA 3.3V 0.01 A
VCCCLK R18
AG30 VCCASW
AG32 VCCCLK 01/02 EC/BIOS share ROM VCCSPI 3.3V 0.022 A
VCCCLK AW40
+PCH_VCC VCCVRM +1.5VS
AD36
+1.05VS VCCCLK AK30 +3VS
VCC3_3 VCCSUS3_3 3.3V 0.261 A
L1 AE30 Thermal
1 2 +PCH_VCC AE32 VCCCLK AK32
4.7UH_NRS2012T4R7MGJ_20% VCCCLK VCC3_3
VCCDSW3_3 3.3V 0.015 A

0.1U_0402_16V7K
1
10U_0603_6.3V6M

1U_0402_6.3V6K

1 1
DH82HM86-SR17E-C2_FCBGA695 8 OF 11
C170

C171

C172
V_PROC_IO 1.05V 0.004 A
2
2 2

Place near pin AP45
Broadwell

+PCH_VPROC +1.05VS
B B
+1.05VS +PCH_VCCCLK +PCH_VPROC R140 2 1 0_0603_5%

1 2
R141 0_0603_5%

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K
1 1 1

C173

C174

C175
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
1 1 1 1 1 2 2 2
C176

C177

C178

C179

C180
2 2 2 2 2

Place near pin Y32,AA30,AA32 Place near pin AD34 Place near pin AD35,AD36 INTEL Recommend follow 486714 DG

Place near pin AG30,AG32,AE30,AE32 Different with COMPAL

0_0805_5%
+3VS +PCH_VCCCLK3_3 +PCH_VCCCFUSE R142 1 2 +1.05VS

1 2 0_0805_5%

1U_0402_6.3V6K
1
R143 0_0603_5% R144 1 2

C181
+3VS
@
2
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1
C182

C183

C184

C185

2 2 2 2
A A

Place near pin M29 Place near pin L29 Place near pin L26,M26 Place near pin U32,V32

Security Classification Compal Secret Data

2013/01/22 2014/01/22
Issued Date Deciphered Date Title
PCH (8/9) PWR
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 20 of 59
5 4 3 2 1
 5 4 3 2 1

D D

U2J LPT_PCH_M_EDS

AL34 K39 U2K LPT_PCH_M_EDS

AL38 VSS VSS L2
AL8 VSS VSS L44 AA16 B19
AM14 VSS VSS M17 AA20 VSS VSS B23
AM24 VSS VSS M22 AA22 VSS VSS B27
AM26 VSS VSS N12 AA28 VSS VSS B31
AM28 VSS VSS N35 AA4 VSS VSS B35
AM30 VSS VSS N39 AB12 VSS VSS B39
AM32 VSS VSS N6 AB34 VSS VSS B7
AM16 VSS VSS P22 AB38 VSS VSS BA40
AN36 VSS VSS P24 AB8 VSS VSS BD11
AN40 VSS VSS P26 AC2 VSS VSS BD15
AN42 VSS VSS P28 AC44 VSS VSS BD19
C AN8 VSS VSS P30 AD14 VSS VSS AY36 C
AP13 VSS VSS P32 AD16 VSS VSS AT43
AP24 VSS VSS R12 AD18 VSS VSS BD31
AP31 VSS VSS R14 AD30 VSS VSS BD35
AP43 VSS VSS R16 AD32 VSS VSS BD39
AR2 VSS VSS R2 AD40 VSS VSS BD7
AK16 VSS VSS R34 AD6 VSS VSS D25
AT10 VSS VSS R38 AD8 VSS VSS AV7
AT15 VSS VSS R44 AE16 VSS VSS F15
AT17 VSS VSS R8 AE28 VSS VSS F20
AT20 VSS VSS T43 AF38 VSS VSS F29
AT26 VSS VSS U10 AF8 VSS VSS F33
AT29 VSS VSS U16 AG16 VSS VSS BC16
AT36 VSS VSS U28 AG2 VSS VSS D4
AT38 VSS VSS U34 AG26 VSS VSS G2
D42 VSS VSS U38 AG28 VSS VSS G38
AV13 VSS VSS U42 AG44 VSS VSS G44
AV22 VSS VSS U6 AJ16 VSS VSS G8
AV24 VSS VSS V14 AJ18 VSS VSS H10
AV31 VSS VSS V16 AJ20 VSS VSS H13
AV33 VSS VSS V26 AJ22 VSS VSS H17
BB25 VSS VSS V43 AJ24 VSS VSS H22
AV40 VSS VSS W2 AJ34 VSS VSS H24
AV6 VSS VSS W44 AJ38 VSS VSS H26
AW2 VSS VSS Y14 AJ6 VSS VSS H31
F43 VSS VSS Y16 AJ8 VSS VSS H36
AY10 VSS VSS Y24 AK14 VSS VSS H40
AY15 VSS VSS Y28 AK24 VSS VSS H7
AY20 VSS VSS Y34 AK43 VSS VSS K10
AY26 VSS VSS Y36 AK45 VSS VSS K15
AY29 VSS VSS Y40 AL12 VSS VSS K20
AY7 VSS VSS Y8 AL2 VSS VSS K29
B B11 VSS VSS BC22 VSS VSS K33 B
B15 VSS BB42 VSS VSS BC28
VSS VSS VSS

DH82HM86-SR17E-C2_FCBGA695 DH82HM86-SR17E-C2_FCBGA695
10 OF 11 11 OF 11

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCH (9/9) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 21 of 59
5 4 3 2 1
 A B C D E

CMOS Camera +3VS

1
(20 MIL)
Q14
+3VS_CMOS eDP Panel 1
PMV65XP_SOT23-3~D R201 2 EMI@ 1 0_0402_5%

3 1
0_0603_5%(20 MIL)
2 @ 1R204 10U L28
@EMI@ CAMERA

D
1 1 (17) USB20_N9 USB20_N9 3 4 USB20_N9_CONN

V1.0 C317 C318 @

DMIC

G
2
0.1U_0402_16V7K 10U_0603_6.3V6M (17) USB20_P9 USB20_P9 2 1 USB20_P9_CONN
2 2
DLW21HN900HQ2L_0805
R205
150K_0402_5% R206
SM070003Y00
2
EMI@
1 0_0402_5% TOUCH SCREEN
(18,23) CMOS_ON# R296 for CMOS shake issue reserve
1
C319
0.1U_0402_16V7K
2

2 JEDP1 CONN@ 2
LCD POWER CIRCUIT 200mA Camera USB20_N9_CONN
USB20_P9_CONN
1
3 1
2
2 4 EDP_CONN_LANE_N1
5 3 4 6 EDP_CONN_LANE_P1
DMIC_DATA 7 5 6 8
+LCDVDD (26) DMIC_DATA 7 8 10
W=80mils DMIC DMIC_CLK 9 EDP_CONN_LANE_N3
+3VS (26) DMIC_CLK 9 10 12
W=80mils U11 2A 11 EDP_CONN_LANE_P3
1 +LCDVDD USB20_N8 13 11 12 14
2A 5 OUT (17) USB20_N8
USB20_P8 15 13 14 16 EDP_CONN_LANE_N2
eDP
IN 250mA Touch PANEL (17) USB20_P8
17 15 16 18 EDP_CONN_LANE_P2
1 1 1 17 18 20
@ R202 2 C308 1 @ 2 TS_RST# 19
GND (18) TS_ON 19 20 22
C307 1 2 +3VS_SS 4 4.7U_0603_6.3V6K C309 R207 0_0402_5% EDP_HPD 21 EDP_CONN_LANE_N0
SS (7) EDP_HPD 21 22 24
0.1U_0402_16V7K 0_0402_5% 0.1U_0402_16V7K BKOFF# 23 EDP_CONN_LANE_P0
2 2 2 (31) BKOFF# 23 24 26
1 3 R238 1 2 PCH_PWM 25
EN (14) PCH_PWM 25 26 28
10K_0402_5% +3VS_CMOS +3VS_CMOS 27 EDP_CONN_AUX
C312 APL3512A_SOT23-5 29 27 28 30 EDP_CONN_AUX#
+3VS 29 30 32 INVPWR_B+
1500P_0402_50V7K +3VS_TOUCH 31
2 +3VS_TOUCH 31 32 34
+LCDVDD 33 1090mA R375
(14) PCH_ENVDD 33 34 36
35 1 2 CPU_B+
37 35 36 38 0_0805_5%
C312 Resevre for APL3512A 39 37 38 40
39 40 W=80mils
R202 Resevre for G5243AT11U

0.1U_0603_25V7K

0.1U_0603_25V7K
2 2
41 42

C315

C316
GND GND
ACES_87142-4041
SP02000ND10 1 1

3 3

EDP_CPU_LANE_N1 C301 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N1

(7) EDP_CPU_LANE_N1
EDP_CPU_LANE_P1 C302 1 2 0.1U_0402_16V7K EDP_CONN_LANE_P1
(7) EDP_CPU_LANE_P1
EDP_CPU_LANE_N0 C303 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N0
(7) EDP_CPU_LANE_N0
EDP_CPU_LANE_P0 C304 1 2 0.1U_0402_16V7K EDP_CONN_LANE_P0
(7) EDP_CPU_LANE_P0
EDP_CPU_AUX C305 1 2 0.1U_0402_16V7K EDP_CONN_AUX
(7) EDP_CPU_AUX
EDP_CPU_AUX# C306 1 2 0.1U_0402_16V7K EDP_CONN_AUX#
(7) EDP_CPU_AUX#
EDP_CPU_LANE_N2 C310 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N2
Touch Panel +3VS +3VS_TOUCH (7) EDP_CPU_LANE_N2
(7) EDP_CPU_LANE_P2
EDP_CPU_LANE_P2 C311 1 2 0.1U_0402_16V7K EDP_CONN_LANE_P2

JP11 JUMP_43X79 EDP_CPU_LANE_N3 C313 1 2 0.1U_0402_16V7K EDP_CONN_LANE_N3

(7) EDP_CPU_LANE_N3
EDP_CPU_LANE_P3 C314 1 2 0.1U_0402_16V7K EDP_CONN_LANE_P3
(7) EDP_CPU_LANE_P3
1 2
1 2
@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LCD Conn/Cam, Touch
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 22 of 59
A B C D E
 A B C D E

CMOS Camera +5VS

(20 MIL) +RE_PWR_1

+RE_PWR_1
Q20 CCD3@
CCD3@ U25 @
PMV65XP_SOT23-3~D C505 2 1 0.1U_0402_16V7K 1
1 0_0603_5%(20 MIL) 13 VDD 1
3 1 2 @ 1 R386 10U EQ31 2 VDD 17 EQ32

D
DE31 3 B_EQ0 A_EQ0 16 DE32
1 1 B_DE0 A_DE0
OS31 4 15 OS32
C510 C511 @ R551 1
@R551
@ 2 4.7K_0402_5% 5 B_EQ1 A_EQ1

G
2
0.1U_0402_16V7K 10U_0603_6.3V6M PD#
2 CCD3@ 2 C503 2 1 0.1U_0402_16V7K USB3_RX3_P_R 12 19 U3RXDP3
(17) USB3_RX3_P A_OUTp A_INp
C507 2 1 0.1U_0402_16V7K USB3_RX3_N_R 11 20 U3RXDN3
(17) USB3_RX3_N A_OUTn A_INn
(17) USB3_TX3_P C508 2 1 0.1U_0402_16V7K USB3_TX3_P_R 9 22 U3TXDP3_C C502 2 1 0.1U_0402_16V7K U3TXDP3
R559 CCD3@ C504 2 1 0.1U_0402_16V7K USB3_TX3_N_R 8 B_INp B_OUTp 23 U3TXDN3_C C506 2 1 0.1U_0402_16V7K U3TXDN3
(17) USB3_TX3_N B_INn B_OUTn
(18,22) CMOS_ON#
150K_0402_5% CCD3@ TEST3 7 14 1 @ R553 2
@R553
REXT TEST +RE_PWR_1
1 CCD3@ I2C_EN3 24 4.7K_0402_5% CCD3@
CCD3@ NC 18 A_DE31 CCD3@
C509 CCD3@ B_DE31 6 A_DE1 21
0.1U_0402_16V7K 10 B_DE1 GND 25
2 CCD3@ GND EAPD
PS8713BTQFN24GTR2-A0_TQFN24_4X4

+RE_PWR_1

2 2

B channel A channel

1
Parade @ @ @ @ @ @ @ @ @ @

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
Port3 (TX) Port3 (RX)

R390

R397

R389

R550

R555

R556

R552

R398

R395

R394
3.5 dB 2.7 dB

2
B_DE1 / B_DE0 A_DE1 / A_DE0
DE (L / L) (H / L) EQ31
B_DE31
Mount：NA Mount：R395 EQ32 A_DE31
DE31
DE32 I2C_EN3
9.5 dB 9.5 dB OS31
B_EQ1 / B_EQ0 A_EQ1 / A_EQ0
EQ (L / L) (L / L)
OS32 TEST3
Mount：NA Mount：NA
1

1
@ @ @ @ @ @ @ @ @
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%

3.83K_0402_1%

@
4.7K_0402_5%

4.7K_0402_5%

4.7K_0402_5%
6.2K Ohm
R400

R554

R399

R388

R396

R391

R557

R392

R393
R387
REXT
REXT Mount：R387
2

2
TI
B channel A channel for 3D Camera
Port3 (TX) Port3 (RX) +5VS

JCCD3
0 dB 0 dB

1
1
B_DE0 A_DE0 1
3
DE (NC) (NC) U25 TI@ U25 PD@
@
R558 U3TXDN3
U3TXDP3
2
3 2
3

Mount：NA Mount：NA 10K_0402_5% 3

4
U3RXDN3 5 4
5

2
U3RXDP3 6
7 dB 7 dB 7 6
B_EQ0 A_EQ0 7
EQ (L) (L) SN65LVPE502ARGER_VQFN24_4X4 PS8713BTQFN24GTR2-A1_TQFN24_4X4 (18) FW_UPDTA1
8
9 8
Mount：R240 Mount：R242 9
+RE_PWR_1 trace width : 20 mils +RE_PWR_1 10
R387 PD@ 11 10
R400 TI@ 12 GND
GND

Port3 R387 R400 R554 R395

6.2K_0402_1%
4.7K_0402_5%
PD@ 6.2K @ @ 4.7K
R395 PD@
R554 TI@

TI@ @ 4.7K 4.7K @

4.7K_0402_5% 4.7K_0402_5%

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3D Camera
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 23 of 59
A B C D E
 5 4 3 2 1

HDMI Connector +HDMI_5V_OUT

+3VS +5VS C320 @1

@ 2 2200P_0402_50V7K
Q9
W=40mils W=40mils C321 1 2 2200P_0402_50V7K
D 1 3 D

0.1U_0402_16V7K

GND
VIN VOUT

2200P_0402_50V7K

2200P_0402_50V7K
0.1U_0402_16V7K
2 1
R208

C323
1M_0402_5% Q6

C322
1 1

2
AP2330W-7_SC59

2.2K_0402_1%

2.2K_0402_1%

@C325
1 2

1
2N7002H_SOT23-3 @

C324
1
TMDS_B_HPD 3 1 2 2

R209

R210
(14,18) TMDS_B_HPD
Co-lay for EMI

2
L11 EMI@

2
HDMI_CLK+_CK 3 4 HDMI_CLK+_CONN JHDMI1 CONN@
3 4 R211 HDMI_DET 19
18 HP_DET
20K_0402_5% +5V
HDMI_CLK-_CK 2 1 HDMI_CLK-_CONN 17
2 1 HDMIDAT_CONN 16 DDC/CEC_GND
DLW21HN900HQ2L_4P SDA

1
HDMICLK_CONN 15
SCL
Co-lay for EMI 14
13 Reserved
DLW21HN900HQ2L_4P CEC
HDMI_TX0-_CK 2 1 HDMI_TX0-_CONN TMDS_B_CLK#_PCH 1 2 HDMI_CLK-_CK R212 1 @EMI@ 2 0_0402_5% HDMI_CLK-_CONN 12 20
2 1 (7) TMDS_B_CLK#_PCH CK- GND
C326 0.1U_0402_16V7K 11 21
TMDS_B_CLK_PCH 1 2 HDMI_CLK+_CK R213 1 @EMI@ 2 0_0402_5% HDMI_CLK+_CONN 10 CK_shield GND 22
(7) TMDS_B_CLK_PCH CK+ GND
HDMI_TX0+_CK 3 4 HDMI_TX0+_CONN TMDS_B_DATA0#_PCH C327 1 2 0.1U_0402_16V7K HDMI_TX0-_CK R214 1 @EMI@ 2 0_0402_5% HDMI_TX0-_CONN 9 23
3 4 (7) TMDS_B_DATA0#_PCH D0- GND
C328 0.1U_0402_16V7K 8
L12 EMI@ TMDS_B_DATA0_PCH 1 2 HDMI_TX0+_CK R215 1 @EMI@ 2 0_0402_5% HDMI_TX0+_CONN 7 D0_shield
(7) TMDS_B_DATA0_PCH D0+
TMDS_B_DATA1#_PCH C329 1 2 0.1U_0402_16V7K HDMI_TX1-_CK R216 1 @EMI@ 2 0_0402_5% HDMI_TX1-_CONN 6
(7) TMDS_B_DATA1#_PCH D1-
L13 EMI@ C330 0.1U_0402_16V7K 5
HDMI_TX1+_CK 3 4 HDMI_TX1+_CONN TMDS_B_DATA1_PCH 1 2 HDMI_TX1+_CK R217 1 @EMI@ 2 0_0402_5% HDMI_TX1+_CONN 4 D1_shield
3 4 (7) TMDS_B_DATA1_PCH D1+
TMDS_B_DATA2#_PCH C331 1 2 0.1U_0402_16V7K HDMI_TX2-_CK R218 1 @EMI@ 2 0_0402_5% HDMI_TX2-_CONN 3
(7) TMDS_B_DATA2#_PCH D2-
C332 0.1U_0402_16V7K 2
HDMI_TX1-_CK 2 1 HDMI_TX1-_CONN TMDS_B_DATA2_PCH 1 2 HDMI_TX2+_CK R219 1 @EMI@ 2 0_0402_5% HDMI_TX2+_CONN 1 D2_shield
2 1 (7) TMDS_B_DATA2_PCH D2+
C333 0.1U_0402_16V7K
DLW21HN900HQ2L_4P

@EMI@C334
C334

@EMI@C335
C335

@EMI@C336
C336

@EMI@C337
C337

@EMI@C338
C338

@EMI@C339
C339

@EMI@C340
C340

@EMI@C341
C341
C CONCR_099ATAC19NBLCNF C

2 2 2 2 2 2 2 2

@EMI@

@EMI@

@EMI@

@EMI@
@EMI@

@EMI@

@EMI@

@EMI@
DLW21HN900HQ2L_4P DC232001K00
HDMI_TX2-_CK 2 1 HDMI_TX2-_CONN
2 1

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
1 1 1 1 1 1 1 1
HDMI_TX2+_CK 3 4 HDMI_TX2+_CONN
3 4
L14 EMI@
+3VS
Pull up R for PCH OR VGA SIDE

EMI
2N7002KDWH_SOT363-6
Q15A

2
(14,16) HDMICLK_NB 1 6 HDMICLK_CONN

5
(14,16) HDMIDAT_NB 4 3 HDMIDAT_CONN

Q15B
2N7002KDWH_SOT363-6
HDMI_TX1+_CK R360 1 2 470_0402_5%
HDMI_TX1-_CK R357 1 2 470_0402_5%
HDMI_CLK+_CK R361 1 2 470_0402_5%
HDMI_CLK-_CK R356 1 2 470_0402_5%

B B

HDMI_TX0-_CK R355 1 2 470_0402_5%

HDMI_TX0+_CK R359 1 2 470_0402_5%
HDMI_TX2-_CK R354 1 2 470_0402_5%
HDMI_TX2+_CK R358 1 2 470_0402_5%
+3VS
D

1
2
G
D11 @ESD@ S Q5

3
+HDMI_5V_OUT 4 3 HDMICLK_CONN D12 @ESD@ D13 @ESD@ 2N7002H_SOT23-3
4 3 HDMI_CLK-_CONN 9 1 HDMI_CLK-_CONN HDMI_TX0-_CONN 9 1 HDMI_TX0-_CONN

HDMI_CLK+_CONN 8 2 HDMI_CLK+_CONN HDMI_TX0+_CONN 8 2 HDMI_TX0+_CONN

HDMI_TX1-_CONN 7 4 HDMI_TX1-_CONN HDMI_TX2-_CONN 7 4 HDMI_TX2-_CONN

HDMI_TX1+_CONN 6 5 HDMI_TX1+_CONN HDMI_TX2+_CONN 6 5 HDMI_TX2+_CONN

+5VS 5 2
Vbus GND
3 3

TVWDF1004AD0_DFN9 TVWDF1004AD0_DFN9

A HDMI_DET 6 1 HDMIDAT_CONN A
6 1
YSUSB2.0-5_SOT-23-6-6

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI LS & Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 24 of 59
5 4 3 2 1
 5 4 3 2 1

+3_LAN Rising time (10%~90%) >1mS and <100mS 

+3VALW +3V_LAN
W=60mils JP6 @
1 2
370mA
1 2
JUMP_43X39

Layout Notice : Place as close

D D
chip as possible.

LDO@ +3V_LAN
+3V_LAN +3V_LAN R220 1 2 0_0603_5%
W=60mils +LAN_VDD10
L15 SWR@
+LAN_REGOUT 1 2
W=60mils 2.2UH +-5% NLC252018T-2R2J-N
1

C346

0.1U_0402_16V7K
@

C350

0.1U_0402_16V7K

C351

0.1U_0402_16V7K

C352

0.1U_0402_16V7K

C353

0.1U_0402_16V7K

0.1U_0402_16V7K
C354

C355

0.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

2
@
C342

C343

1 2 1 1 1 1 1 1

1
C344 SWR@ C345 SWR@

C349

1U_0402_6.3V6K
2

4.7U_0603_6.3V6K 2 0.1U_0402_16V7K LDO@ C347 SWR@ SWR@

1
4.7U_0603_6.3V6K C348

2
2 1 0.1U_0402_16V7K 2 2 2 2 2 2

close to pin 22 +3V_LAN

close to U12 : Pin  11, 32 These caps close to U12 : Pin  23 ( Should be place within 200 mils ) These caps close to U12 : Pin 11,32
These components close to U12 : Pin 24 DVDD33
These components close to U12 : Pin 3,8,22,30 EC pin29 implement Internal PU
LDO mode SWR mode
1uF reserved on Pin 22
R221 1 2 10K_0402_5% LAN_WAKE#_R

U12

8106@
Green CLK U12 8111@

C
RTL8106EUS-CG C
SA00006N900
XTLI R362 1 GCLK@ 2 0_0402_5% CLK_25M_LAN_XIN (27)
These caps close to U11
MDI0+ 1 17 PCIE_PRX_C_DTX_P3 C357 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_P3
MDIP0 HSOP PCIE_PRX_DTX_P3 (17)
MDI0- 2 18 PCIE_PRX_C_DTX_N3 C358 1 2 0.1U_0402_16V7K PCIE_PRX_DTX_N3
MDIN0 HSON PCIE_PRX_DTX_N3 (17)
+LAN_VDD10 3 19
AVDD10 PERSTB PLT_RST# (14,28,31,34,36)
MDI1+ 4 20 ISOLATEB R222 1 2 1K_0402_5% +3VS
MDI1- 5 MDIP1 ISOLATEB 21 LAN_WAKE#_R R223 1 2 0_0402_5%
MDIN1 LANWAKEB LAN_WAKE# (31)
MDI2+ 6 22 +LAN_VDD10
MDI2- 7 MDIP2 DVDD10 23 +3V_LAN
C356 EMI@ +LAN_VDD10 8 MDIN2 VDDREG 24 +LAN_REGOUT
R372 AVDD10 REGOUT
15P_0402_50V8J MDI3+ 9 25 1
MDIP3 LED2 T36
1 2 1 2 XTLI MDI3- 10 26 to EC
MDIN3 LED1/GPIO LAN_PWRDN (31)
1 0_0402_5% +3V_LAN 11 27 1
AVDD33 LED0 T37
NOGCLK@ NOGCLK@ LAN_CLKREQ# 12 28 XTLO ISOLATEB
(15,18) CLKREQ_LAN# CLKREQB CKXTAL1
Y3 13 29 XTLI
1 (17) PCIE_PTX_C_DRX_P3 HSIP CKXTAL2

1
25MHZ_12PF_7V25000012 14 30 +LAN_VDD10 R225
(17) PCIE_PTX_C_DRX_N3 HSIN AVDD10
2 15 31 LAN_RSET 1 2 R226
GND (15) CLK_PCIE_LAN REFCLK_P RSET
NOGCLK@ 16 32 +3V_LAN 2.49K_0402_1% 15K_0402_5%
(15) CLK_PCIE_LAN# REFCLK_N AVDD33 33
GND

2
4
GND

3
C359
15P_0402_50V8J 3 RTL8111GUL-CG_QFN32_4X4
1 2 XTLO SA00006ML10

NOGCLK@

JRJ1 CONN@
B B
9
MDO0+ 1 GND
D10 @ESD@ PR1+ 10
AZC099-04S.R7G_SOT23-6 MDO0- 2 GND
MDI2- 1 4 MDI3- PR1-
I/O1 I/O3 MDO1+ 3
PR2+
MDO2+ 4 CHASSIS1_GND
TS1 2 5 PR3+
+V_DAC 1 24 GND VDD MDO2- 5
TCT1 MCT1 PR3-
MDI3- 2 23 MDO3- MDO1- 6
TD1+ MX1+ MDI3+ 3 6 MDI2+ PR2-
MDI3+ 3 22 MDO3+ I/O2 I/O4 MDO3+ 7
TD1- MX1- PR4+ 11
+V_DAC 4 21 MDO3- 8 GND
TCT2 MCT2 FOR EMI suggest PR4- 12
MDI2- 5 20 MDO2- R227 EMI@ GND
TD2 MX2+ Place Close to TS1
1 2 1 2
MDI2+ 6 19 MDO2+ 75_0805_5% CHASSIS1_GND SANTA_130460-3
TD2- MX2- C360 10P_0603_50V8-J @ESD@ DC234007K00
+V_DAC 7 18 D14
TCT3 MCT3 2 1 AZC099-04S.R7G_SOT23-6
MDI0- 8 17 MDO0- MDI0- 1 4 MDI1-
TD3+ MX3+ DL1 I/O1 I/O3
MDI0+ 9 16 MDO0+ BS4200N-C-LV_SMB-F2
TD3- MX3- EMI@
+V_DAC 10 15 2 5
TCT4 MCT4 SCV00001D00 GND VDD
MDI1- 11 14 MDO1-
TD4+ MX4+
MDI1+ 12 13 MDO1+ MDI0+ 3 6 MDI1+
TD4- MX4- I/O2 I/O4

A
350UH_IH-160
D10/D14 A

1 SP050006F00
PN:SC300001J00 Place Close to TS1
C300
0.01U_0402_16V7K
2
TS1

8106@ Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/15 Deciphered Date 2012/07/11 Title

HH-160 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN-RTL8111GUS/8106EUS
SP050005D00 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-B111P 0.2

Date: Wednesday, October 30, 2013 Sheet 25 of 59

5 4 3 2 1
 A B C D E F G H

+3VS +3VDD_CODEC +3VDD_CODEC +IOVDD_CODEC

600ohms @100MHz 2A
P/N: SM01000EE00 R228
0_0603_5% 0_0603_5%
R229
Place near U10 +5VDDA_CODEC 1 @ 2 2 @ 1
R230 +5VS

0.1U_0402_16V7K

1U_0402_6.3V6K

0.1U_0402_16V7K
+5VS 1 @ 2 +5VS_PVDD Place near Pin26 1 1

1
C361

C362

C363
0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
0_0805_5% 2 1 1 1 @ 2
+IOVDD_CODEC L10 0_0603_5% @

C365

C366

2
1 V1.0 2 2 1

C364

0.1U_0402_16V7K

4.7U_0603_6.3V6K
+3VDD_CODEC +1.5VS
1 2 2 1 1
R231 @

C367

C368
1 2 Place near Pin1 Place near Pin9
0_0402_5%
1
C369 2 2
1U_0402_6.3V6K
2

41

46

26

40
1

9
U10
Place near Pin40

DVDD-IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
22
21 LINE1-L(PORT-C-L) 43 SPK_L-

24
LINE1-R(PORT-C-R) SPK-OUT-L-
SPK-OUT-L+
42 SPK_L+ JACK_PLUG Delay circutis
23 LINE2-L(PORT-E-L) 45 SPK_R+
LINE2-R(PORT-E-R) SPK-OUT-R+ 44 SPK_R- +3VS +3VS
EXT_MIC_RING2 17 SPK-OUT-R-
W=40 mils (34) EXT_MIC_RING2 MIC2-L(PORT-F-L) /RING2
EXT_MIC_SLEEVE 18
(34) EXT_MIC_SLEEVE MIC2-R(PORT-F-R) /SLEEVE 32 HP_OUTL (34)
HPOUT-L(PORT-I-L)

1
31 33 @ JACK_SENSE#
LINE1-VREFO-L HPOUT-R(PORT-I-R) HP_OUTR (34)
30 R377 @
LINE1-VREFO-R 10 HDA_SYNC_AUDIO R378
SYNC HDA_SYNC_AUDIO (13) 100K_0402_5%
DMIC_DATA 2 6 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO (13) 100K_0402_5%
(22) DMIC_DATA GPIO0/DMIC-DATA BCLK
DMIC_CLK 1 2 DMIC_CLK_R 3
(22) DMIC_CLK GPIO1/DMIC-CLK

2
1 L16 EMI@ SBY100505T-301Y-N

3
@
R235 1 2 0_0402_5% PDB 47 5 HDA_SDOUT_AUDIO 5
ALC283-CG Q19A
D
C370
22P_0402_50V8J

(27,31) EC_MUTE# HDA_SDOUT_AUDIO (13)

G

HDA_RST_AUDIO# 11 PDB SDATA-OUT 8 R236 1 2 33_0402_5% DMN66D0LDW-7_SOT363-6

(13) HDA_RST_AUDIO# HDA_SDIN0 (13)
S
2 RESETB SDATA-IN

4
6
@EMI@ 48 R346 1 EMI@ 2 22_0402_5% @
SPDIF-OUT/GPIO2 SPDIF-OUT (34)
PC_BEEP 12 PLUG_IN# 1 2 2 Q19B
D

(34) PLUG_IN#
G
PCBEEP
JACK_SENSE# R237 1 2 39.2K_0402_1% 13 MONO-OUT
16 MONO-OUT (27) Sub-woofer @
R380
S

DMN66D0LDW-7_SOT363-6
SENSE A

1
2 14 MIC2-VREFO MIC2-VREFO (34) 10K_0402_5% 1 1 2
SENSE B 29
37 MIC2-VREFO C372 2 1 4.7U_0603_6.3V6K @ @
C373 2 1 1U_0402_6.3V6K 35 CBP 7 LDO3 C374 2 1 4.7U_0603_6.3V6K C500 C499
CBN LDO3-CAP 39 LDO2 10U_0603_6.3V6M 2 2 10U_0603_6.3V6M
LDO2-CAP 27 LDO1 C375 2 1 4.7U_0603_6.3V6K
36 LDO1-CAP R379 1 2 100K_0402_5%
+3VS CPVDD
C376 2 1 4.7U_0603_6.3V6K
28 C377 1 2 1U_0402_6.3V6K
20 VREF PLUG_IN# R376 1 2 0_0402_5% JACK_SENSE#
CPVREF 15 JDREF R239 1 2 20K_0402_1%
C378 2 1 4.7U_0603_6.3V6K 19 JDREF 34 CPVEE
MIC-CAP CPVEE
Reserve for cancel Delay circutis
2
R240 1 2 0_0402_5% 4
49 DVSS 25 C379
Thermal PAD AVSS1 38
AVSS2 1U_0402_6.3V6K
1

ALC283-CG_MQFN48_6X6
R240 pop on ALC283, SA000060500
NC on ALC233

+3VLP

+3VS

1
EXT_MIC_SLEEVE

100K_0402_5%
R232
1

3
2N7002KDWH_SOT363-6
EMI SPK_R+_CONN SPK_L-_CONN R233 @

Q16B
2
100K_0402_5% 5
SPK_R-_CONN SPK_L+_CONN

2
3 3

4
3

1 2 HDA_BITCLK_AUDIO

2N7002KDWH_SOT363-6
Q16A
HDA_RST_AUDIO# 1 2 2
R248@EMI@ 27_0402_5% @ESD@ @ESD@ R234
1 10K_0402_5% 1

1
1U_0402_6.3V6K
C371
@EMI@ D15 D16
C387 PACDN042Y3R_SOT23-3 PACDN042Y3R_SOT23-3 @
1

33P_0402_50V8J GNDA
2 2

Reserve for ESD request.

wide 40MIL JSPK1 CONN@

R245 1 2 0_0402_5%
@EMI@ EC Beep (31) BEEP# 1 2 SPK_R+ R241 1 EMI@ 2 0_0603_5% SPK_R+_CONN 4 6
C384 0.1U_0402_16V7K SPK_R- R242 1 EMI@ 2 0_0603_5% SPK_R-_CONN 3 4 G2 5
SPK_L+ R243 1 EMI@ 2 0_0603_5% SPK_L+_CONN 2 3 G1
C386 2
R246 1 2 0_0402_5%
@EMI@ R249 SPK_L- R244 1 EMI@ 2 0_0603_5% SPK_L-_CONN 1
1 2PC_BEEP1 1 2 1 2 PC_BEEP 1
PCH Beep

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K
(13) HDA_SPKR
C385 0.1U_0402_16V7K 1K_0402_5% 1 1 1 1 CVILU_CI4304M2HR0-NH
R247 1 2 0_0402_5%
@EMI@ SP02000Y500

C380

C381

C382

C383
0.1U_0402_16V7K
1

@ SE074102K80
R200 1 @EMI@ 2 0_0402_5% PC Beep R250
10K_0402_5% EMI@
2
EMI@
2
EMI@
2
EMI@
2
2

4 4

GND GNDA

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HD Audio ALC283/Audio Jack
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 26 of 59
A B C D E F G H
 Place near Pin25
Sub Woofer +5VS
+12VS_WF
R251
2 WF@ 1 +12VS

10U_0805_25V6K
0.1U_0402_16V7K
1 0_0805_5%

1
C388

WF@ C389
2
2

1
10_0603_5%

WF@
R252
WF@
@ 100K_0402_5%
R253
U14 WF@

2
from EC WF@
R254 1 2 1K_0402_5% 1 28 WF_GNDA
(26,31) EC_MUTE# 2 SD# LPVDD 27
FLAG# LPVDD
C390 WF@
WF_GNDA 3 26
4 LINP LBSP 25 1 2 0.47U_0603_10V
WF@ LINN LOUTP
EMI@
WF@ GAIN0 5 24 L29 1 2 JSPK2 CONN@
WF@ GAIN1 6 GAIN0 PGND FBMA-L11-201209-221LMA30_2P 4
WF@ GAIN1 23 SPKWF+ 3 GND
LOUTN @EMI@ GND
C391 1 2 1U_0402_16V6K 7 22 SPKWF+ L27 1 2 SPKWF+_CONN 2
AVDD LBSN 22uH// SH00000K000 1 2
1
Close to U14 WF_GNDA
C392 1 2 1U_0402_16V6K VCLAMP
8
AGND RBSN
ROUTN
21
20 SPKWF- SPKWF- L26 1
@EMI@
2 SPKWF-_CONN ACES_50271-0020N-001
WF_GNDA 20K_0402_1% R224 2 1 2 WF@ 1 9 22uH// SH00000K000
C469 2 1 R297 62K_0402_1% 10 VCLAMP 19 EMI@
1U_0402_16V6K
V0.2 PLIMIT PGND C394 WF@ L40 1 2

C396 @EMI@

C397 @EMI@
2.2U_0603_16V6K

2.2U_0603_16V6K
1

1
WF_GNDA
8.66K_0402_1% 2 R299 1 1 2 11 18 1 2 0.47U_0603_10V FBMA-L11-201209-221LMA30_2P
R1564 WF@ R1565 WF@ RINN ROUTP

1
C393 0.47U_0603_10V 12 17 WF_GNDA
2 1 2 1 15K_0402_1% 2 R341 1 1 2 RINP RBSP @EMI@ R349 R348 @EMI@
(26) MONO-OUT 0_0402_5% 0_0402_5% C395 0.47U_0603_10V 13 16 10_0402_5% 10_0402_5%
NC RPVDD

2
20.5K_0402_1% 2 R342 1 14 15
WF_GNDA WF@ MONO RPVDD +12VS_WF

1 2

1 2
1 1 WF@ @EMI@ C477
680P_0402_50V7K 2 1 C472 29 C478 @EMI@
C450 @ C443 @ GND 330P_0402_50V7K

10U_0805_25V6K
330P_0402_50V7K

0.1U_0402_16V7K
22P_0402_50V8J 22P_0402_50V8J V0.2 1 WF_GNDA WF_GNDA

C471

WF@ C470
WF@

2
2 2

1
WF@ APA2619RI-TRL_TSSOP28 WF_GNDA C396 C397
WF@ SA00007BA00

WF@

2
WF@ 2
WF_GNDA EMI@ EMI@
WF_GNDA WF_GNDA

1000P 50V X7R 0603 1000P 50V X7R 0603

SE025102J80 SE025102J80
WF_GNDA
+5VS

R257 1 @ 2 10K_0402_5% GAIN0

R382 1 EMI@ 2 0_0402_5% V
R258 1 @ 2 10K_0402_5% GAIN1
R381 1 EMI@ 2 0_0402_5%
WF@
R259 1 2 10K_0402_5%
R383 1 EMI@ 2 0_0402_5% WF@
R260 1 2 10K_0402_5%

WF_GNDA WF_GNDA

+CHGRTC_R

GCLK@
Green CLK +RTCVCC

390_0402_5% 2 1 R366

1
22U_0603_6.3V6M 2 1 C496 R374
U24 0_0402_5%
GCLK@ @
+3VLP C495

2
GCLK@ 10 14 1 2 2.2U_0402_6.3V6M
C485 VBAT VDD_RTC_OUT GCLK@
1 2 15
0.1U_0402_16V7K +V3.3A

+3V_LAN 2
VDD 9 CLK_32K_RTC_XIN_R R373 1 GCLK@ 2 0_0402_5% CLK_32K_RTC_XIN
32kHz CLK_32K_RTC_XIN (13)
GCLKDIS@
+3V3_AON 11 12 CLK_27M_VGA_XIN_R R364 1 2 22_0402_5% CLK_27M_VGA_XIN
VDDIO_27M 27MHz CLK_27M_VGA_XIN (36)

+3V_LAN 8 6 CLK_25M_LAN_XIN_R R365 1 GCLK@ 2 33_0402_5% CLK_25M_LAN_XIN

VDDIO_25M_A 25MHz_A CLK_25M_LAN_XIN (25)

+1.05VS 3 5 CLK_25M_PCH_XIN_R R363 1 GCLK@ 2 0_0402_5% CLK_25M_PCH_XIN

VDDIO_25M_B 25MHz_B CLK_25M_PCH_XIN (15)
C489 1 25M_GREEN_XIN 1
0.1U_0402_16V7K

0.1U_0402_16V7K

1 1 XTAL_IN
C487 C488 25M_GREEN_XOUT 16 for EMI
0.1U_0402_16V7K

0.1U_0402_16V7K

1 XTAL_OUT
GND1
GND2
GND3

GND4

C486
GCLK@

GCLK@

GCLK@

2 2 2
GCLK@

2
SLG3NB304VTR_TQFN16_2X3
4
7
13

17

GCLKDIS@ C498 1 2 10P_0402_25V8J

@EMI@
C491 1 2 10P_0402_25V8J
@EMI@
C492 1 2 10P_0402_25V8J
@EMI@
C490 1 2 10P_0402_25V8J
@EMI@
25M_GREEN_XIN U24 GCLKUMA@

25M_GREEN_XOUT Reserve for EMI

Y4 25MHZ_10PF_7V25000014 SLG3NB244VTR
1 3
1 3
GND GND
2 GCLK@ 2
GCLK@ C494 2 4 C493
GCLK@ 12P_0402_50V8J
15P_0402_50V8J
1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

2011/06/15 2012/07/11
Issued Date Deciphered Date Title
ROM/KBD/PWR/CR/LED/TP Conn.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 27 of 59
 1 2 3 4 5

WLAN

A A

+3VS +3VS_WLAN

JP7
1 2
1 2
JUMP_43X39 1 1
JP@
C398 C399
For Power consumption 4.7U_0603_6.3V6K 0.1U_0402_16V7K

Measurement
2 2
NGFF for WLAN (TYPE 2230)

+3VS_WLAN

JWLAN1 CONN@

1 2
USB20_P10 3 GND 3.3VAUX 4
(17) USB20_P10 USB_D+ 3.3VAUX
Bluetooth USB20_N10 5 6
(17) USB20_N10 USB_D- LED1#
7 8
9 GND PCM_CLK 10
B B
11 SIDO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_IN 14
15 SDO_DAT0 PCM_OUT 16
17 SDO_DAT1 LED2# 18
19 SDO_DAT2 GND 20
SDO_DAT3 UART_WAKE#
21
SDIO_WAKE# UART_RX
22 For EC to detect
23
SDIO_RESET# debug card insert.

24 R267 1 2
V0.2 25 UART_TX 26 100K_0402_5%
27 GND UART_CTS 28
(17) PCIE_PTX_C_DRX_P2 PETP0 UART_RTS
29 30
(17) PCIE_PTX_C_DRX_N2 PETN0 RESERVED EC_TX (31,34)
31 32
GND RESERVED EC_RX (31,34)
33 34
(17) PCIE_PRX_DTX_P2 PERP0 RESERVED
35 36
(17) PCIE_PRX_DTX_N2 PERN0 COEX3
37 38
CLK_PCIE_WLAN1 39 GND COEX2 40
(15) CLK_PCIE_WLAN1 REFCLKP0 COEX1
(15) CLK_PCIE_WLAN1# CLK_PCIE_WLAN1# 41 42 SUSCLK
REFCLKN0 SUSCLK SUSCLK (14,31)
43 44 PLT_RST# (14,25,31,34,36)
CLKREQ_WLAN# 45 GND PERST0# 46
(15) CLKREQ_WLAN# CLKEQ0# W_DISABLE2# W_DISABLE#2 (14,18)
(14,18) PCIE_WAKE# R263 1 @ 2 0_0402_5% 47 48 W_DISABLE#1 (14,18)
49 PEWAKE0# W_DISABLE1# 50
51 GND I2C_DATA 52
53 RSRVD/PETP1 I2C_CLK 54
55 RSRVD/PETN1 ALERT 56
57 GND RESERVED 58
59 RSRVD/PERP1 RESERVED 60
C
61 RSRVD/PERN1 RESERVED 62 C
63 GND RESERVED 64
65 RESERVED 3.3VAUX 66
RESERVED 3.3VAUX +3VS_WLAN
67
GND

69 68
MTG77 MTG76

CONCR_213EAAA32FA
SP070011I00

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN/SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 28 of 59
1 2 3 4 5
 1 2 3 4 5

SATA HDD CONN.

A A

+3VS JHDD1
SATA_PTX_C_DRX_P4_RC400 2 1 0.01U_0402_16V7K SATA_PTX_DRX_P4_C 1
SATA_PTX_C_DRX_N4_RC402 2 1 0.01U_0402_16V7K SATA_PTX_DRX_N4_C 2 1
U15 @ 3 2
7 10 SATA_PRX_C_DTX_N4_RC403 2 1 0.01U_0402_16V7K SATA_PRX_DTX_N4_C 4 3
+3VS EN VDD 4
20 SATA_PRX_C_DTX_P4_RC404 2 1 0.01U_0402_16V7K SATA_PRX_DTX_P4_C 5
SATA_PTX_DRX_P4 0.01U_0402_16V7K 1 2 C405 SATA_PTX_C_DRX_P4 1 VDD 6 5
(13) SATA_PTX_DRX_P4 A_INp 6
SATA_PTX_DRX_N4 0.01U_0402_16V7K 1 2 C401 SATA_PTX_C_DRX_N4 2 6 DEW2 7
(13) SATA_PTX_DRX_N4 A_INn NC 7
16 DEW1 8
SATA_PRX_DTX_P4 0.01U_0402_16V7K 1 2 C406 SATA_PRX_C_DTX_P4 5 NC 9 8
(13) SATA_PRX_DTX_P4 B_OUTp 9
SATA_PRX_DTX_N4 0.01U_0402_16V7K 1 2 C407 SATA_PRX_C_DTX_N4 4 9 SATA1_A_PRE0 +5VS 1 @ 2 +5VS_HDD 10
(13) SATA_PRX_DTX_N4 B_OUTn A_PRE0 10
8 SATA1_B_PRE0 R345 0_0805_5%
SATA1_A_PRE1 19 B_PRE0
SATA1_B_PRE1 17 A_PRE1 15 SATA_PTX_C_DRX_P4_R
B_PRE1 A_OUTp 14 SATA_PTX_C_DRX_N4_R
SATA1_TEST 18 A_OUTn
3 TEST 11 SATA_PRX_C_DTX_P4_R
13 GND B_INp 12 SATA_PRX_C_DTX_N4_R 11
21 GND B_INn 12 GND
EPAD GND
PS8520CTQFN20GTR2-A_TQFN20_4X4 ACES_50208-01001-001
CONN@

U15 Parade@ U15 TI@ SP01000JF10

B B
PS8520CTQFN20GTR2-A_TQFN20_4X4 SN75LVCP601RTJR_TQFN20_4X4

SA00005U300 SA00003ZX00

Add EQ pin for PI3EQX6741STZDEX

+3VS
+3VS Place caps.
near U1 5
+5VS_HDD
Pleace near HDD CONN
@ @
SATA1_TEST 1 R269 2 0_0402_5% SATA1_TEST 1 R268 2 0_0402_5% +5VS_HDD

1U_0402_6.3V6K
C408

0.1U_0402_16V7K
C411

0.01U_0402_16V7K
C412
1 1

1
@ @

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K
SATA1_B_PRE11 R270 2 0_0402_5% SATA1_B_PRE11 R271 2 4.7K_0402_5% 1 1 1 1
@ Parade@

C413

C414

C409

C410
2 2

2
C SATA1_A_PRE11 R272 2 0_0402_5% SATA1_A_PRE1 1 R273 2 4.7K_0402_5% C
@ @ @ @
SATA1_A_PRE01 R274 2 0_0402_5% SATA1_A_PRE01 R275 2 4.7K_0402_5% 2 2 2 2
@ @
SATA1_B_PRE01 R276 2 0_0402_5% SATA1_B_PRE01 R277 2 4.7K_0402_5%
@ @
DEW1 1 R296 2 0_0402_5% DEW1 1 R340 2 4.7K_0402_5%
@ @
DEW2 1 R369 2 0_0402_5% DEW2 1 R384 2 4.7K_0402_5%

D D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDD/ODD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 29 of 59
1 2 3 4 5
 A B C D E

@EMI@
R278 2 1 0_0402_5%
+USB3_VCCA
L17 EMI@ +USB3_VCCA
3 4 U3RXDN1 +5VALW 1.5A
(17) USB3_RX1_N 3 4 JUSB1 CONN@ U16
U3TXDP1 9 W=80mils
2 1 U3RXDP1 1 SSTX+ 1 8
(17) USB3_RX1_P 2 1 VBUS GND OUT
U3TXDN1 8 2 7
DLW21HN900HQ2L_4P SSTX- IN OUT
CON-USBP0+ 3 1 2 3 6
R279 2 1 0_0402_5% 7 D+ C417 @ C418 4 IN OUT 5 USB_OC0#
GND EN# OC# USB_OC0# (17,18)
@EMI@ CON-USBP0- 2 10
U3RXDP1 6 D- GND 11 0.1U_0402_16V7K 2.2U_0603_10V6K
1 R280 2 @EMI@ 1 0_0402_5% 4 SSRX+ GND 12 2 1 AP2301MPG-13 MSOP 8P 1
GND GND 1
U3RXDN1 5 13
L18 EMI@ SSRX- GND + C415
(17) USB3_TX1_N 2 1 U3TXDN1_R 3 4 U3TXDN1 TAITW_PUBAU2-09FNLS1NN4H0 USB_ON# 220U_6.3V_M
C419 0.1U_0402_16V7K 3 4 PCB Footprint = C_MP6VLPS220MC4R2
2
DC233008A20
(17) USB3_TX1_P 2 1 U3TXDP1_R 2 1 U3TXDP1
C420 0.1U_0402_16V7K 2 1
DLW21HN900HQ2L_4P

R281 2 1 0_0402_5%
EMI @EMI@
Co-lay
D17
U3TXDP1 1 9U3TXDP1
D18
U3TXDN1 2 8U3TXDN1
EMI 3 CON-USBP0-
U3RXDP1 4 7U3RXDP1 1
R282 2 1 0_0402_5%
@EMI@ 2 CON-USBP0+
U3RXDN1 5 6U3RXDN1
DLW21HN900HQ2L_4P YSLC05CH_SOT23-3
(17) USB20_N0 USB20_N0 2 1 CON-USBP0-
2 1 @ESD@
3
(17) USB20_P0 USB20_P0 3 4 CON-USBP0+ SC300001G00 6pin
3 4 TVWDF1004AD0_DFN9
L19 EMI@ @ESD@
R283 2 1 0_0402_5%
@EMI@

2 2

+USB3_VCCB

@EMI@
R284 2 1 0_0402_5% JUSB2 CONN@
U3TXDP2 9 +USB3_VCCB
L20 EMI@ 1 SSTX+
3 4 U3RXDN2 U3TXDN2 8 VBUS +5VALW U17
1.5A
(17) USB3_RX2_N 3 4 SSTX-
CON-USBP1+ 3 W=80mils
7 D+ 1 8
2 1 U3RXDP2 CON-USBP1- 2 GND 10 2 GND OUT 7
(17) USB3_RX2_P 2 1 D- GND IN OUT
U3RXDP2 6 11 1 2 3 6
DLW21HN900HQ2L_4P SSRX+ GND IN OUT
4 12 C423 @C424
@ C424 4 5 USB_OC0#
R285 2 1 0_0402_5% U3RXDN2 5 GND GND 13 EN# OC#
@EMI@ SSRX- GND 0.1U_0402_16V7K 2.2U_0603_10V6K
TAITW_PUBAU2-09FNLS1NN4H0 2 1 AP2301MPG-13 MSOP 8P 1
3 R286 2 1 0_0402_5% 3
@EMI@ + C416
DC233008A20
L21 EMI@ 220U_6.3V_M
(17) USB3_TX2_N 2 1 U3TXDN2_R 3 4 U3TXDN2 (31) USB_ON# USB_ON# PCB Footprint = C_MP6VLPS220MC4R2
C425 0.1U_0402_16V7K 3 4 2

(17) USB3_TX2_P 2 1 U3TXDP2_R 2 1 U3TXDP2

C426 0.1U_0402_16V7K 2 1
DLW21HN900HQ2L_4P

R287 2 1 0_0402_5%
D19
EMI @EMI@
Co-lay U3RXDN2 1 9U3RXDN2
D20
U3RXDP2 2 8U3RXDP2 3 CON-USBP1+
1
U3TXDN2 4 7U3TXDN2 2 CON-USBP1-

EMI U3TXDP2 5 6U3TXDP2

YSLC05CH_SOT23-3
@EMI@
R288 2 1 0_0402_5% @ESD@

L22 EMI@ 3 SC300001G00 6pin

USB20_P1 3 4 CON-USBP1+
(17) USB20_P1 3 4 TVWDF1004AD0_DFN9
@ESD@
USB20_N1 2 1 CON-USBP1-
(17) USB20_N1 2 1
DLW21HN900HQ2L_4P

R289 2 1 0_0402_5%
@EMI@
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/iPODcharger/Felica
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 30 of 59
A B C D E
 5 4 3 2 1

+3VLP_EC +EC_VCCA
+3VLP Vcc 3.3V Board ID
L23
JP8 FBMA-L11-160808-800LMT_0603 +3VLP_EC
Ra 100K +/- 1%
1 2 1 2 +EC_VCCA
1 2
Board ID Rb VAD_BID typ V

2
JUMP_43X39

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1000P_0402_50V7K

1000P_0402_50V7K

0_0402_5%
1 1 1 2 2 1
JP@ @ @ @ R291

C427

C428

C429

C430

C431

R290
C432
0 0 0 V Ra 100K_0402_1%
+EC_VCCLPC 0.1U_0402_16V7K
For Power consumption 2 2 2 1 1 2 1 12K +/- 1% 0.354 V
Measurement

1
2
15K +/- 1% BRDID
ECAGND
2 0.430 V
ECAGND (47)

1
3 20K +/- 1% 0.550 V 1
R292 C433

111
125
D 0.1U_0402_16V7K D
Rb 0_0402_5%

22
33
96

67
U18

9
@
2

EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC
EC_VDD/VCC

EC_VDD/VCC

EC_VDD/AVCC
EC_VDD0

2
1 21 Analog Board ID definition,
(14,18) GATEA20 GATEA20/GPIO00 GPIO0F KBL_W_PWM# (32)
2 23
(14,18) KB_RST# KBRST#/GPIO01 BEEP#/GPIO10 BEEP# (26) Please see page 3.
3 26
(16) SERIRQ SERIRQ GPIO12 EC_FAN_PWM1 (34)
LPC_FRAME# 4 27
+3VLP_EC (16) LPC_FRAME# LPC_FRAME# ACOFF/GPIO13 EC_FAN_PWM2 (34)
LPC_AD3 5
(16) LPC_AD3 LPC_AD3
LPC_AD2 7 PWM Output C438 2 1 100P_0402_50V8J ECAGND
(16) LPC_AD2 LPC_AD2
LPC_AD1 8 63 VCIN1_BATT_TEMP BATT_TEMP
(16) LPC_AD1 LPC_AD1 BATT_TEMP/GPIO38 VCIN1_BATT_TEMP (47)
LPC_AD0 10 LPC & MISC 64 VCIN1_BATT_DROP
(16) LPC_AD0 LPC_AD0 GPIO39 65 ADP_I
VCIN1_BATT_DROP (47) For 9022 only
ADP_I/GPIO3A ADP_I (47,48)
1 @ 2 LAN_WAKE# CLK_PCI_EC 12 AD Input 66
(15) CLK_PCI_EC CLK_PCI_EC GPIO3B ADP_ID (46)
R295 10K_0402_5% 13 75 BRDID
(14,25,28,34,36) PLT_RST# PCIRST#/GPIO05 GPIO42
1 @ 2 VCIN1_BATT_TEMP EC_RST# 37 76
EC_RST# IMON/GPIO43 ENBKL (14)
R293 47K_0402_5% EC_SCI# 20 R368 2 @ 1 BKOFF#
(18) EC_SCI# EC_SCII#/GPIO0E
38 0_0402_5%
(47) BATT_LEN# GPIO1D 68
EC DAC_BRIG/GPIO3C AOU_EN (34)
2 9012@ 1 EC_RST# 70
(32) KSI[0..7] EN_DFAN1/GPIO3D
R298 47K_0402_5% DA Output 71
IREF/GPIO3E ADP_ID_CLOSE (46)
9012@ KSI0 55 72
KSI0/GPIO30 CHGVADJ/GPIO3F SUSWARN# (14) DS3
1 2 KSI1 56
C434 0.1U_0402_16V7K KSI2 57 KSI1/GPIO31
KSI3 58 KSI2/GPIO32 83 EC_MUTE#
KSI3/GPIO33 EC_MUTE#/GPIO4A EC_MUTE# (26,27)
1 2 ACIN EC KSI4 59 84 USB_ON#
KSI4/GPIO34 USB_EN#/GPIO4B USB_ON# (30)
C435 100P_0402_50V8J KSI5 60 85
KSI5/GPIO35 CAP_INT#/GPIO4C TPL_GND (32)
2 @ 1 VCOUT1_PROCHOT# KSI6 61 PS2 Interface 86
KSI6/GPIO36 EAPD/GPIO4D SYS_PWROK (14,5)
R300 100K_0402_5% KSI7 62 87 TP_CLK
(32) KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_CLK (32)
KSO0 39 88 TP_DATA
KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA (32)
C KSO1 40 C
2 @ 1 EC_MUTE# KSO2 41 KSO1/GPIO21
R302 10K_0402_5% KSO3 42 KSO2/GPIO22 97
KSO3/GPIO23 CPU1.5V_S3_GATE/GPXIOA00 LAN_PWRDN (25)
@EMI@ KSO4 43 98 VGA_AC_DET
KSO4/GPIO24 WOL_EN/GPXIOA01 PWR_LEVEL (36)
2 1 2 @EMI@ 1CLK_PCI_EC 44
KSO5/GPIO25 Int. K/B
KSO5 99 ME_FLASH
ME_EN/GPXIOA02 ME_FLASH (13)
C436 R303 33_0402_5% KSO6 45 109 VCIN0_PH1
46 KSO6/GPIO26 Matrix VCIN0_PH/GPXIOD00 VCIN0_PH1 (47) NTC_V
22P_0402_50V8J KSO7
KSO7/GPIO27 SPI Device Interface
1 2 PLT_RST# KSO8 47
C497 @ESD@ 100P_0402_50V8J KSO9 48 KSO8/GPIO28 119 SPI_SO_L
KSO9/GPIO29 SPIDI/GPIO5B SPI_SO_L (16)
KSO10 49 120 SPI_SI_R
KSO10/GPIO2A SPIDO/GPIO5C SPI_SI_R (16)
KSO11 50 SPI Flash ROM 126 SPI_CLK_PCH_EC R1181 2
KSO11/GPIO2B SPICLK/GPIO58 SPI_CLK_PCH (16)
KSO12 51 128 SPI_SB_CS0# 15_0402_5%
KSO12/GPIO2C SPICS#/GPIO5A SPI_SB_CS0# (16)
KSO13 52
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 VGA_ALERT#
KSO15/GPIO2F ENBKL/GPIO40 VGA_ALERT# (36)
KSO16 81 74
KSO16/GPIO48 PECI_KB930/GPIO41 VGATE (55)
KSO17 82 89
KSO17/GPIO49 FSTCHG/GPIO50 90 BATT_CHG_LED#
BATT_CHG_LED#/GPIO52 BATT_CHG_LED# (33)
91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# (32)
EC_SMB_CK1 77 GPIO 92 PWR_LED#
(47,48) EC_SMB_CK1 EC_SMB_CK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# (33)
EC_SMB_DA1 78 93 BATT_LOW_LED#
(47,48) EC_SMB_DA1 EC_SMB_DA1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_LOW_LED# (33)
EC_SMB_CK2 79 SM Bus 95 SYSON
(16,32,36) EC_SMB_CK2 EC_SMB_CK2/GPIO46 SYSON/GPIO56 SYSON (35,50)
EC_SMB_DA2 80 121
(16,32,36) EC_SMB_DA2 EC_SMB_DA2/GPIO47 VR_ON/GPIO57 VR_ON (55)
127 PM_SLP_S4#
PM_SLP_S4#/GPIO59 PM_SLP_S4# (14)

PM_SLP_S3# 6 100 EC_RSMRST#

(14) PM_SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# (14)
PM_SLP_S5# 14 101 EC_LID_OUT#
+3VS +3VLP_EC (14) PM_SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# (18)
EC_SMI# 15 102 Turbo_V
(15,18) EC_SMI# EC_SMI#/GPIO08 PROCHOT_IN/GPXIOA05 VCIN1_ADP_PROCHOT (47)
RP25 16 103 VCOUT1_PROCHOT# PROCHOT
GPIO0A H_PROCHOT#_EC/GPXIOA06 VCOUT1_PROCHOT# (47)
1 8 EC_SMB_CK1 V0.2
(14,35) SLP_SUS# 17 104 VCOUT0_MAIN_PWR_ON MAINPWON
GPIO0B VCOUT0_PH/GPXIOA07 VCOUT0_MAIN_PWR_ON (49)
2 7 EC_SMB_DA1 EC 18 GPO 105 R367 2 1 BKOFF#
B (54) PWR_GPS_DOWN# GPIO0C BKOFF#/GPXIOA08 BKOFF# (22)
3 6 EC_SMB_CK2 LAN_WAKE# 19 GPIO 106 PBTN_OUT# 0_0402_5% B
4 5 EC_SMB_DA2 V0.2 (25) LAN_WAKE# 25 GPIO0D PBTN_OUT#/GPXIOA09 107 DPWROK_EC
PBTN_OUT# (14)
(48) ACOFF EC_INVT_PWM/GPIO11 PCH_APWROK/GPXIOA10 DPWROK_EC (14)
28 108 +1.05VS_PGOOD
(34) EC_TACH1 FAN_SPEED1/GPIO14 SA_PGOOD/GPXIOA11 +1.05VS_PGOOD (52)
2.2K_0804_8P4R_5% 29
V0.2 (34) EC_TACH2 EC_TX 30 EC_PME#/GPIO15
(28,34) EC_TX EC_TX/GPIO16
1 2 TP_CLK EC_RX 31 110 ACIN
(28,34) EC_RX EC_RX/GPIO17 AC_IN/GPXIOD01 ACIN (14,48)
R304 4.7K_0402_5% PCH_PWROK 32 112 EC_ON
EC (14,9) PCH_PWROK PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON (49)
1 2 TP_DATA 34 114 ON/OFF
(33) NOVO# 36 SUSP_LED#/GPIO19 ON/OFF/GPXIOD03 115 ON/OFF (33)
R305 4.7K_0402_5%
(32) NUM_LED# NUM_LED#/GPIO1A GPI LID_SW#/GPXIOD04
LID_SW#
LID_SW# (33)
116 SUSP#
SUSP#/GPXIOD05 SUSP# (34,35,50,51,52,53)
1 2 EC_SCI# 117 NUVOTON_VTT R3701 @ 2 10K_0402_5% +1.05VS
R294 10K_0402_5% GPXIOD06 118 PECI_KB9012 1 2
PECI_KB9012/GPXIOD07 H_PECI (5)
SUSCLK 122 R306 43_0402_1%
AGND/AGND

(14,28) SUSCLK XCLKI/GPIO5D

DGPU_PWR_EN 123 124 +V18R
GND/GND
GND/GND
GND/GND
GND/GND

(14,45) DGPU_PWR_EN XCLKO/GPIO5E V18R +3VLP_EC

For 9022 +V18R, +EC_VCCLPC can be
GND0

changed to 1.8V if supports 1.8V I/F.

1

R307 1 9022@ 2 0_0402_5%

1

C479 1
R339 @ @ KB9022C_LQFP128_14X14 C437
11
24
35
94
113

ECAGND 69

100K_0402_5%
20P_0402_50V8

SA000075S20 20mil 4.7U_0603_6.3V6K

2

9012@ R308 2 9022@ 1 0_0402_5%

2
2

+3VS
L24 2 1
FBMA-L11-160808-800LMT_0603 1 2 @
C439
<Co-lay> 1 9012@ 2 0.1U_0402_16V7K
(55) VR_HOT#

5
R309 0_0402_5%
KB9012A4 : SA00004OB30 ECAGND

P
H_PROCHOT# 4 2 VCOUT1_PROCHOT#
KB9022 C : SA000075S20 (5) H_PROCHOT# Y A

NC

G
1
A C440 U19 A

3
47P_0402_50V8J SN74LVC1G06DCKR_SC70-5
9012@ 9012@
2 ESD@

Security Classification
2009/12/01
Compal Secret Data
2011/12/31 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE­KB9012A4/KB9022
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA­B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 31 of 59
5 4 3 2 1
 Close to DDR
SMSC thermal sensor REMOTE1+ MMST3904-7-F_SOT323-3
placed near by VRAM +3VS
1

1
C
15" INT_KBD CONN. 17" @ C441
100P_0402_50V8J
2
B
Q12
2

1
E

3
JKB1 CONN@ JKB2 CONN@ +3VS R310 REMOTE1-
KSI1 1 KSI1 1 10K_0402_5%
KSI7 2 1 KSI7 2 1 @
KSI[0..7] KSI6 3 2 KSI6 3 2 U20
(31) KSI[0..7] 3 3

2
KSO9 4 KSO9 4 C444 2 0.1U_0402_16V7K
KSO[0..17] KSI4 5 4 KSI4 5 4
(31) KSO[0..17]
KSI5 6 5 KSI5 6 5 1 10 EC_SMB_CK2
Close to FAN
6 6 VDD SMCLK EC_SMB_CK2 (16,31,36)
KSO0 7 KSO0 7
KSI2 8 7 KSI2 8 7 1 REMOTE1+ 2 9 EC_SMB_DA2
8 8 DP1 SMDATA EC_SMB_DA2 (16,31,36) move to power board
KSI3 9 KSI3 9
KSO5 10 9 KSO5 10 9 REMOTE1- 3 8
KSO1 11 10 KSO1 11 10 DN1 ALERT#
KSI0 12 11 KSI0 12 11 REMOTE2+ 4 7
12 12 (33) REMOTE2+ DP2 THERM#
KSO2 13 KSO2 13
KSO4 14 13 KSO4 14 13 REMOTE2- 5 6
KSO7 15 14 KSO7 15 14 (33) REMOTE2- DN2 GND REMOTE1,2+/-:
15 15
KSO8
KSO6
16
17 16
KSO8
KSO6
16
17 16 Trace width/space:10/10 mil
17 17
KSO3 18
18
KSO3 18
18
EMC1403-2-AIZL-TR_MSOP10 Trace length:<8"
KSO12 19 KSO12 19 P/N:SA000029210
KSO13 20 19 KSO13 20 19
20 20 SA000029210
KSO14 21 KSO14 21
22 21 22 21
KSO11
22
KSO11
22 Address 1001_101xb F75303M P/N:SA000046C00
KSO10 23 KSO10 23
KSO15 24 23 KSO15 24 23 Close U20
KSO16 25 24 KSO16 25 24 REMOTE1+ REMOTE2+
300_0402_5% KSO17 26 25 KSO17 26 25
26 26 1 1
+5VS R311 1 2 +5VS_CAPLED 27 +5VS_CAPLED 27
CAPS_LED# 28 27 CAPS_LED# 28 27 C442 C445 @
(31) CAPS_LED# 28 28
+5VS R344 1 2 +5VS_NUMLED 29 31 +5VS_NUMLED 29 31 2200P_0402_50V7K 2200P_0402_50V7K
NUM_LED# 30 29 GND 32 NUM_LED# 30 29 GND 32 2 REMOTE1- 2 REMOTE2-
(31) NUM_LED# 30 GND 30 GND
300_0402_5%
ACES_88514-3001 ACES_88514-3001
SP010011A00 SP010011A00

+3VS

TouchPad
C446 15"
0.1U_0402_16V7K JTP1 CONN@

6 8
TP_CLK 5 6 G2 7
(31) TP_CLK 5 G1
TP_DATA 4
(31) TP_DATA 4
1 1 0_0402_5% 3
+5VS +5VS_KBL @EMI@ @EMI@ R313 2 @ 1PCH_SMB_CLK_TP 2 3
(11,12,16) SMB_CLK_S3 2
C447 C448 2 @ 1PCH_SMB_DATA_TP 1

R312
KB BackLight Control 100P_0402_50V8J
2 2
100P_0402_50V8J
(11,12,16) SMB_DATA_S3
R314 0_0402_5% 1
ACES_51524-0060N-001
40mil

2
1 @ 2 SP010014M10
KB Backlight
KB Backlight
10K_0402_5%

0_0805_5% @ESD@
1

15" D22
1

C449
17" PSOT24C_SOT23-3
R315

1U_0402_16V6K

1
@ JKBL1 CONN@
2

JKBL2 CONN@
2

+5VS_KBL 1
2 1 +5VS_KBL 1
30mil 2 1
KBL_GND 3 2 17"
Q11 4 3 KBL_GND 3 2
4 3
1

MMBF170-7-F_SOT23-3

4
5 4 17@ 300_0402_5% JTP2 CONN@
6 GND 5 R351 1 2 8
GND GND +5VS 8
6 TPL_GND 7 10
E&T_6916-Q04N-03R GND (31) TPL_GND 6 7 G2 9
+3VS 6 G1
2 SP01000TB00 E&T_6916-Q04N-03R TP_CLK 5
(31) KBL_W_PWM# SP01000TB00 TP_DATA 4 5
3 4
PCH_SMB_CLK_TP 2 3
PCH_SMB_DATA_TP 1 2
1
3

ACES_51524-0080N-001
SP01001A900

SPK Backlight
17"
+5VS JSPKL1 CONN@

1
2 1
KBL_GND 3 2 5
4 3 G1 6
4 G2
CVILU_CI4304M2HR0-NH
Security Classification Compal Secret Data Compal Electronics, Inc.
SP02000Y500
Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP/KC3810
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 32 of 59
 A B C D E

Connector: 0.3A / pin

PWR Board CONN.

4 +5VALW Power Board 4

+3VLP

1
R371
10K_0402_5%

2
R317

2
S

3
100K_0402_5% R318 G
100K_0402_5% PWR_LED# 2 Q24
(31) PWR_LED#
NOVO_BTN# PMV65XP_SOT23-3~D

1
D23 ON/OFFBTN# D

1
2 NOVO# PWR_LED
NOVO# (31)
NOVO_BTN# 1 1

2
3 ON/OFF
ON/OFF (31) C421
0.1U_0402_16V7K JPWR1 CONN@
DAN202UT106_SC70-3 D24 @ESD@ 2
PJSOT24C 3P C/A SOT-23 6 8
@ ON/OFFBTN# 5 6 G2 7
5 G1

1
R319 NOVO_BTN# 4
ON/OFFBTN# 2 1 REMOTE2+ 3 4
(32) REMOTE2+ 3
REMOTE2- 2
(32) REMOTE2- 2
0_0402_5% 1
JPW1 1
1 2 ACES_51524-0060N-001
SP010014M10
SHORT PADS

BOT SIDE
3 @ 3

Lid switch
LED-B CONN
2 2

+3VALW 1 R320 2 JLED1 CONN@

100K_0402_5% V0.2
+3VLP 6 8
LID_SW# PWR_LED 5 6 G2 7
LID_SW# (31) 5 G1
BATT_LOW_LED# 4
(31) BATT_LOW_LED# 4
BATT_CHG_LED# 3
(31) BATT_CHG_LED# 3
1 2 SATA_LED 2
2
2

1
C452 C453 1
VCC

VOUT

0.1U_0402_16V7K 10P_0402_50V8J V0.2 ACES_51524-0060N-001

2 1 +3VS SP010014M10
GND
1

1
U21 R385
10K_0402_5% @

2
S

3
G
SA00004PT00 2 Q22
(13) SATA_LED#
PMV65XP_SOT23-3~D
D

1
1
C501
0.1U_0402_16V7K
2

1 1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR_OK/FN_B/LED_B/RF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 33 of 59
A B C D E
 5 4 3 2 1

+5VALW

@
C454 2 1 4.7U_0402_6.3V6M

C455 2 1 0.1U_0402_16V7K
+USB2_VCCC
D D
@EMI@
U22 +USB2_VCCC R338 2 1 0_0402_5%
1 12
9 IN OUT 10 USB20_P4_L L25 EMI@
13 STATUS# DP_IN 11 USB20_N4_L USB20_P4_L 3 4 USB20_P4_CONN
(17) USB_OC2# FAULT# DM_IN 3 4
4 2

47U_0805_6.3V6M
ILIM_SEL DM_OUT USB20_N4 (17)
5 3

0.1U_0402_16V7K

C467
(31) AOU_EN EN DP_OUT USB20_P4 (17) 1

1
AOU_CTL1 6 15 R324 1 @ 2 2.2M_0402_1% USB20_N4_L 2 1 USB20_N4_CONN
AOU_CTL2 7 CTL1 ILIM_LO 16 R323 1 2 20K_0402_1% 2 1

C468
CTL2 ILIM_HI DLW21HN900HQ2L_4P
AOU_CTL3 8 14
CTL3 GND 2

2
17
T-PAD @ R336 2 1 0_0402_5%
TPS2544RTER_QFN16_3X3
SA000070N00 @EMI@

+5VALW
USB Board CONN.
R335 2 1 0_0402_5%

JSUB1 CONN@
AOU_CTL1 R337 2 @ 1 0_0402_5% AOU_CTL2 31 32
+USB2_VCCC 31 32
EMC 29
29 30
30
27 28 USB20_P4_CONN
R316 27 28
SPDIF-OUT 25 26 USB20_N4_CONN
1 2 AOU_CTL3 23 25 26 24
+5VALW (14,25,28,31,36) PLT_RST# 23 24
21 22
(15) CLKREQ_CR# 21 22

1
@EMI@ (17) PCIE_PTX_C_DRX_P5 PCIE_PTX_C_DRX_P5 19 20 CLK_PCIE_CR CLK_PCIE_CR (15)
C 100K_0402_5% PCIE_PTX_C_DRX_N5 17 19 20 18 CLK_PCIE_CR# C
(17) PCIE_PTX_C_DRX_N5 17 18 CLK_PCIE_CR# (15)
R347 PCIE_PRX_DTX_P5 15 16
D (17) PCIE_PRX_DTX_P5 15 16
1

22_0402_5% PCIE_PRX_DTX_N5 13 14
(17) PCIE_PRX_DTX_N5 13 14
(31,35,50,51,52,53) SUSP# R301 2 1 0_0402_5% AOU_CTL1 2 HP_OUTL 11 12 +3VS
(26) HP_OUTL 11 12

2
G HP_OUTR 9 10
(26) HP_OUTR 9 10
Q23 S 1 (26) EXT_MIC_SLEEVE EXT_MIC_SLEEVE 7 8 +5VS
7 8
3

2N7002H_SOT23-3 @EMI@ (26) EXT_MIC_RING2 EXT_MIC_RING2 5 6 PLUG_IN# PLUG_IN# (26)

C476 40 mils 3 5 6 4 SPDIF-OUT
40 mils 3 4 SPDIF-OUT (26)
22P_0402_50V8J 1 2
2 1 2

(26) MIC2-VREFO R321 1 2 2.2K_0402_5% ACES_50255-03001-001

SP02000RN00
R322 1 2 2.2K_0402_5%

D25
3 EXT_MIC_SLEEVE
1
2 EXT_MIC_RING2

YSLC05CH_SOT23-3
@ESD@

B
H1 @ H2 @
Fan1 Control Circuit B

HOLEA HOLEA FD1 FD2 FD3 FD4

FIDUCAL FIDUCAL FIDUCAL FIDUCAL
GPU @ @ @ @ +5VS
R325
1

0_0603_5% JFAN1 CONN@

1

1 @ 2 +5VS_FAN 1
2 1
H_3P2 H_3P2 (31) EC_TACH1 2
(31) EC_FAN_PWM1 3
4 3
5 4
2 G5
H3 @ H4 @ H5 @ H6 @ H10 @ H12 @ H13 @ 6
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA C456 G6
CPU MB 1
10U_0603_6.3V6M ACES_50273-0040N-001
SP02000TI00
1

10U
H_3P2 H_3P2 H_3P2 H_3P2 H_2P5 H_2P5 H_3P0 For Debug only'

H7 @
HOLEA
H15 @
HOLEA
H16 @
HOLEA
H17 @
HOLEA JDUG1 CONN@
+5VS FAN2 Control Circuit
R343
1 0_0603_5% JFAN2 CONN@
WLAN (28,31) EC_TX
+3VALW
2
3
1
2
1 @ 2 +5VS_FAN2 1
2 1
(28,31) EC_RX 3 (31) EC_TACH2 2
1

4 (31) EC_FAN_PWM2 3
5 4 4 3
H_3P2 H_2P5 H_2P5 H_3P0 6 G5 5 4
G6 2 G5
6
ACES_50273-0040N-001 C474 G6
A H8 @ H9 @ H20 H21 SP02000TI00 ACES_50273-0040N-001 A
10U_0603_6.3V6M
HOLEA HOLEA HOLEA HOLEA H22 1 SP02000TI00
HOLEA
LAN 10U
1

H_3P2
CHASSIS1_GND H_1P5N H_1P5N
for LAN screw hole
Security Classification Compal Secret Data Compal Electronics, Inc.
H_3P2 H_4P0X3P0
Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title
橢圓孔 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0/FAN/Screw holes
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 34 of 59
5 4 3 2 1
 A B C D E

+5VALW to +5VS Transfer

+5VALW

1 +5VS 1
+5VSJ
1 2
10U_0603_6.3V6M C457 @ +5VSJ @ JP5
JUMP_43X118
2 1 2 1
0.1U_0402_16V7K C458 U23 2 1 +3VALW +3V_PCH
1 14
200mil @ JP10
+5VL 2 VIN1 VOUT1 13 JUMP_43X39
VIN1 VOUT1 2 1

0.01U_0402_16V7K
R326 2 1 3VS_EN 3 12 C459 1 2 220P_0402_50V7K 2 1

10U_0603_6.3V6M
C460

C461
(31,34,50,51,52,53) SUSP# ON1 CT1 1 1
0_0402_5%
4 11
R327

VBIAS GND @ 3 1
10K_0402_5%

2 2
2

5 10 C462 1 2 470P_0402_50V7K 1 1
ON2 CT2 +3VSJ

1
AO3413_SOT23
DS3@ C484

DS3@ C483

4.7U_0603_6.3V6K

1U_0402_6.3V6K
+3VALW

1
6 9 120mil 4.7U_0603_6.3V6K @

@ C482
7 VIN2 VOUT2 8 Q10 R352
@

VIN2 VOUT2 2 2

2
DS3@ 470_0603_5%
1

2
15

0.01U_0402_16V7K
GPAD

2
10U_0603_6.3V6M
0.1U_0402_16V7K
1 TPS22966DPUR_SON14_2X3 V0.2 1@ +5VALW

10U_0603_6.3V6M
1 1 D

1
+3VSJ +3VS

C466
@ JP9 2 SLP_SUS

C463

C464

C465
R353
JUMP_43X39 DS3@ G
2 2@ 2 2 2 1 1 2 SLP_SUS S Q13 @
2 1

3
2N7002K_SOT23-3
47K_0402_5%

D 1

1
SLP_SUS# 2 C481 DS3@
2
(14,31) SLP_SUS# 0.1U_0402_16V7K 2

+3VALW to +3VS Transfer

G Q21 2
S
2N7002K_SOT23-3

3
DS3@

Discharge circuit-1 +3VALW +1.35V +0.675VS

+5VALW +1.5VS +1.05VS

3 3
1

1
1

1
R328 R331
R329 R330 22_0402_5% 220_0402_5% R332
100K_0402_5% 68_0402_5%
2

470_0402_5%

2
R333
2

2
0.675VS_CHG

100K_0402_5%
1.35V_CHG

1.5VS_CHG

VCCP_CHG
2
6

3
D
1

Q17B
D
1

(31,50) SYSON SYSON 2 2N7002KDWH_SOT363-6 Q18A Q18B

G SYSON# 2 SUSP 5 SUSP# 2 SUSP 2 2N7002KDWH_SOT363-6 SUSP 5 2N7002KDWH_SOT363-6
Q17A
R334

S G
3

Q7 2N7002KDWH_SOT363-6 Q8
10K_0402_5%

S
1

4
2

2N7002H_SOT23-3 2N7002H_SOT23-3
@
1

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC/DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS B LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 35 of 59
A B C D E
 5 4 3 2 1

U30A +3V3_AON

PEG_CRX_GTX_P[0..15] PEG_PTX_C_DRX_P0 AN12 Part 1 of 7 @

(4) PEG_CRX_GTX_P[0..15] PEX_RX0
PEG_PTX_C_DRX_N0 AM12
PEX_RX0_N GPIO0
P6 GC6_FB_EN
GC6_FB_EN (14,38) TO PCH XTAL_OUTBUFF 1 2
PEG_PTX_C_DRX_P1 AN14 M3 R503 10K_0402_5%
PEG_CRX_GTX_N[0..15] PEG_PTX_C_DRX_N1 AM14 PEX_RX1 GPIO1 L6
(4) PEG_CRX_GTX_N[0..15] PEX_RX1_N GPIO2
PEG_PTX_C_DRX_P2 AP14 P5 PWR_LEVEL_R 1 DIS@ 2
PEG_PTX_C_DRX_N2 AP15 PEX_RX2 GPIO3 P7 R502 100K_0402_5%
PEG_PTX_C_DRX_P[0..15] PEG_PTX_C_DRX_P3 AN15 PEX_RX2_N GPIO4 L7 3V3_MAIN_EN
(4) PEG_PTX_C_DRX_P[0..15] PEX_RX3 GPIO5 3V3_MAIN_EN (45,54)
PEG_PTX_C_DRX_N3 AM15 M7 GPU_EVENT# TO PCH XTAL_OUTBUFF 1 DIS@ 2
PEX_RX3_N GPIO6 GPU_EVENT# (14)
PEG_PTX_C_DRX_P4 AN17 N8 R517 10K_0402_5%
PEG_PTX_C_DRX_N[0..15] AM17 PEX_RX4 GPIO7 L3
(4) PEG_PTX_C_DRX_N[0..15]
PEG_PTX_C_DRX_N4
PEX_RX4_N GPIO8
SYS_PEX_RST_MON# TO PCH THRMTRIP#
PEG_PTX_C_DRX_P5 AP17
PEX_RX5 GPIO9
M2 VGA_ALERT#
VGA_ALERT# (31) TO EC
PEG_PTX_C_DRX_N5 AP18 L1 VRAM_VREF_CTL DIS@
PEX_RX5_N GPIO10 VRAM_VREF_CTL (41,43)
D PEG_PTX_C_DRX_P6 AN18 M5 NVVDD_PWM_VID PWR_LEVEL_R 2 1 D
PEX_RX6 GPIO11 NVVDD_PWM_VID (54) PWR_LEVEL (31)
PEG_PTX_C_DRX_N6 AM18 N3 PWR_LEVEL_R TO EC

GPIO
PEG_PTX_C_DRX_P7 AN20 PEX_RX6_N GPIO12 M4 NVVDD_PSI D31 RB751V-40_SOD323-2
PEX_RX7 GPIO13 NVVDD_PSI (54) +3V3_AON
PEG_PTX_C_DRX_N7 AM20 N4
PEG_PTX_C_DRX_P8 AP20 PEX_RX7_N GPIO14 P2
PEG_PTX_C_DRX_N8 AP21 PEX_RX8 GPIO15 R8 RP36
PEG_PTX_C_DRX_P9 AN21 PEX_RX8_N GPIO16 M6 3V3_MAIN_EN 1 8
PEG_PTX_C_DRX_N9 AM21 PEX_RX9 GPIO17 R1 VGA_ALERT# 2 7
PEG_PTX_C_DRX_P10 AN23 PEX_RX9_N GPIO18 P3 GPU_OVERT# 3 6
PEX_RX10 GPIO19 (37,45) GPU_OVERT#
PEG_PTX_C_DRX_N10 AM23 P4 XTAL_SSIN 4 5
PEG_PTX_C_DRX_P11 AP23 PEX_RX10_N GPIO20 P1 DGPU_RST_HOLD#
PEG_PTX_C_DRX_N11 AP24 PEX_RX11 GPIO21 +1.05VSG 10K_8P4R_5%
PEG_PTX_C_DRX_P12 AN24 PEX_RX11_N DIS@
PEG_PTX_C_DRX_N12 AM24 PEX_RX12 L31 DIS@
PEG_PTX_C_DRX_P13 AN26 PEX_RX12_N +PLLVDD 1 2 RP37

10U_0603_6.3V6M
PEG_PTX_C_DRX_N13 AM26 PEX_RX13 FBMA-L11-160808300LMA25T_2P SMB_CLK_GPU 1 8

0.1U_0402_16V7K
PEX_RX13_N 1
PEG_PTX_C_DRX_P14 AP26 SMB_DATA_GPU 2 7

22U_0603_6.3V6M

C603
PEX_RX14 1

1
PEG_PTX_C_DRX_N14 AP27 @ VGA_EDID_DATA 3 6

DIS@

DIS@
PEG_PTX_C_DRX_P15 AN27 PEX_RX14_N AK9 VGA_EDID_CLK 4 5

C607

C602
SE095224K00 PEG_PTX_C_DRX_N15 AM27 PEX_RX15 DACA_RED AL10 2
PEX_RX15_N DACA_GREEN 2

2
S CER CAP 0.22U 10V K X5R 0402 AL9 I2C 2.2K_8P4R_5%
DACA_BLUE DIS@

DACs
PEG_CRX_GTX_P0 C601 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P0 AK14
PEG_CRX_GTX_N0 C604 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N0 AJ14 PEX_TX0 AM9 RP38
PEG_CRX_GTX_P1 C606 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P1 AH14 PEX_TX0_N DACA_HSYNC AN9 VGA_CRT_CLK 1 8
1 2 AG14 PEX_TX1 DACA_VSYNC
PEG_CRX_GTX_N1 C609 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N1
PEX_TX1_N under GPU 22U 0603 C941,C945
for layout limitation
VGA_CRT_DATA 2 7
PEG_CRX_GTX_P2 C610 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P2 AK15 HDCP_SDA 3 6
PEG_CRX_GTX_N2 C611 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N2 AJ15 PEX_TX2 AG10 close to AD8 HDCP_SCL 4 5
PEG_CRX_GTX_P3 C612 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P3 AL16 PEX_TX2_N DACA_VDD AP9

PCI EXPRESS
PEG_CRX_GTX_N3 C613 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N3 AK16 PEX_TX3 DACA_VREF AP8 2.2K_8P4R_5%
PEG_CRX_GTX_P4 C614 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P4 AK17 PEX_TX3_N DACA_RSET SW@ @
PEG_CRX_GTX_N4 C615 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N4 AJ17 PEX_TX4 GC6_FB_EN 3
C PEG_CRX_GTX_P5 C616 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P5 AH17 PEX_TX4_N 11.35V_PWR_EN RP39 C
PEX_TX5 1.35V_PWR_EN (45)

2
PEG_CRX_GTX_N5 C617 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N5 AG17 2 GC6_FB_EN 1 8
PEX_TX5_N (18,45,54) DGPU_PWROK
PEG_CRX_GTX_P6 C618 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P6 AK18 DIS@ GPU_EVENT# 2 7
PEG_CRX_GTX_N6 C619 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N6 AJ18 PEX_TX6 D30 R488 DGPU_RST_HOLD# 3 6 V0.2
PEG_CRX_GTX_P7 C620 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P7 AL19 PEX_TX6_N DAN202UT106_SC70-3 100K_0402_5% 4 5
PEG_CRX_GTX_N7 C621 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N7 AK19 PEX_TX7 R4 VGA_CRT_CLK
PEX_TX7_N I2CA_SCL

1
PEG_CRX_GTX_P8 C622 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P8 AK20 R5 VGA_CRT_DATA 10K_8P4R_5%
PEG_CRX_GTX_N8 C623 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N8 AJ20 PEX_TX8 I2CA_SDA DIS@
PEG_CRX_GTX_P9 C624 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P9 AH20 PEX_TX8_N R7 HDCP_SCL
PEG_CRX_GTX_N9 C625 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N9 AG20 PEX_TX9 I2CB_SCL R6 HDCP_SDA RP35
PEG_CRX_GTX_P10 C626 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P10 AK21 PEX_TX9_N I2CB_SDA NVVDD_PSI 1 8
PEX_TX10

I2C
PEG_CRX_GTX_N10 C627 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N10 AJ21 R2 VGA_EDID_CLK (37) JTAG_TRST 2 7
PEG_CRX_GTX_P11 C628 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P11 AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA 3 6
PEX_TX11 I2CC_SDA (37) TESTMODE
PEG_CRX_GTX_N11 C629 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N11 AK22 VGA_CLKREQ#_R 4 5
PEG_CRX_GTX_P12 C630 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P12 AK23 PEX_TX11_N T4 SMB_CLK_GPU
PEG_CRX_GTX_N12 C631 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N12 AJ23 PEX_TX12 I2CS_SCL T3 SMB_DATA_GPU 10K_8P4R_5%
PEG_CRX_GTX_P13 C632 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P13 AH23 PEX_TX12_N I2CS_SDA DIS@
PEG_CRX_GTX_N13 C633 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N13 AG23 PEX_TX13
PEG_CRX_GTX_P14 C634 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P14 AK24 PEX_TX13_N
PEX_TX14 Green CLK
PEG_CRX_GTX_N14 C635 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N14 AJ24
PEG_CRX_GTX_P15 C636 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_P15 AL25 PEX_TX14_N
PEG_CRX_GTX_N15 C637 1 2 DIS@ 0.22U_0402_10V6K PEG_CRX_C_GTX_N15 AK25 PEX_TX15 GCLKDIS@
PEX_TX15_N XTALIN 1 2 CLK_27M_VGA_XIN (27)
AD8 +PLLVDD R516 0_0402_5%
AJ11 PLLVDD
NC AE8 L30 +1.05VSG
AL13 SP_PLLVDD BLM18PG181SN1D_2P
(15) CLK_PEG_VGA PEX_REFCLK
(15) CLK_PEG_VGA# AK13 AD7 +GPU_PLLVDD 1 2 NOGCLKDIS@
VGA_CLKREQ#_R AK12 PEX_REFCLK_N VID_PLLVDD DIS@ Y5 27MHZ_10PF_7V27000050 V0.2

22U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_16V7K

4.7U_0603_6.3V6K
PEX_CLKREQ_N

10P_0402_50V8J
CLK

1 1 1

1
1 @ 2 PEX_TSTCLK_OUT AJ26 H3 XTALIN DIS@ DIS@ DIS@ @ XTALIN 1 3XTAL_OUT

10P_0402_50V8J
NOGCLKDIS@
PEX_TSTCLK_OUT XTAL_IN 1 3
Default unstuffed R401 200_0402_1% PEX_TSTCLK_OUT# AK26 H2 XTAL_OUT

NOGCLKDIS@
PEX_TSTCLK_OUT_N XTAL_OUT 1 GND GND 1
B B

C640

C642

C643

C644
2 2 2

2
DGPU_PEX_RST# AJ12 J4 XTAL_OUTBUFF

C638

C639
AP29 PEX_RST_N XTAL_OUTBUFF H1 XTAL_SSIN 2 4
PEX_TERMP XTAL_SSIN 2 2
2

R402 C640 under GPU

DGPU_PWROK

+3V_PCH 2.49K_0402_1% DIS@

N15P-GT_BGA908
close to ball : AE8,AD7
1
1

R501
10K_0402_5%
+3V3_AON
+3V3_AON
2

DIS@
2

Q33A
VGA_CLKREQ#_R 1 6 CLK_REQ_VGA#
CLK_REQ_VGA# (15)
2N7002KDWH_SOT363-6 2 DIS@
When REFCLK current is below 20mA, don't need C646 2 SW@
1 @ 2 above gate control for CLKREQ_GPU#, and keep 0.1U_0402_25V6K C645
R403 0_0402_5% 0.1U_0402_25V6K
REFCLK free running 1

5
U40
1

5
V0.2 U39

VCC
(14,45) DGPU_HOLD_RST# 1

VCC
IN1 4 SYS_PEX_RST_MON# 1
2 OUT IN1 4 DGPU_PEX_RST#
(14,25,28,31,34) PLT_RST#

GND
IN2 DGPU_RST_HOLD# 2 OUT

GND
Internal Thermal Sensor IN2
MC74VHC1G08DFT2G SC70 5P

3
+3V3_AON DIS@ MC74VHC1G08DFT2G SC70 5P

3
SW@
A A
5

DIS@

SMB_CLK_GPU 4 3
EC_SMB_CK2 (16,31,32)
Q32B 2N7002KDWH_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
2

DIS@
Issued Date 2013/04/02 Deciphered Date 2014/04/02 Title
SMB_DATA_GPU 1 6
Q32A 2N7002KDWH_SOT363-6
EC_SMB_DA2 (16,31,32)
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (1/5) PEG & DAC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 36 of 59
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0
+3VS_DGPU SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED
ROM_SCLK
U30D
ROM_SO +3VS_DGPU RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
Part 4 of 7
AM6
IFPA_TXC +3VS_DGPU
AN6
IFPA_TXC_N 3V3AUX_NC
P8 ROM_SI DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
AP3 AC6
AN3 IFPA_TXD0 NC AJ28
D
IFPA_TXD0_N NC STRAP0 Keep pull-up to 3V3_AON and pull-down to GND foot print and stuff 50K ohm pull-up D
AN5 AJ4
IFPA_TXD1 NC
AM5
IFPA_TXD1_N NC
AJ5 trace width: 16mils STRAP1
AL6 AL11
AK6 IFPA_TXD2 NC C15 differential voltage sensing.
AJ6 IFPA_TXD2_N NC D19 differential signal routing. STRAP2 RESERVED
AH6 IFPA_TXD3 NC D20

NC
IFPA_TXD3_N NC D23 STRAP3
NC D26
AJ9 NC H31 +VGA_CORE STRAP4
AH9 IFPB_TXC NC T8
AP6 IFPB_TXC_N NC V32
AP5 IFPB_TXD4 NC
IFPB_TXD4_N

2
AM7 Pull-up to +3VS
IFPB_TXD5
AL7
IFPB_TXD5_N
R404 SKU Device ID bit5 to bit0 Resistor Values _DGPU Pull-down to Gnd
AN8 DIS@ 100_0402_1%
IFPB_TXD6
AM8
IFPB_TXD6_N 5K 1000 0000
AK8 N15P-GX 0x1392
IFPB_TXD7

1
AL8
IFPB_TXD7_N 10K 1001 0001
L4 VCCSENSE_VGA
VDD_SENSE VCCSENSE_VGA (54)
15K 1010 0010
AK1
AJ1 IFPC_L0
IFPC_L0_N 20K 1011 0011
AJ3 L5 VSSSENSE_VGA
IFPC_L1 GND_SENSE VSSSENSE_VGA (54)
AJ2
IFPC_L1_N 25K 1100 0100
AH3
IFPC_L2
AH4
IFPC_L2_N 30K 1101 0101
AG5 2 DIS@ 1
IFPC_L3
AG4
IFPC_L3_N
R405 100_0402_1% 35K 1110 0110
TEST 45K 1111 0111
AM1 AK11
C AM2 IFPD_L0 TESTMODE TESTMODE (36) C
AM3 IFPD_L0_N AM10 JTAG_TCK
IFPD_L1 JTAG_TCK PAD T51 @
AM4 AM11 JTAG_TDI PAD @
IFPD_L1_N JTAG_TDI T52 +3V3_AON +3VS_DGPU
AL3 AP12 JTAG_TDO PAD @ MULTI LEVEL STRAPS
IFPD_L2 JTAG_TDO T50
AL4 AP11 JTAG_TMS PAD
IFPD_L2_N JTAG_TMS T53 @
AK4 AN11
AK5 IFPD_L3 JTAG_TRST_N JTAG_TRST (36)
IFPD_L3_N

1
10K_0402_1%
49.9K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%
LVDS/TMDS

10K_0402_1%
@ @ @ @ @ @ @

14.7K_0402_1%
AD2 DIS@

R406

R407

R408

R409

R410
AD3 IFPE_L0

R412
AD1 IFPE_L0_N
SERIAL

R439

R413
IFPE_L1

2
AC1
AC2 IFPE_L1_N H6 STRAP0 ROM_SI
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK STRAP1 STRAP3 ROM_SO
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI STRAP2 STRAP4 ROM_SCLK
AC5 IFPE_L3 ROM_SI H7 ROM_SO
IFPE_L3_N ROM_SO

1
4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
AE3 @ @ @ @ @ @ DIS@ DIS@

R414

R415

R416

R417

R418
AE4 IFPF_L0
AF4 IFPF_L0_N
AF5 IFPF_L1
GENERAL

R411

R420

R419
IFPF_L1_N

2
AD4 DIS@
AD5 IFPF_L2 L2 1 2
AG1 IFPF_L2_N BUFRST_N R422 10K_0402_5%
AF1 IFPF_L3 M1 GPU_OVERT#
IFPF_L3_N OVERT GPU_OVERT# (36,45)
J1 MULTI_STRAP_REF0_GND 1 DIS@ 2
MULTI_STRAP_REF0_GND R424 40.2K_0402_1% For X76 (N15P-GX)
AG3
AG2 IFPC_AUX_I2CW_SCL ZZZ3 X76L01@ ZZZ4 X76L03@
B IFPC_AUX_I2CW_SDA_N J2 STRAP0 B
STRAP0 GPU FB Memory DDR5 ROM_SI
J7 STRAP1
AK3 STRAP1 J6 STRAP2
AK2 IFPD_AUX_I2CX_SCL STRAP2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 Samsung 2G K4G20325FD-FC03
J3 STRAP4 X76L02@ PD 5K
STRAP4
10K_0402_1% 15K_0402_1%
AB3 128Mx16
AB4 IFPE_AUX_I2CY_SCL X7654438L01 X7654438L03
IFPE_AUX_I2CY_SDA_N K3
THERMDP Hynix 2G H5GC2H24BFR-T2C
K4 X76L01@ PD 10K
AF3 THERMDN ZZZ5 X76L02@ ZZZ6 X76L04@
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N N15P-GX
Hynix 4G H5GC4H24MFR-T2C
X76L03@ PD 15K
256Mx16 5K_0402_1% 20K_0402_1%
N15P-GT_BGA908
Samsung 4G K4G41325FC-HC03 X7654438L02 X7654438L04
X76L04@ PD 20K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/02 Deciphered Date 2014/04/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (2/5) TMDS/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 37 of 59
5 4 3 2 1
 5 4 3 2 1

MDA[15..0] MDC[15..0]
(41) MDA[15..0] (43) MDC[15..0]
MDA[31..16] MDC[31..16]
(41) MDA[31..16] (43) MDC[31..16]
MDA[47..32] MDC[47..32]
(42) MDA[47..32] (44) MDC[47..32]
MDA[63..48] MDC[63..48]
(42) MDA[63..48] (44) MDC[63..48]

U30B U30C
CMDA[31..0] (41,42) CMDC[31..0] (42,43,44)
Part 2 of 7 Part 3 of 7
D MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0 D
MDA1 M29 FBA_D0 FBA_CMD0 T31 CMDA1 MDC1 E9 FBB_D0 FBB_CMD0 E14 CMDC1
MDA2 L29 FBA_D1 FBA_CMD1 U29 CMDA2 MDC2 G8 FBB_D1 FBB_CMD1 F14 CMDC2
MDA3 M28 FBA_D2 FBA_CMD2 R34 CMDA3 MDC3 F9 FBB_D2 FBB_CMD2 A12 CMDC3
MDA4 N31 FBA_D3 FBA_CMD3 R33 CMDA4 MDC4 F11 FBB_D3 FBB_CMD3 B12 CMDC4
MDA5 P29 FBA_D4 FBA_CMD4 U32 CMDA5 MDC5 G11 FBB_D4 FBB_CMD4 C14 CMDC5
MDA6 R29 FBA_D5 FBA_CMD5 U33 CMDA6 MDC6 F12 FBB_D5 FBB_CMD5 B14 CMDC6
MDA7 P28 FBA_D6 FBA_CMD6 U28 CMDA7 MDC7 G12 FBB_D6 FBB_CMD6 G15 CMDC7
MDA8 J28 FBA_D7 FBA_CMD7 V28 CMDA8 MDC8 G6 FBB_D7 FBB_CMD7 F15 CMDC8
MDA9 H29 FBA_D8 FBA_CMD8 V29 CMDA9 MDC9 F5 FBB_D8 FBB_CMD8 E15 CMDC9
MDA10 J29 FBA_D9 FBA_CMD9 V30 CMDA10 MDC10 E6 FBB_D9 FBB_CMD9 D15 CMDC10
MDA11 H28 FBA_D10 FBA_CMD10 U34 CMDA11 MDC11 F6 FBB_D10 FBB_CMD10 A14 CMDC11
MDA12 G29 FBA_D11 FBA_CMD11 U31 CMDA12 MDC12 F4 FBB_D11 FBB_CMD11 D14 CMDC12
MDA13 E31 FBA_D12 FBA_CMD12 V34 CMDA13 MDC13 G4 FBB_D12 FBB_CMD12 A15 CMDC13
MDA14 E32 FBA_D13 FBA_CMD13 V33 CMDA14 MDC14 E2 FBB_D13 FBB_CMD13 B15 CMDC14
MDA15 F30 FBA_D14 FBA_CMD14 Y32 CMDA15 MDC15 F3 FBB_D14 FBB_CMD14 C17 CMDC15
MDA16 C34 FBA_D15 FBA_CMD15 AA31 CMDA16 MDC16 C2 FBB_D15 FBB_CMD15 D18 CMDC16
MDA17 D32 FBA_D16 FBA_CMD16 AA29 CMDA17 MDC17 D4 FBB_D16 FBB_CMD16 E18 CMDC17
MDA18 B33 FBA_D17 FBA_CMD17 AA28 CMDA18 MDC18 D3 FBB_D17 FBB_CMD17 F18 CMDC18
MDA19 C33 FBA_D18 FBA_CMD18 AC34 CMDA19 MDC19 C1 FBB_D18 FBB_CMD18 A20 CMDC19
MDA20 F33 FBA_D19 FBA_CMD19 AC33 CMDA20 MDC20 B3 FBB_D19 FBB_CMD19 B20 CMDC20
MDA21 F32 FBA_D20 FBA_CMD20 AA32 CMDA21 MDC21 C4 FBB_D20 FBB_CMD20 C18 CMDC21
MDA22 H33 FBA_D21 FBA_CMD21 AA33 CMDA22 MDC22 B5 FBB_D21 FBB_CMD21 B18 CMDC22
MDA23 H32 FBA_D22 FBA_CMD22 Y28 CMDA23 MDC23 C5 FBB_D22 FBB_CMD22 G18 CMDC23
MDA24 P34 FBA_D23 FBA_CMD23 Y29 CMDA24 MDC24 A11 FBB_D23 FBB_CMD23 G17 CMDC24
MDA25 P32 FBA_D24 FBA_CMD24 W31 CMDA25 MDC25 C11 FBB_D24 FBB_CMD24 F17 CMDC25
MDA26 P31 FBA_D25 FBA_CMD25 Y30 CMDA26 MDC26 D11 FBB_D25 FBB_CMD25 D16 CMDC26
FBA_D26 FBA_CMD26 FBB_D26 FBB_CMD26

MEMORY INTERFACE B
MDA27 P33 AA34 CMDA27 MDC27 B11 A18 CMDC27
MDA28 L31 FBA_D27 FBA_CMD27 Y31 CMDA28 MDC28 D8 FBB_D27 FBB_CMD27 D17 CMDC28
MDA29 L34 FBA_D28 FBA_CMD28 Y34 CMDA29 MDC29 A8 FBB_D28 FBB_CMD28 A17 CMDC29
MDA30 L32 FBA_D29 FBA_CMD29 Y33 CMDA30 MDC30 C8 FBB_D29 FBB_CMD29 B17 CMDC30
MDA31 L33 FBA_D30 FBA_CMD30 V31 CMDA31 MDC31 B8 FBB_D30 FBB_CMD30 E17 CMDC31
C MDA32 AG28 FBA_D31 FBA_CMD31 R28 MDC32 F24 FBB_D31 FBB_CMD31 G14 C
MDA33 AF29 FBA_D32 FBA_CMD32 AC28 R427 +1.35VSG MDC33 G23 FBB_D32 FBB_CMD32 G20 R428 +1.35VSG
MEMORY INTERFACE

MDA34 AG29 FBA_D33 FBA_CMD33 R32 FBA_DEBUG0 2 @ 1 60.4_0402_1% MDC34 E24 FBB_D33 FBB_CMD33 C12 FBC_DEBUG0 2 @ 1 60.4_0402_1%
MDA35 AF28 FBA_D34 FBA_CMD34 AC32 FBA_DEBUG1 2 @ 1 MDC35 G24 FBB_D34 FBB_CMD34 C20 FBC_DEBUG1 2 @ 1
MDA36 AD30 FBA_D35 FBA_CMD35 R429 60.4_0402_1% MDC36 D21 FBB_D35 FBB_CMD35 R430 60.4_0402_1%
MDA37 AD29 FBA_D36 MDC37 E21 FBB_D36
MDA38 AC29 FBA_D37 MDC38 G21 FBB_D37
MDA39 AD28 FBA_D38 MDC39 F21 FBB_D38
MDA40 AJ29 FBA_D39 MDC40 G27 FBB_D39
MDA41 AK29 FBA_D40 MDC41 D27 FBB_D40
MDA42 AJ30 FBA_D41 MDC42 G26 FBB_D41
MDA43 AK28 FBA_D42 MDC43 E27 FBB_D42
MDA44 AM29 FBA_D43 MDC44 E29 FBB_D43
MDA45 AM31 FBA_D44 R30 MDC45 F29 FBB_D44 D12
FBA_D45 FBA_CLK0 CLKA0 (41) FBB_D45 FBB_CLK0 CLKC0 (43)
MDA46 AN29 R31 CLKA0# (41) MDC46 E30 E12 CLKC0# (43)
MDA47 AM30 FBA_D46 FBA_CLK0_N AB31 MDC47 D30 FBB_D46 FBB_CLK0_N E20
FBA_D47 FBA_CLK1 CLKA1 (42) FBB_D47 FBB_CLK1 CLKC1 (44)
MDA48 AN31 AC31 CLKA1# (42) MDC48 A32 F20 CLKC1# (44)
MDA49 AN32 FBA_D48 FBA_CLK1_N MDC49 C31 FBB_D48 FBB_CLK1_N
FBA_D49 FBB_D49
A

MDA50 AP30 MDC50 C32

MDA51 AP32 FBA_D50 MDC51 B32 FBB_D50
MDA52 AM33 FBA_D51 K31 MDC52 D29 FBB_D51 F8
FBA_D52 FBA_WCK01 FBA_WCK01 (41) FBB_D52 FBB_WCK01 FBB_WCK01 (43)
MDA53 AL31 L30 FBA_WCK01# (41) MDC53 A29 E8 FBB_WCK01# (43)
MDA54 AK33 FBA_D53 FBA_WCK01_N H34 MDC54 C29 FBB_D53 FBB_WCK01_N A5
FBA_D54 FBA_WCK23 FBA_WCK23 (41) FBB_D54 FBB_WCK23 FBB_WCK23 (43)
MDA55 AK32 J34 FBA_WCK23# (41) MDC55 B29 A6 FBB_WCK23# (43)
MDA56 AD34 FBA_D55 FBA_WCK23_N AG30 MDC56 B21 FBB_D55 FBB_WCK23_N D24
FBA_D56 FBA_WCK45 FBA_WCK45 (42) FBB_D56 FBB_WCK45 FBB_WCK45 (44)
MDA57 AD32 AG31 FBA_WCK45# (42) MDC57 C23 D25 FBB_WCK45# (44)
MDA58 AC30 FBA_D57 FBA_WCK45_N AJ34 MDC58 A21 FBB_D57 FBB_WCK45_N B27
FBA_D58 FBA_WCK67 FBA_WCK67 (42) FBB_D58 FBB_WCK67 FBB_WCK67 (44)
MDA59 AD33 AK34 FBA_WCK67# (42) MDC59 C21 C27 FBB_WCK67# (44)
MDA60 AF31 FBA_D59 FBA_WCK67_N MDC60 B24 FBB_D59 FBB_WCK67_N
MDA61 AG34 FBA_D60 MDC61 C24 FBB_D60
MDA62 AG32 FBA_D61 MDC62 B26 FBB_D61
MDA63 AG33 FBA_D62 J30 MDC63 C26 FBB_D62 D6 +FB_PLLAVDD300mA DIS@ +1.05VSG
B FBA_D63 NC J31 FBB_D63 NC D7 L32 B
(41) DQMA[3..0] NC (43) DQMC[3..0] NC
DQMA0 P30 J32 DQMC0 E11 C6 +FB_PLLAVDD 1 2
DQMA1 F31 FBA_DQM0 NC J33 DQMC1 E3 FBB_DQM0 NC B6 FBMA-L11-160808300LMA25T_2P

22U_0805_6.3V6M
DQMA2 F34 FBA_DQM1 NC AH31 DQMC2 A3 FBB_DQM1 NC F26

DIS@ C647
FBA_DQM2 NC FBB_DQM2 NC 1
(42) DQMA[7..4]
DQMA3 M32
FBA_DQM3 NC
AJ31
(44) DQMC[7..4]
DQMC3 C9
FBB_DQM3 NC
E26 Or use same as L10 PN: SM01000FE00
DQMA4 AD31 AJ32 DQMC4 F23 A26
DQMA5 AL29 FBA_DQM4 NC AJ33 DQMC5 F27 FBB_DQM4 NC A27
DQMA6 AM32 FBA_DQM5 NC DQMC6 C30 FBB_DQM5 NC 2
DQMA7 AF34 FBA_DQM6 DQMC7 A24 FBB_DQM6
FBA_DQM7 FBB_DQM7
(41) DQSA[3..0] (43) DQSC[3..0]
DQSA0 M31 E1 GC6_FB_EN_R DQSC0 D10
FBA_DQS_WP0 FB_CLAMP FBB_DQS_WP0
DQSA1 G31
FBA_DQS_WP1
DQSC1 D5
FBB_DQS_WP1
L15= 30ohm
DQSA2 E33
FBA_DQS_WP2 Under GPU DQSC2 C3
FBB_DQS_WP2
DQSA3 M33 DQSC3 B9
(42) DQSA[7..4]
DQSA4 AE31 FBA_DQS_WP3 K27 close to ball : K27 (44) DQSC[7..4]
DQSC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
DQSA5 AK30 FBA_DQS_WP4 FB_DLL_AVDD C648 DIS@ DQSC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD
FBA_DQS_WP5 FBB_DQS_WP5 100mA
DQSA6 AN33 1 2 DQSC6 B30
DQSA7 AF33 FBA_DQS_WP6 0.1U_0402_16V7K DQSC7 A23 FBB_DQS_WP6

0.1U_0402_16V7K
FBA_DQS_WP7 U27 +FB_PLLAVDD FBB_DQS_WP7
FBA_PLL_AVDD 1
M30 D9

C650
H30 FBA_DQS_RN0 1 2 E4 FBB_DQS_RN0 DIS@
E34 FBA_DQS_RN1 C649 0.1U_0402_16V7K B2 FBB_DQS_RN1
M34 FBA_DQS_RN2 H26 DIS@ A9 FBB_DQS_RN2 2
AF30 FBA_DQS_RN3 FB_VREF D22 FBB_DQS_RN3
FBA_DQS_RN4 FBB_DQS_RN4
AK31
FBA_DQS_RN5 Under GPU D28
FBB_DQS_RN5
AM34
FBA_DQS_RN6 close to ball : U27 A30
FBB_DQS_RN6 Under GPU
AF32 B23
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17

N15P-GT_BGA908 N15P-GT_BGA908
A GC6_FB_EN_R 1 @ 2 A
GC6_FB_EN (14,36)
R426 0_0402_5%
2

DIS@ R518
Near GPU 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

1

Issued Date 2013/04/02 Deciphered Date 2014/04/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (3/5) TMDS/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 38 of 59
5 4 3 2 1
 5 4 3 2 1

Under GPU Near GPU +1.05VSG

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

4.7U_0603_6.3V6K
D D

DIS@ C652

DIS@ C653

DIS@ C670

DIS@ C671

DIS@ C654

DIS@ C655
1U_0402_6.3V6K
1 1 1 1 1 1
U30E

DIS@ C651
1
+1.35VSG Under GPU Part 5 of 7
2 2 2 2 2 2
9000mA 2
AA27 AG19
AA30 FBVDDQ_0 PEX_IOVDD_0 AG21

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
AB27 FBVDDQ_1 PEX_IOVDD_1 AG22
C656

C657

C658

C672

C659

C660
1 1 1 1 1 1 FBVDDQ_2 PEX_IOVDD_2
AB33 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
2 2 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 Under GPU Near GPU +1.05VSG
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
B13 FBVDDQ_8 PEX_IOVDDQ_0 AG15

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_9 PEX_IOVDDQ_1
Under GPU B19 AG16

DIS@ C673

DIS@ C661

DIS@ C662

DIS@ C663

DIS@ C664

DIS@ C674

DIS@ C665
FBVDDQ_11 PEX_IOVDDQ_2 1 1 1 1 1 1 1
E13 AG18
E19 FBVDDQ_12 PEX_IOVDDQ_3 AG25
H10 FBVDDQ_14 PEX_IOVDDQ_4 AH15
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

H11 FBVDDQ_15 PEX_IOVDDQ_5 AH18 2 2 2 2 2 2 2

C666

C675

C667

C676

C668

C669
1 1 1 1 1 1 FBVDDQ_16 PEX_IOVDDQ_6
H12 AH26
H13 FBVDDQ_17 PEX_IOVDDQ_7 AH27
H14 FBVDDQ_18 PEX_IOVDDQ_8 AJ27
DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
2 2 2 2 2 2 H18 FBVDDQ_19 PEX_IOVDDQ_9 AK27
H19 FBVDDQ_22 PEX_IOVDDQ_10 AL27
H20 FBVDDQ_23 PEX_IOVDDQ_11 AM28

POWER
H21 FBVDDQ_24 PEX_IOVDDQ_12 AN28
Near GPU H22 FBVDDQ_25 PEX_IOVDDQ_13
H23 FBVDDQ_26 +3V3_AON
FBVDDQ_27
H24 Near GPU
330U 2V D2 LESR9M EEFSX H1.9

N14P_GB4-128 H8 FBVDDQ_28 AH12

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

DG-6246_V04 H9 FBVDDQ_29 PEX_PLL_HVDD

DIS@ C677

DIS@ C678

DIS@ C679

DIS@ C680

1U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
1 1 1 1 FBVDDQ_30
C L27 @ 1 2 C
@ C790

C681

C682

C683
1 FBVDDQ_31 1 1 1
M27 C684 0.1U_0402_16V7K
SGA20331E10

+ N27 FBVDDQ_32 AG12

2 2 2 2 P27 FBVDDQ_33 PEX_SVDD_3V3

DIS@

DIS@

DIS@
R27 FBVDDQ_34 @ 1 2 2 2 2 @
2 T27 FBVDDQ_35 C685 0.1U_0402_16V7K RP40
T30 FBVDDQ_36 AG26 IFPEF_PLLVDD 1 8
T33 FBVDDQ_37 PEX_PLLVDD IFPA_IOVDD 2 7
Y27 FBVDDQ_38 IFPC_IOVDD 3 6
FBVDDQ_43 +1.05VSG IFPC_PLLVDD 4 5
3V3_AON
J8 Under GPU Near GPU
K8 2.2K_8P4R_5%
3V3_AON L8

0.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
B16 3V3_MAIN M8 @

DIS@ C686

DIS@ C687

DIS@ C688
FBVDDQ_AON 3V3_MAIN 1 1 1
E16 RP41
H15 FBVDDQ_AON IFPD_IOVDD 1 8
H16 FBVDDQ_AON IFPD_PLLVDD 2 7
V27 FBVDDQ_AON AH8 IFPAB_PLLVDD 2 2 2 IFPAB_PLLVDD3 6
W27 FBVDDQ_AON IFPAB_PLLVDD AJ8 IFPB_IOVDD 4 5
W30 FBVDDQ_AON IFPAB_RSET
W33 FBVDDQ_AON AG8 IFPA_IOVDD 10K_8P4R_5%
FBVDDQ_AON IFPA_IOVDD AG9 IFPB_IOVDD
IFPB_IOVDD @
RP42
AF7 IFPC_PLLVDD Under GPU (one per pin) Near GPU +3V3_AON IFPE_IOVDD 1 8
+1.35VSG IFPC_PLLVDD AF8 IFPF_IOVDD 2 7
IFPC_RSET 3 6

0.1U_0402_16V7K
2 @ 1 FB_VDDQ_SENSE F1 AF6 IFPC_IOVDD 4 5

0.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
R431 10_0402_5% FB_VDDQ_SENSE IFPC_IOVDD

DIS@ C694

DIS@ C705

DIS@ C695

DIS@ C689
1 1 1 1
10K_8P4R_5%
2 DIS@ 1 FB_GND_SENSE F2 AG7 IFPD_PLLVDD
+1.35VSG R432 10_0402_5% FB_GND_SENSE IFPD_PLLVDD AN2
B NC 2 2 2 2 B
2 DIS@ 1 FB_CAL_PD_VDDQ J27 AG6 IFPD_IOVDD
R433 40.2_0402_1% FB_CAL_PD_VDDQ IFPD_IOVDD

2 DIS@ 1 FB_CAL_PU_GND H27 AB8 IFPEF_PLLVDD

R434 40.2_0402_1% FB_CAL_PU_GND IFPEF_PLVDD AD6
IFPEF_RSET +3VS_DGPU
Under GPU (one per pin) Near GPU
2 DIS@ 1 FB_CAL_TERM_GND H25 AC7 IFPE_IOVDD
R435 60.4_0402_1% FB_CAL_TERM_GND IFPE_IOVDD AC8 IFPF_IOVDD
IFPF_IOVDD

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
Place near balls

C690

C691

C692

C693
1 1 1 1

DIS@

DIS@

DIS@

DIS@
N15P-GT_BGA908 2 2 2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/02 Deciphered Date 2014/04/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (4/5) POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 39 of 59
5 4 3 2 1
 5 4 3 2 1

U30F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
+VGA_CORE U30G +VGA_CORE AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
Part 7 of 7 V17 AB12 GND_4 GND_104 E25
D AA12 VDD_56 V18 AB14 GND_5 GND_105 E5 D
AA14 VDD_0 VDD_57 V20 AB16 GND_6 GND_106 E7
AA16 VDD_1 VDD_58 V22 AB19 GND_7 GND_107 F28
AA19 VDD_2 VDD_59 W12 AB2 GND_8 GND_108 F7
AA21 VDD_3 VDD_60 W14 AB21 GND_9 GND_109 G10
AA23 VDD_4 VDD_61 W16 A33 GND_10 GND_110 G13
AB13 VDD_5 VDD_62 W19 AB23 GND_11 GND_111 G16
AB15 VDD_6 VDD_63 W21 AB28 GND_12 GND_112 G19
AB17 VDD_7 VDD_64 W23 AB30 GND_13 GND_113 G2
AB18 VDD_8 VDD_65 Y13 AB32 GND_14 GND_114 G22
AB20 VDD_9 VDD_66 Y15 AB5 GND_15 GND_115 G25
AB22 VDD_10 VDD_67 Y17 AB7 GND_16 GND_116 G28
AC12 VDD_11 VDD_68 Y18 AC13 GND_17 GND_117 G3
AC14 VDD_12 VDD_69 Y20 AC15 GND_18 GND_118 G30
AC16 VDD_13 VDD_70 Y22 AC17 GND_19 GND_119 G32
AC19 VDD_14 VDD_71 AC18 GND_20 GND_120 G33
AC21 VDD_15 AA13 GND_21 GND_121 G5
AC23 VDD_16 U1 AC20 GND_22 GND_122 G7
M12 VDD_17 XVDD_1 U2 AC22 GND_23 GND_123 K2
M14 VDD_18 XVDD_2 U3 AE2 GND_24 GND_124 K28
M16 VDD_19 XVDD_3 U4 AE28 GND_25 GND_125 K30
VDD_20 XVDD_4 GND_26 GND_126

POWER
M19 U5 AE30 K32
M21 VDD_21 XVDD_5 U6 AE32 GND_27 GND_127 K33
M23 VDD_22 XVDD_6 U7 AE33 GND_28 GND_128 K5
N13 VDD_23 XVDD_7 U8 AE5 GND_29 GND_129 K7
N15 VDD_24 XVDD_8 AE7 GND_30 GND_130 M13
N17 VDD_25 AH10 GND_31 GND_131 M15
N18 VDD_26 V1 AA15 GND_32 GND_132 M17
N20 VDD_27 XVDD_9 V2 AH13 GND_33 GND_133 M18
N22 VDD_28 XVDD_10 V3 AH16 GND_34 GND_134 M20
P12 VDD_29 XVDD_11 V4 AH19 GND_35 GND_135 M22
P14 VDD_30 XVDD_12 V5 AH2 GND_36 GND_136 N12
C P16 VDD_31 XVDD_13 V6 AH22 GND_37 GND_137 N14 C
P19 VDD_32 XVDD_14 V7 AH24 GND_38 GND_138 N16
P21 VDD_33 XVDD_15 V8 AH28 GND_39 GND_139 N19
P23 VDD_34 XVDD_16 AH29 GND_40 GND_140 N2
R13 VDD_35 AH30 GND_41 GND_141 N21
R15 VDD_36 W2 AH32 GND_42 GND_142 N23
R17 VDD_37 XVDD_17 W3 AH33 GND_43 GND_143 N28

GND
R18 VDD_38 XVDD_18 W4 AH5 GND_44 GND_144 N30
R20 VDD_39 XVDD_19 W5 AH7 GND_45 GND_145 N32
R22 VDD_40 XVDD_20 W7 AJ7 GND_46 GND_146 N33
T12 VDD_41 XVDD_21 W8 AK10 GND_47 GND_147 N5
T14 VDD_42 XVDD_22 AK7 GND_48 GND_148 N7
T16 VDD_43 AL12 GND_49 GND_149 P13
T19 VDD_44 Y1 AL14 GND_50 GND_150 P15
T21 VDD_45 NC Y2 AL15 GND_51 GND_151 P17
T23 VDD_46 NC Y3 AL17 GND_52 GND_152 P18
U13 VDD_47 NC Y4 AL18 GND_53 GND_153 P20
U15 VDD_48 XVDD_23 Y5 AL2 GND_54 GND_154 P22
U17 VDD_49 XVDD_24 Y6 AL20 GND_55 GND_155 R12
U18 VDD_50 XVDD_25 Y7 AL21 GND_56 GND_156 R14
U20 VDD_51 XVDD_26 Y8 AL23 GND_57 GND_157 R16
U22 VDD_52 XVDD_27 AL24 GND_58 GND_158 R19
V13 VDD_53 AL26 GND_59 GND_159 R21
V15 VDD_54 AA1 AL28 GND_60 GND_160 R23
VDD_55 NC AA2 AL30 GND_61 GND_161 T13
NC AA3 AL32 GND_62 GND_162 T15
NC AA4 AL33 GND_63 GND_163 T17
NC AA5 AL5 GND_64 GND_164 T18
NC AA6 AM13 GND_65 GND_165 T2
NC AA7 AM16 GND_66 GND_166 T20
NC AA8 AM19 GND_67 GND_167 T22
NC AM22 GND_68 GND_168 AG11
B AM25 GND_69 GND_169 T28 B
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
N15P-GT_BGA908 AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
AN19 GND_74 GND_174 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W32
A GND_OPT A

N15P-GT_BGA908

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/02 Deciphered Date 2014/04/02 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (5/5) POWER/ GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 40 of 59
5 4 3 2 1
 5 4 3 2 1

MIRROR
NORMAL U32

Memory Partition A - Lower 16 bits U31

MF=0 MF=1 MF=1 MF=0

MF=0 MF=1 MF=1 MF=0

A4 MDA24
A4 MDA0 DQSA3 C2 DQ24 DQ0 A2 MDA25

VRAM DDR5 chips DQSA0

DQSA2
C2
C13
R13
EDC0
EDC1
EDC3
EDC2
DQ24
DQ25
DQ26
DQ0
DQ1
DQ2
A2
B4
B2
MDA1
MDA2
MDA3
DQSA1
C13
R13
R2
EDC0
EDC1
EDC2
EDC3
EDC2
EDC1
DQ25
DQ26
DQ27
DQ1
DQ2
DQ3
B4
B2
E4
MDA26
MDA27
MDA28
Mode H
Address 0..31
Mode H
Address 32..63
EDC2 EDC1 DQ27 DQ3 EDC3 EDC0 DQ28 DQ4
R2 E4 MDA4 E2 MDA29 CMD0 CS* CMD16 CS*
128Mx16 GDDR5 *8==>2GB EDC3 EDC0 DQ28
DQ29
DQ4
DQ5
E2 MDA5 DQ29
DQ30
DQ5
DQ6
F4 MDA30
DQ30 DQ6
F4 MDA6 DQMA3 D2
DBI0# DBI3# DQ31 DQ7
F2 MDA31 CMD1 A3_BA3 CMD17 A3_BA3
DQMA0 D2 F2 MDA7 D13 A11

D
256Mx16 GDDR5 *8==>4GB DQMA2
D13
P13
DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11
A13
DQMA1 P13
P2
DBI1#
DBI2#
DBI2#
DBI1#
DQ16
DQ17
DQ8
DQ9
A13
B11
CMD2 A2_BA0 CMD18 A2_BA0 D
DBI2# DBI1# DQ17 DQ9 DBI3# DBI0# DQ18 DQ10
P2
DBI3# DBI0# DQ18 DQ10
B11
DQ19 DQ11
B13 CMD3 A4_BA2 CMD19 A4_BA2
B13 CLKA0 J12 E11
DQ19 DQ11 CK DQ20 DQ12
CLKA0 J12
CK DQ20 DQ12
E11 CLKA0# J11
CK# DQ21 DQ13
E13 CMD4 A5_BA1 CMD20 A5_BA1
CLKA0# J11 E13 CMDA14 J3 F11
CK# DQ21 DQ13 CKE# DQ22 DQ14
CMDA14 J3
CKE# DQ22 DQ14
F11
DQ23 DQ15
F13 CMD5 WE* CMD21 WE*
F13 CMDA9 J5 U11 MDA8
DQ23 DQ15 A12/A13 DQ8 DQ16
CMDA9 J5
A12/A13 DQ8 DQ16
U11 MDA16
DQ9 DQ17
U13 MDA9 CMD6 A7_A8 CMD22 A7_A8
U13 MDA17 CMDA10 K4 T11 MDA10
DQ9 DQ17 A8/A7 A10/A0 DQ10 DQ18
CMDA6 K4
A8/A7 A10/A0 DQ10 DQ18
T11 MDA18 CMDA11 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDA11 CMD7 A6_A11 CMD23 A6_A11
CMDA7 K5 T13 MDA19 CMDA1 K10 N11 MDA12
DQMA[7..0] A11/A6 A9/A1 DQ11 DQ19 BA1/A5 BA3/A3 DQ12 DQ20
(38,42) DQMA[7..0]
CMDA4 K10
BA1/A5 BA3/A3 DQ12 DQ20
N11 MDA20 CMDA2 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDA13 CMD8 ABI* CMD24 ABI*
CMDA3 K11 N13 MDA21 M11 MDA14
CMDA[31..0] BA2/A4 BA0/A2 DQ13 DQ21 DQ14 DQ22
(38,42) CMDA[31..0] DQ14 DQ22
M11 MDA22 CMDA4 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDA15 CMD9 A12_RFU CMD25 A12_RFU
CMDA1 H10 M13 MDA23 CMDA3 H11 U4
DQSA[7..0] BA3/A3 BA1/A5 DQ15 DQ23 +1.35VSG BA0/A2 BA2/A4 DQ0 DQ24
(38,42) DQSA[7..0]
CMDA2 H11
BA0/A2 BA2/A4 DQ0 DQ24
U4 CMDA7 H5
A9/A1 A11/A6 DQ1 DQ25
U2 CMD10 A0_A10 CMD26 A0_A10
CMDA11 H5 U2 CMDA6 H4 T4
MDA[63..0] A9/A1 A11/A6 DQ1 DQ25 A10/A0 A8/A7 DQ2 DQ26
(38,42) MDA[63..0]
CMDA10 H4
A10/A0 A8/A7 DQ2 DQ26
T4
DQ3 DQ27
T2 CMD11 A1_A9 CMD27 A1_A9

2
T2 N4
DQ3 DQ27 DQ4 DQ28
DQ4 DQ28
N4 R438 A5
NC DQ5 DQ29
N2 CMD12 RAS* CMD28 RAS*
A5 N2 1K_0402_1% DIS@ U5 M4
NC DQ5 DQ29 NC DQ6 DQ30
U5
NC DQ6 DQ30
M4
DQ7 DQ31
M2 CMD13 RST* CMD29 RST*
M2
DQ7 DQ31

1
J1
MF
+1.35VSG CMD14 CK1* CMD30 CK1*
R436 DIS@ 1 2 1K_0402_1% MF0 J1 +1.35VSG SEN0 J10
MF SEN
R437 DIS@ 1 2 1K_0402_1% SEN0 J10
SEN
1 DIS@ 2 ZQ1 J13
ZQ VDDQ
B1 CMD15 CAS* CMD31 CAS*
R440 DIS@ 1 2 121_0402_1% ZQ0 J13 B1 R441 121_0402_1% D1
ZQ VDDQ VDDQ
VDDQ
D1
VDDQ
F1 CMD32 NO USED
F1 CMDA8 J4 M1
VDDQ ABI# VDDQ
CMDA8 J4
ABI# VDDQ
M1 CMDA15 G3
RAS# CAS# VDDQ
P1 CMD33 NO USED
CMDA12 G3 P1 CMDA5 G12 T1
RAS# CAS# VDDQ CS# WE# VDDQ
CMDA0 G12
CS# WE# VDDQ
T1 CMDA12 L3
CAS# RAS# VDDQ
G2 CMD34 Debug0
C +1.35VSG CMDA15 L3 G2 CMDA0 L12 L2 C
CAS# RAS# VDDQ WE# CS# VDDQ
CMDA5 L12
WE# CS# VDDQ
L2
VDDQ
B3 CMD35 Debug1
B3 D3
VDDQ VDDQ
1

D3 F3
R492 VDDQ F3 FBA_WCK23# D5 VDDQ H3
549_0402_1% D5 VDDQ H3 FBA_WCK23 D4 WCK01# WCK23# VDDQ K3
(38) FBA_WCK01# WCK01# WCK23# VDDQ WCK01 WCK23 VDDQ
DIS@ (38) FBA_WCK01 D4 K3 M3
WCK01 WCK23 VDDQ M3 FBA_WCK01# P5 VDDQ P3
VDDQ WCK23# WCK01# VDDQ
2

(38) FBA_WCK23# P5 P3 FBA_WCK01 P4 T3

P4 WCK23# WCK01# VDDQ T3 WCK23 WCK01 VDDQ E5
FBA_VREFC (42) (38) FBA_WCK23 WCK23 WCK01 VDDQ VDDQ
E5 N5
VDDQ N5 A10 VDDQ E10
VDDQ VREFD VDDQ
1

A10 E10 U10 N10

R498 R494 DIS@ U10 VREFD VDDQ N10 FBA_VREFC J14 VREFD VDDQ B12
1.33K_0402_1% 2 1 FBA_VREFC J14 VREFD VDDQ B12 VREFC VDDQ D12
931_0402_1% VREFC VDDQ VDDQ
DIS@ DIS@ C761 820P_0402_25V8K D12 F12
VDDQ F12 VDDQ H12
VDDQ VDDQ
2

H12 CMDA13 J2 K12

CMDA13 J2 VDDQ K12 RESET# VDDQ M12
RESET# VDDQ VDDQ
6

M12 P12
Q37A VDDQ P12 VDDQ T12
VDDQ T12 VDDQ G13
2 DIS@ VDDQ G13 VDDQ L13
(36,43) VRAM_VREF_CTL VDDQ VDDQ
L13 B14
2N7002KDWH_SOT363-6 VDDQ B14 VDDQ D14
VDDQ VDDQ
1

D14 F14
100K_0402_5%

+1.35VSG
VDDQ VDDQ
1

+1.35VSG F14 M14

VDDQ M14 G1 VDDQ P14
R500

DIS@
G1 VDDQ P14 L1 VDD VDDQ T14
L1 VDD VDDQ T14 G4 VDD VDDQ
G4 VDD VDDQ L4 VDD
VDD VDD
2

L4 C5 A1
B C5 VDD A1 R5 VDD VSSQ C1 B
R5 VDD VSSQ C1 C10 VDD VSSQ E1
C10 VDD VSSQ E1 R10 VDD VSSQ N1
R10 VDD VSSQ N1 D11 VDD VSSQ R1 +1.35VSG
D11 VDD VSSQ R1 G11 VDD VSSQ U1
CLKA0 G11 VDD VSSQ U1 L11 VDD VSSQ H2
(38) CLKA0 VDD VSSQ VDD VSSQ
L11 H2 P11 K2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
VDD VSSQ VDD VSSQ
1

P11 K2 G14 A3

10U_0805_25V6K

10U_0805_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DIS@ G14 VDD VSSQ A3 L14 VDD VSSQ C3

DIS@ C696

DIS@ C697

DIS@ C698

DIS@ C699

DIS@ C700

DIS@ C701

DIS@ C702

DIS@ C703

DIS@ C704
VDD VSSQ VDD VSSQ 1 1 1 1 1 1 1

1
R487 L14 C3 E3
80.6_0402_1% VDD VSSQ E3 VSSQ N3
VSSQ N3 VSSQ R3
VSSQ VSSQ
2

2
CLKA0# R3 H1 U3 2 2 2 2 2 2 2
(38) CLKA0# VSSQ VSS VSSQ
H1 U3 K1 C4
K1 VSS VSSQ C4 B5 VSS VSSQ R4
B5 VSS VSSQ R4 G5 VSS VSSQ F5
G5 VSS VSSQ F5 L5 VSS VSSQ M5
L5 VSS VSSQ M5 T5 VSS VSSQ F10
T5 VSS VSSQ F10 B10 VSS VSSQ M10
B10 VSS VSSQ M10 D10 VSS VSSQ C11 +1.35VSG
D10 VSS VSSQ C11 G10 VSS VSSQ R11
G10 VSS VSSQ R11 L10 VSS VSSQ A12
L10 VSS VSSQ A12 P10 VSS VSSQ C12
P10 VSS VSSQ C12 T10 VSS VSSQ E12

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
T10 VSS VSSQ E12 H14 VSS VSSQ N12

DIS@ C708

DIS@ C709

DIS@ C710

DIS@ C711

DIS@ C712

DIS@ C713

DIS@ C714
VSS VSSQ VSS VSSQ 1 1 1 1 1 1 2
H14 N12 K14 R12
K14 VSS VSSQ R12 VSS170-BALL VSSQ U12
VSS170-BALL VSSQ U12 VSSQ H13
VSSQ H13 SGRAM GDDR5 VSSQ K13 2 2 2 2 2 2 1
SGRAM GDDR5 VSSQ K13 VSSQ A14
VSSQ A14 VSSQ C14
VSSQ C14 VSSQ E14
A VSSQ E14 VSSQ N14 A
VSSQ N14 VSSQ R14
VSSQ R14 VSSQ U14
VSSQ U14 VSSQ
VSSQ @ K4G41325FC-HC04_FBGA170~D
@ K4G41325FC-HC04_FBGA170~D

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/02 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 1/4
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 41 of 59
5 4 3 2 1
 5 4 3 2 1

NORMAL MIRROR
U33 U34

Memory Partition A - Upper 16 bits MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0

A4 MDA32 A4 MDA56
DQSA4 C2 DQ24 DQ0 A2 MDA33 DQSA7 C2 DQ24 DQ0 A2 MDA57
C13 EDC0 EDC3 DQ25 DQ1 B4 C13 EDC0 EDC3 DQ25 DQ1 B4
EDC1 EDC2 DQ26 DQ2
MDA34
EDC1 EDC2 DQ26 DQ2
MDA58 Mode H Mode H
DQSA6 R13 B2 MDA35 DQSA5 R13 B2 MDA59 0..31 32..63
VRAM DDR5 chips EDC2 EDC1 DQ27 DQ3 EDC2 EDC1 DQ27 DQ3 Address Address
R2 E4 MDA36 R2 E4 MDA60
EDC3 EDC0 DQ28 DQ4 EDC3 EDC0 DQ28 DQ4
DQ29 DQ5
E2 MDA37
DQ29 DQ5
E2 MDA61 CMD0 CS* CMD16 CS*
F4 MDA38 F4 MDA62
DQ30 DQ6 DQ30 DQ6
DQMA4 D2 F2 MDA39 DQMA7 D2 F2 MDA63 CMD1 A3_BA3 CMD17 A3_BA3
128Mx16 GDDR5 *8==>2GB D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11 D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11
D DQMA6 P13
DBI2# DBI1# DQ17 DQ9
A13 DQMA5 P13
DBI2# DBI1# DQ17 DQ9
A13 CMD2 A2_BA0 CMD18 A2_BA0 D
P2 B11 P2 B11
256Mx16 GDDR5 *8==>4GB CLKA1 J12
DBI3# DBI0# DQ18
DQ19
DQ10
DQ11
B13
E11 CLKA1 J12
DBI3# DBI0# DQ18
DQ19
DQ10
DQ11
B13
E11
CMD3 A4_BA2 CMD19 A4_BA2
CK DQ20 DQ12 CK DQ20 DQ12
CLKA1# J11
CK# DQ21 DQ13
E13 CLKA1# J11
CK# DQ21 DQ13
E13 CMD4 A5_BA1 CMD20 A5_BA1
CMDA30 J3 F11 CMDA30 J3 F11
CKE# DQ22 DQ14 CKE# DQ22 DQ14
DQ23 DQ15
F13
DQ23 DQ15
F13 CMD5 WE* CMD21 WE*
CMDA25 J5 U11 MDA48 CMDA25 J5 U11 MDA40
DQSA[7..0] A12/A13 DQ8 DQ16 A12/A13 DQ8 DQ16
(38,41) DQSA[7..0] DQ9 DQ17
U13 MDA49
DQ9 DQ17
U13 MDA41 CMD6 A7_A8 CMD22 A7_A8
CMDA22 K4 T11 MDA50 CMDA26 K4 T11 MDA42
DQMA[7..0] A8/A7 A10/A0 DQ10 DQ18 A8/A7 A10/A0 DQ10 DQ18
(38,41) DQMA[7..0]
CMDA23 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDA51 CMDA27 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDA43 CMD7 A6_A11 CMD23 A6_A11
CMDA20 K10 N11 MDA52 CMDA17 K10 N11 MDA44
MDA[63..0] BA1/A5 BA3/A3 DQ12 DQ20 BA1/A5 BA3/A3 DQ12 DQ20
(38,41) MDA[63..0]
CMDA19 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDA53 CMDA18 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDA45 CMD8 ABI* CMD24 ABI*
M11 MDA54 M11 MDA46
CMDA[31..0] DQ14 DQ22 DQ14 DQ22
(38,41) CMDA[31..0]
CMDA17 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDA55 CMDA20 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDA47 CMD9 A12_RFU CMD25 A12_RFU
CMDA18 H11 U4 CMDA19 H11 U4
BA0/A2 BA2/A4 DQ0 DQ24 +1.35VSG BA0/A2 BA2/A4 DQ0 DQ24
CMDA27 H5
A9/A1 A11/A6 DQ1 DQ25
U2 CMDA23 H5
A9/A1 A11/A6 DQ1 DQ25
U2 CMD10 A0_A10 CMD26 A0_A10
CMDA26 H4 T4 CMDA22 H4 T4
A10/A0 A8/A7 DQ2 DQ26 A10/A0 A8/A7 DQ2 DQ26
DQ3 DQ27
T2
DQ3 DQ27
T2 CMD11 A1_A9 CMD27 A1_A9

2
N4 N4
DQ4 DQ28 DQ4 DQ28
A5
NC DQ5 DQ29
N2 R447 A5
NC DQ5 DQ29
N2 CMD12 RAS* CMD28 RAS*
U5 M4 DIS@ 1K_0402_1% U5 M4
NC DQ6 DQ30 NC DQ6 DQ30
DQ7 DQ31
M2
DQ7 DQ31
M2 CMD13 RST* CMD29 RST*

1
R446 DIS@ 1 2 1K_0402_1% MF1 J1
MF
+1.35VSG J1
MF
+1.35VSG CMD14 CK1* CMD30 CK1*
R449 DIS@ 1 2 1K_0402_1% SEN1 J10 SEN1 J10
SEN SEN
R450 DIS@ 1 2 121_0402_1% ZQ2 J13
ZQ VDDQ
B1 1 R451 2 ZQ3 J13
ZQ VDDQ
B1 CMD15 CAS* CMD31 CAS*
D1 121_0402_1% D1
VDDQ VDDQ
VDDQ
F1 DIS@
VDDQ
F1 CMD32 NO USED
CMDA24 J4 M1 CMDA24 J4 M1
ABI# VDDQ ABI# VDDQ
CMDA28 G3
RAS# CAS# VDDQ
P1 CMDA31 G3
RAS# CAS# VDDQ
P1 CMD33 NO USED
CMDA16 G12 T1 CMDA21 G12 T1
CS# WE# VDDQ CS# WE# VDDQ
C CMDA31 L3
CAS# RAS# VDDQ
G2 CMDA28 L3
CAS# RAS# VDDQ
G2 CMD34 Debug0 C
CMDA21 L12 L2 CMDA16 L12 L2
WE# CS# VDDQ WE# CS# VDDQ
VDDQ
B3
VDDQ
B3 CMD35 Debug1
D3 D3
VDDQ F3 VDDQ F3
D5 VDDQ H3 FBA_WCK67# D5 VDDQ H3
(38) FBA_WCK45# WCK01# WCK23# VDDQ WCK01# WCK23# VDDQ
+1.35VSG (38) FBA_WCK45 D4 K3 FBA_WCK67 D4 K3
WCK01 WCK23 VDDQ M3 WCK01 WCK23 VDDQ M3
R508 1 2 DIS@ 10K_0402_5% P5 VDDQ P3 FBA_WCK45# P5 VDDQ P3
(38,41,42) CMDA14 (38) FBA_WCK67# WCK23# WCK01# VDDQ WCK23# WCK01# VDDQ
(38,42) CMDA30 R512 1 2 DIS@ 10K_0402_5% (38) FBA_WCK67 P4 T3 FBA_WCK45 P4 T3
R509 1 2 DIS@ 10K_0402_5% WCK23 WCK01 VDDQ E5 WCK23 WCK01 VDDQ E5
(38,43) CMDC14 VDDQ VDDQ
(38,44) CMDC30 R513 1 2 DIS@ 10K_0402_5% N5 N5
A10 VDDQ E10 A10 VDDQ E10
U10 VREFD VDDQ N10 DIS@ U10 VREFD VDDQ N10
FBA_VREFC J14 VREFD VDDQ B12 2 1 FBA_VREFC J14 VREFD VDDQ B12
(41) FBA_VREFC VREFC VDDQ VREFC VDDQ
(38,41,42) CMDA13 R510 1 2 DIS@ 10K_0402_5% D12 C765 820P_0402_25V8K D12
R514 1 2 DIS@ 10K_0402_5% VDDQ F12 VDDQ F12
(38,42) CMDA29 VDDQ VDDQ
(38,43) CMDC13 R515 1 2 DIS@ 10K_0402_5% H12 H12
R511 1 2 DIS@ 10K_0402_5% CMDA29 J2 VDDQ K12 CMDA29 J2 VDDQ K12
(38,44) CMDC29 RESET# VDDQ RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
VDDQ T12 VDDQ T12
VDDQ G13 VDDQ G13
VDDQ L13 VDDQ L13
CLKA1 VDDQ B14 VDDQ B14
(38) CLKA1 VDDQ VDDQ
D14 D14
VDDQ VDDQ
1

+1.35VSG F14 +1.35VSG F14

DIS@ VDDQ M14 VDDQ M14
R455 G1 VDDQ P14 G1 VDDQ P14
80.6_0402_1% L1 VDD VDDQ T14 L1 VDD VDDQ T14
G4 VDD VDDQ G4 VDD VDDQ
VDD VDD
2

CLKA1# L4 L4
(38) CLKA1# VDD VDD
B C5 A1 C5 A1 B
R5 VDD VSSQ C1 R5 VDD VSSQ C1
C10 VDD VSSQ E1 C10 VDD VSSQ E1
R10 VDD VSSQ N1 R10 VDD VSSQ N1
D11 VDD VSSQ R1 D11 VDD VSSQ R1
G11 VDD VSSQ U1 G11 VDD VSSQ U1
L11 VDD VSSQ H2 L11 VDD VSSQ H2 +1.35VSG
P11 VDD VSSQ K2 P11 VDD VSSQ K2
G14 VDD VSSQ A3 G14 VDD VSSQ A3
L14 VDD VSSQ C3 L14 VDD VSSQ C3

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
VDD VSSQ E3 VDD VSSQ E3

10U_0805_25V6K

10U_0805_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
VSSQ N3 VSSQ N3

DIS@ C726

DIS@ C727

DIS@ C707

DIS@ C706

DIS@ C724

DIS@ C720

DIS@ C715

DIS@ C728

DIS@ C718
VSSQ VSSQ 1 1 1 1 1 1 1

1
R3 R3
H1 VSSQ U3 H1 VSSQ U3
K1 VSS VSSQ C4 K1 VSS VSSQ C4
VSS VSSQ VSS VSSQ

2
B5 R4 B5 R4 2 2 2 2 2 2 2
G5 VSS VSSQ F5 G5 VSS VSSQ F5
L5 VSS VSSQ M5 L5 VSS VSSQ M5
T5 VSS VSSQ F10 T5 VSS VSSQ F10
B10 VSS VSSQ M10 B10 VSS VSSQ M10
D10 VSS VSSQ C11 D10 VSS VSSQ C11
G10 VSS VSSQ R11 G10 VSS VSSQ R11
L10 VSS VSSQ A12 L10 VSS VSSQ A12 +1.35VSG
P10 VSS VSSQ C12 P10 VSS VSSQ C12
T10 VSS VSSQ E12 T10 VSS VSSQ E12
H14 VSS VSSQ N12 H14 VSS VSSQ N12

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
K14 VSS VSSQ R12 K14 VSS VSSQ R12
VSS170-BALL VSSQ U12 VSS170-BALL VSSQ U12

DIS@ C716

DIS@ C725

DIS@ C719

DIS@ C722

DIS@ C717

DIS@ C723

DIS@ C721
VSSQ VSSQ 1 1 1 1 1 1 2
H13 H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14 2 2 2 2 2 2 1
A VSSQ E14 VSSQ E14 A
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
@ K4G41325FC-HC04_FBGA170~D
@ K4G41325FC-HC04_FBGA170~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/02 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 2/4
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 42 of 59
5 4 3 2 1
 5 4 3 2 1

MIRROR
Memory Partition B - Lower 16 bits U36
NORMAL U35

MF=0 MF=1 MF=1 MF=0

MF=0 MF=1 MF=1 MF=0 A4 MDC24

DQSC3 C2 DQ24 DQ0 A2 MDC25

VRAM DDR5 chips DQSC0 C2

C13 EDC0 EDC3
DQ24
DQ25
DQ0
DQ1
A4
A2
B4
MDC0
MDC1
MDC2
DQSC1
C13
R13
R2
EDC0
EDC1
EDC2
EDC3
EDC2
EDC1
DQ25
DQ26
DQ27
DQ1
DQ2
DQ3
B4
B2
E4
MDC26
MDC27
MDC28
Mode H
Address 0..31
Mode H
Address 32..63
EDC1 EDC2 DQ26 DQ2 EDC3 EDC0 DQ28 DQ4
DQSC2 R13 B2 MDC3 E2 MDC29 CMD0 CS* CMD16 CS*
128Mx16 GDDR5 *8==>2GB R2 EDC2
EDC3
EDC1
EDC0
DQ27
DQ28
DQ3
DQ4
E4 MDC4 DQ29
DQ30
DQ5
DQ6
F4 MDC30
DQ29 DQ5
E2 MDC5 DQMC3 D2
DBI0# DBI3# DQ31 DQ7
F2 MDC31 CMD1 A3_BA3 CMD17 A3_BA3
F4 MDC6 D13 A11
D 256Mx16 GDDR5 *8==>4GB DQMC0 D2
D13 DBI0# DBI3#
DQ30
DQ31
DQ6
DQ7
F2
A11
MDC7 DQMC1 P13
P2
DBI1#
DBI2#
DBI2#
DBI1#
DQ16
DQ17
DQ8
DQ9
A13
B11
CMD2 A2_BA0 CMD18 A2_BA0 D

DBI1# DBI2# DQ16 DQ8 DBI3# DBI0# DQ18 DQ10

DQMC2 P13
DBI2# DBI1# DQ17 DQ9
A13
DQ19 DQ11
B13 CMD3 A4_BA2 CMD19 A4_BA2
DQMC[7..0] P2 B11 CLKC0 J12 E11
(38,44) DQMC[7..0] DBI3# DBI0# DQ18 DQ10 CK DQ20 DQ12
DQ19 DQ11
B13 CLKC0# J11
CK# DQ21 DQ13
E13 CMD4 A5_BA1 CMD20 A5_BA1
CMDC[31..0] CLKC0 J12 E11 CMDC14 J3 F11
(38,42,44) CMDC[31..0] CK DQ20 DQ12 CKE# DQ22 DQ14
CLKC0# J11
CK# DQ21 DQ13
E13
DQ23 DQ15
F13 CMD5 WE* CMD21 WE*
DQSC[7..0] CMDC14 J3 F11 CMDC9 J5 U11 MDC8
(38,44) DQSC[7..0] CKE# DQ22 DQ14 A12/A13 DQ8 DQ16
DQ23 DQ15
F13
DQ9 DQ17
U13 MDC9 CMD6 A7_A8 CMD22 A7_A8
MDC[63..0] CMDC9 J5 U11 MDC16 CMDC10 K4 T11 MDC10
(38,44) MDC[63..0] A12/A13 DQ8 DQ16 A8/A7 A10/A0 DQ10 DQ18
DQ9 DQ17
U13 MDC17 CMDC11 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDC11 CMD7 A6_A11 CMD23 A6_A11
CMDC6 K4 T11 MDC18 CMDC1 K10 N11 MDC12
A8/A7 A10/A0 DQ10 DQ18 BA1/A5 BA3/A3 DQ12 DQ20
CMDC7 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDC19 CMDC2 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDC13 CMD8 ABI* CMD24 ABI*
CMDC4 K10 N11 MDC20 M11 MDC14
BA1/A5 BA3/A3 DQ12 DQ20 DQ14 DQ22
CMDC3 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDC21 CMDC4 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDC15 CMD9 A12_RFU CMD25 A12_RFU
M11 MDC22 CMDC3 H11 U4
DQ14 DQ22 +1.35VSG BA0/A2 BA2/A4 DQ0 DQ24
CMDC1 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDC23 CMDC7 H5
A9/A1 A11/A6 DQ1 DQ25
U2 CMD10 A0_A10 CMD26 A0_A10
CMDC2 H11 U4 CMDC6 H4 T4
BA0/A2 BA2/A4 DQ0 DQ24 A10/A0 A8/A7 DQ2 DQ26
CMDC11 H5
A9/A1 A11/A6 DQ1 DQ25
U2
DQ3 DQ27
T2 CMD11 A1_A9 CMD27 A1_A9

2
CMDC10 H4 T4 N4
A10/A0 A8/A7 DQ2 DQ26 DQ4 DQ28
DQ3 DQ27
T2 R458 A5
NC DQ5 DQ29
N2 CMD12 RAS* CMD28 RAS*
N4 1K_0402_1% DIS@ U5 M4
DQ4 DQ28 NC DQ6 DQ30
A5
NC DQ5 DQ29
N2
DQ7 DQ31
M2 CMD13 RST* CMD29 RST*
U5 M4
NC DQ6 DQ30

1
DQ7 DQ31
M2 J1
MF
+1.35VSG CMD14 CK1* CMD30 CK1*
SEN2 J10
SEN
R456 DIS@ 1 2 1K_0402_1% MF2 J1
MF
+1.35VSG ZQ5 J13
ZQ VDDQ
B1 CMD15 CAS* CMD31 CAS*
R457 DIS@ 1 2 1K_0402_1% SEN2 J10 D1
SEN VDDQ

2
R462 DIS@ 1 2 121_0402_1% ZQ4 J13
ZQ VDDQ
B1
VDDQ
F1 CMD32 NO USED
D1 R460 CMDC8 J4 M1
VDDQ ABI# VDDQ
VDDQ
F1 DIS@ 121_0402_1% CMDC15 G3
RAS# CAS# VDDQ
P1 CMD33 NO USED
CMDC8 J4 M1 CMDC5 G12 T1
ABI# VDDQ CS# WE# VDDQ
C CMDC12 G3
RAS# CAS# VDDQ
P1 CMDC12 L3
CAS# RAS# VDDQ
G2 CMD34 Debug0 C

1
CMDC0 G12 T1 CMDC0 L12 L2
CS# WE# VDDQ WE# CS# VDDQ
CMDC15 L3
CAS# RAS# VDDQ
G2
VDDQ
B3 CMD35 Debug1
CMDC5 L12 L2 D3
+1.35VSG WE# CS# VDDQ B3 VDDQ F3
VDDQ D3 FBB_WCK23# D5 VDDQ H3
VDDQ F3 FBB_WCK23 D4 WCK01# WCK23# VDDQ K3
VDDQ WCK01 WCK23 VDDQ
1

(38) FBB_WCK01# D5 H3 M3
R493 D4 WCK01# WCK23# VDDQ K3 FBB_WCK01# P5 VDDQ P3
(38) FBB_WCK01 WCK01 WCK23 VDDQ WCK23# WCK01# VDDQ
549_0402_1% M3 FBB_WCK01 P4 T3
DIS@ P5 VDDQ P3 WCK23 WCK01 VDDQ E5
(38) FBB_WCK23# WCK23# WCK01# VDDQ VDDQ
(38) FBB_WCK23 P4 T3 N5
WCK23 WCK01 VDDQ VDDQ
2

E5 A10 E10
VDDQ N5 U10 VREFD VDDQ N10
FBB_VREFC (44) VDDQ VREFD VDDQ
A10 E10 FBB_VREFC J14 B12
C762 VREFD VDDQ VREFC VDDQ
U10 N10 D12
VREFD VDDQ VDDQ
1

2 1 FBB_VREFC J14 B12 F12

R499 R495 820P_0402_25V8K VREFC VDDQ D12 VDDQ H12
1.33K_0402_1% DIS@ VDDQ F12 CMDC13 J2 VDDQ K12
931_0402_1% VDDQ RESET# VDDQ
DIS@ DIS@ H12 M12
CMDC13 J2 VDDQ K12 VDDQ P12
RESET# VDDQ VDDQ
2

M12 T12
Q37B VDDQ P12 VDDQ G13
VDDQ VDDQ
3

2N7002KDWH_SOT363-6 T12 L13

VDDQ G13 VDDQ B14
VDDQ L13 VDDQ D14
5 DIS@ VDDQ B14 +1.35VSG VDDQ F14
(36,41) VRAM_VREF_CTL VDDQ VDDQ
D14 M14
+1.35VSG VDDQ F14 G1 VDDQ P14 +1.35VSG
VDDQ VDD VDDQ
4

M14 L1 T14
G1 VDDQ P14 G4 VDD VDDQ
L1 VDD VDDQ T14 L4 VDD

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
B G4 VDD VDDQ C5 VDD A1 B

10U_0805_25V6K

10U_0805_25V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
L4 VDD R5 VDD VSSQ C1

DIS@ C742

DIS@ C743

DIS@ C730

DIS@ C729

DIS@ C740

DIS@ C736

DIS@ C731

DIS@ C744

DIS@ C734
VDD VDD VSSQ 1 1 1 1 1 1 1

1
C5 A1 C10 E1
R5 VDD VSSQ C1 R10 VDD VSSQ N1
C10 VDD VSSQ E1 D11 VDD VSSQ R1
VDD VSSQ VDD VSSQ

2
R10 N1 G11 U1 2 2 2 2 2 2 2
D11 VDD VSSQ R1 L11 VDD VSSQ H2
G11 VDD VSSQ U1 P11 VDD VSSQ K2
L11 VDD VSSQ H2 G14 VDD VSSQ A3
CLKC0 P11 VDD VSSQ K2 L14 VDD VSSQ C3
(38) CLKC0 VDD VSSQ VDD VSSQ
G14 A3 E3
VDD VSSQ VSSQ
1

L14 C3 N3
DIS@ VDD VSSQ E3 VSSQ R3 +1.35VSG
R465 VSSQ N3 H1 VSSQ U3
80.6_0402_1% VSSQ R3 K1 VSS VSSQ C4
H1 VSSQ U3 B5 VSS VSSQ R4

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
VSS VSSQ VSS VSSQ
2

CLKC0# K1 C4 G5 F5
(38) CLKC0# VSS VSSQ VSS VSSQ
B5 R4 L5 M5

DIS@ C732

DIS@ C741

DIS@ C735

DIS@ C738

DIS@ C733

DIS@ C739

DIS@ C737
VSS VSSQ VSS VSSQ 1 1 1 1 1 1 2
G5 F5 T5 F10
L5 VSS VSSQ M5 B10 VSS VSSQ M10
T5 VSS VSSQ F10 D10 VSS VSSQ C11
B10 VSS VSSQ M10 G10 VSS VSSQ R11 2 2 2 2 2 2 1
D10 VSS VSSQ C11 L10 VSS VSSQ A12
G10 VSS VSSQ R11 P10 VSS VSSQ C12
L10 VSS VSSQ A12 T10 VSS VSSQ E12
P10 VSS VSSQ C12 H14 VSS VSSQ N12
T10 VSS VSSQ E12 K14 VSS VSSQ R12
H14 VSS VSSQ N12 VSS170-BALL VSSQ U12
K14 VSS VSSQ R12 VSSQ H13
VSS170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13
VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
A VSSQ A14 VSSQ E14 A
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 @ K4G41325FC-HC04_FBGA170~D
VSSQ

@ K4G41325FC-HC04_FBGA170~D Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/02 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 3/4
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 43 of 59
5 4 3 2 1
 5 4 3 2 1

MIRROR
Memory Partition B - Upper 16 bits U38
NORMAL U37

MF=0 MF=1 MF=1 MF=0

MF=0 MF=1 MF=1 MF=0 A4 MDC56

DQSC7 C2 DQ24 DQ0 A2 MDC57
A4 C13 EDC0 EDC3 DQ25 DQ1 B4
MDC32 MDC58 Mode H Mode H
VRAM DDR5 chips DQSC4

DQSC6
C2
C13
R13
EDC0
EDC1
EDC3
EDC2
DQ24
DQ25
DQ26
DQ0
DQ1
DQ2
A2
B4
B2
MDC33
MDC34
MDC35
DQSC5 R13
R2
EDC1
EDC2
EDC3
EDC2
EDC1
EDC0
DQ26
DQ27
DQ28
DQ2
DQ3
DQ4
B2
E4
E2
MDC59
MDC60
MDC61
Address
CMD0
0..31
CS*
Address
CMD16
32..63
CS*
R2 EDC2 EDC1 DQ27 DQ3 E4 MDC36 DQ29 DQ5 F4 MDC62
128Mx16 GDDR5 *8==>2GB EDC3 EDC0 DQ28
DQ29
DQ4
DQ5
E2
F4
MDC37
MDC38
DQMC7 D2
D13 DBI0# DBI3#
DQ30
DQ31
DQ6
DQ7
F2
A11
MDC63 CMD1 A3_BA3 CMD17 A3_BA3
DQ30 DQ6 DBI1# DBI2# DQ16 DQ8
D DQMC4 D2 F2 MDC39 DQMC5 P13 A13 CMD2 A2_BA0 CMD18 A2_BA0 D
256Mx16 GDDR5 *8==>4GB D13 DBI0#
DBI1#
DBI3#
DBI2#
DQ31
DQ16
DQ7
DQ8
A11 P2 DBI2#
DBI3#
DBI1#
DBI0#
DQ17
DQ18
DQ9
DQ10
B11
DQMC6 P13
DBI2# DBI1# DQ17 DQ9
A13
DQ19 DQ11
B13 CMD3 A4_BA2 CMD19 A4_BA2
P2 B11 CLKC1 J12 E11
DBI3# DBI0# DQ18 DQ10 CK DQ20 DQ12
DQ19 DQ11
B13 CLKC1# J11
CK# DQ21 DQ13
E13 CMD4 A5_BA1 CMD20 A5_BA1
DQSC[7..0] CLKC1 J12 E11 CMDC30 J3 F11
(38,43) DQSC[7..0] CK DQ20 DQ12 CKE# DQ22 DQ14
CLKC1# J11
CK# DQ21 DQ13
E13
DQ23 DQ15
F13 CMD5 WE* CMD21 WE*
DQMC[7..0] CMDC30 J3 F11 CMDC25 J5 U11 MDC40
(38,43) DQMC[7..0] CKE# DQ22 DQ14 A12/A13 DQ8 DQ16
DQ23 DQ15
F13
DQ9 DQ17
U13 MDC41 CMD6 A7_A8 CMD22 A7_A8
MDC[63..0] CMDC25 J5 U11 MDC48 CMDC26 K4 T11 MDC42
(38,43) MDC[63..0] A12/A13 DQ8 DQ16 A8/A7 A10/A0 DQ10 DQ18
DQ9 DQ17
U13 MDC49 CMDC27 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDC43 CMD7 A6_A11 CMD23 A6_A11
CMDC[31..0] CMDC22 K4 T11 MDC50 CMDC17 K10 N11 MDC44
(38,42,43) CMDC[31..0] A8/A7 A10/A0 DQ10 DQ18 BA1/A5 BA3/A3 DQ12 DQ20
CMDC23 K5
A11/A6 A9/A1 DQ11 DQ19
T13 MDC51 CMDC18 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDC45 CMD8 ABI* CMD24 ABI*
CMDC20 K10 N11 MDC52 M11 MDC46
BA1/A5 BA3/A3 DQ12 DQ20 DQ14 DQ22
CMDC19 K11
BA2/A4 BA0/A2 DQ13 DQ21
N13 MDC53 CMDC20 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDC47 CMD9 A12_RFU CMD25 A12_RFU
M11 MDC54 CMDC19 H11 U4
DQ14 DQ22 +1.35VSG BA0/A2 BA2/A4 DQ0 DQ24
CMDC17 H10
BA3/A3 BA1/A5 DQ15 DQ23
M13 MDC55 CMDC23 H5
A9/A1 A11/A6 DQ1 DQ25
U2 CMD10 A0_A10 CMD26 A0_A10
CMDC18 H11 U4 CMDC22 H4 T4
BA0/A2 BA2/A4 DQ0 DQ24 A10/A0 A8/A7 DQ2 DQ26
CMDC27 H5
A9/A1 A11/A6 DQ1 DQ25
U2
DQ3 DQ27
T2 CMD11 A1_A9 CMD27 A1_A9

2
CMDC26 H4 T4 N4
A10/A0 A8/A7 DQ2 DQ26 DQ4 DQ28
DQ3 DQ27
T2 R468 A5
NC DQ5 DQ29
N2 CMD12 RAS* CMD28 RAS*
N4 1K_0402_1% DIS@ U5 M4
DQ4 DQ28 NC DQ6 DQ30
A5
NC DQ5 DQ29
N2
DQ7 DQ31
M2 CMD13 RST* CMD29 RST*
U5 M4
NC DQ6 DQ30

1
DQ7 DQ31
M2 J1
MF
+1.35VSG CMD14 CK1* CMD30 CK1*
SEN3 J10
SEN
R466 DIS@ 1 2 1K_0402_1% MF3 J1
MF
+1.35VSG 1 R470 2 ZQ7 J13
ZQ VDDQ
B1 CMD15 CAS* CMD31 CAS*
R467 DIS@ 1 2 1K_0402_1% SEN3 J10 DIS@ D1
SEN VDDQ
R472 DIS@ 1 2 121_0402_1% ZQ6 J13
ZQ VDDQ
B1 121_0402_1%
VDDQ
F1 CMD32 NO USED
D1 CMDC24 J4 M1
VDDQ ABI# VDDQ
VDDQ
F1 CMDC31 G3
RAS# CAS# VDDQ
P1 CMD33 NO USED
CMDC24 J4 M1 CMDC21 G12 T1
ABI# VDDQ CS# WE# VDDQ
C CMDC28 G3
RAS# CAS# VDDQ
P1 CMDC28 L3
CAS# RAS# VDDQ
G2 CMD34 Debug0 C
CMDC16 G12 T1 CMDC16 L12 L2
CS# WE# VDDQ WE# CS# VDDQ
CMDC31 L3
CAS# RAS# VDDQ
G2
VDDQ
B3 CMD35 Debug1
CMDC21 L12 L2 D3
WE# CS# VDDQ B3 VDDQ F3
VDDQ D3 FBB_WCK67# D5 VDDQ H3
VDDQ F3 FBB_WCK67 D4 WCK01# WCK23# VDDQ K3
D5 VDDQ H3 WCK01 WCK23 VDDQ M3
(38) FBB_WCK45# WCK01# WCK23# VDDQ VDDQ
(38) FBB_WCK45 D4 K3 FBB_WCK45# P5 P3
WCK01 WCK23 VDDQ M3 FBB_WCK45 P4 WCK23# WCK01# VDDQ T3
P5 VDDQ P3 WCK23 WCK01 VDDQ E5
(38) FBB_WCK67# WCK23# WCK01# VDDQ VDDQ
(38) FBB_WCK67 P4 T3 N5
WCK23 WCK01 VDDQ E5 A10 VDDQ E10
VDDQ C763 VREFD VDDQ
N5 U10 N10
A10 VDDQ E10 2 1 FBB_VREFC J14 VREFD VDDQ B12
U10 VREFD VDDQ N10 820P_0402_25V8K VREFC VDDQ D12
FBB_VREFC J14 VREFD VDDQ B12 DIS@ VDDQ F12
(43) FBB_VREFC VREFC VDDQ VDDQ
D12 H12
VDDQ F12 CMDC29 J2 VDDQ K12
VDDQ H12 RESET# VDDQ M12
CMDC29 J2 VDDQ K12 VDDQ P12
RESET# VDDQ M12 VDDQ T12
VDDQ P12 VDDQ G13
VDDQ T12 VDDQ L13
CLKC1 VDDQ G13 VDDQ B14
(38) CLKC1 VDDQ VDDQ
L13 D14
VDDQ VDDQ
1

B14 +1.35VSG F14

DIS@ VDDQ D14 VDDQ M14
R475 +1.35VSG VDDQ F14 G1 VDDQ P14
80.6_0402_1% VDDQ M14 L1 VDD VDDQ T14
G1 VDDQ P14 G4 VDD VDDQ
VDD VDDQ VDD
2

CLKC1# L1 T14 L4
(38) CLKC1# VDD VDDQ VDD
B G4 C5 A1 B
L4 VDD R5 VDD VSSQ C1
C5 VDD A1 C10 VDD VSSQ E1
R5 VDD VSSQ C1 R10 VDD VSSQ N1
C10 VDD VSSQ E1 D11 VDD VSSQ R1 +1.35VSG
R10 VDD VSSQ N1 G11 VDD VSSQ U1
D11 VDD VSSQ R1 L11 VDD VSSQ H2
G11 VDD VSSQ U1 P11 VDD VSSQ K2
L11 VDD VSSQ H2 G14 VDD VSSQ A3

10U_0805_25V6K

10U_0805_25V6K

C756

C752

C747

C760

C750
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
P11 VDD VSSQ K2 L14 VDD VSSQ C3

1U_0402_6.3V6K

1U_0402_6.3V6K
VDD VSSQ VDD VSSQ 1 1 1 1 1 1 1

1
G14 A3 E3

C758

C759

DIS@ C746

DIS@ C745
L14 VDD VSSQ C3 VSSQ N3
VDD VSSQ E3 VSSQ R3

DIS@

DIS@

DIS@

DIS@

DIS@
VSSQ VSSQ

2
N3 H1 U3 2 2 2 2 2 2 2

DIS@

DIS@
VSSQ R3 K1 VSS VSSQ C4
H1 VSSQ U3 B5 VSS VSSQ R4
K1 VSS VSSQ C4 G5 VSS VSSQ F5
B5 VSS VSSQ R4 L5 VSS VSSQ M5
G5 VSS VSSQ F5 T5 VSS VSSQ F10
L5 VSS VSSQ M5 B10 VSS VSSQ M10
T5 VSS VSSQ F10 D10 VSS VSSQ C11 +1.35VSG
B10 VSS VSSQ M10 G10 VSS VSSQ R11
D10 VSS VSSQ C11 L10 VSS VSSQ A12
G10 VSS VSSQ R11 P10 VSS VSSQ C12
L10 VSS VSSQ A12 T10 VSS VSSQ E12

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
P10 VSS VSSQ C12 H14 VSS VSSQ N12

DIS@ C751

DIS@ C754

DIS@ C749

DIS@ C755

DIS@ C753
1U_0402_6.3V6K

1U_0402_6.3V6K
VSS VSSQ VSS VSSQ 1 1 1 1 1 1 2
T10 E12 K14 R12

DIS@ C748

DIS@ C757
H14 VSS VSSQ N12 VSS170-BALL VSSQ U12
K14 VSS VSSQ R12 VSSQ H13
VSS170-BALL VSSQ U12 SGRAM GDDR5 VSSQ K13 2 2 2 2 2 2 1
VSSQ H13 VSSQ A14
SGRAM GDDR5 VSSQ K13 VSSQ C14
A VSSQ A14 VSSQ E14 A
VSSQ C14 VSSQ N14
VSSQ E14 VSSQ R14
VSSQ N14 VSSQ U14
VSSQ R14 VSSQ
VSSQ U14 @ K4G41325FC-HC04_FBGA170~D
VSSQ
@ K4G41325FC-HC04_FBGA170~D
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2013/04/02 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX GDDR5 4/4
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-B111P
Date: Wednesday, October 30, 2013 Sheet 44 of 59
5 4 3 2 1
 5 4 3 2 1

+3VS to +3V3_AON Vgs=-4.5V,Id=3A,Rds<97mohm +3VS to +3VS_DGPU

Vgs=-4.5V,Id=3A,Rds<97mohm
+3V3_AON +VGA_CORE
+3VS +3V3_AON +3VS_DGPU +3VS +3VS_DGPU
DIS@ Q36
+3VS
2

2
+3VS

2
R476 R477 3 1 3 1

D
220_0402_5% 470_0805_5% SW@ AO3413_SOT23
DIS@ DIS@ Q25 AO3413_SOT23 SW@ R504

2
1 1 220_0402_5% 1 1

G
6 1

3 1

2
2
D C778 C779 DIS@ R507 C783 D

6 1
R478 DIS@ 20K_0402_5% SW@ SW@ SW@ C784
20K_0402_5% 0.1U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K
Q31A Q31B DIS@ 2 2 2 2

1
2 DGPU_PWR_EN# 5 2N7002KDWH_SOT363-6 Q35A R505

1
DIS@ DIS@ R479 SW@ 2 3V3_MAIN_EN# 3V3_MAIN_EN# 1 2
2N7002KDWH_SOT363-6 DGPU_PWR_EN# 1 2 2N7002KDWH_SOT363-6 SW@ 10K_0402_5%
1

3
10K_0402_5%

3
DIS@ Q35B
Q33B SW@
3V3_MAIN_EN 5
(14,31) DGPU_PWR_EN DGPU_PWR_EN 5
2N7002KDWH_SOT363-6 2N7002KDWH_SOT363-6

4
DIS@

4
+1.35V to +1.35VSG
+1.35V +1.35VSG +3V3_AON +1.05VS to +1.05VSG
+3V3_AON
+3V3_AON

2
R524
C Q27 DIS@ 10K_0402_5% +1.05VS +1.05VSG +3V3_AON C
2

2
8 1 @
7 D S 2 R529 @ R480 R526 R522 R521
D S

1
6 3 1 2 B+ 470_0805_5% 10K_0402_5% 10K_0402_5% +1.35VSG_PGOOD 10K_0402_5%
D S

2
5 4 180K_0402_5% DIS@ DIS@ DIS@ Q26 DIS@ DIS@
D G D

1
R483 DIS@ 8 1 R530 @ R482 R525 R523
2N7002K_SOT23-3 D S
1

1
AO4354_SO8 VRAM_1.35VS_GATE 1 2 +12VS 2 7 2 1 2 B+ 470_0805_5% 10K_0402_5% 10K_0402_5% +1.05VS_DGPU_PGOOD
180K_0402_5% G Q39 6 D S 3 180K_0402_5% DIS@
1 1 D S DIS@ DIS@ D
1

1
C DIS@ 5 4 R491 DIS@
0.01U_0402_25V7K
4.7U_0603_6.3V6K

S
D G 2N7002K_SOT23-3

1
C780 C781 R484 Q29A 2 Q41 1 VRAM_1.05VS_GATE 1 2 +12VS 2
DIS@ DIS@ DIS@ 820K_0402_5% Q29B B MMST3904-7-F_SOT323-3 AO4354_SO8 180K_0402_5% G Q38
2 2 1

1
2 1.35V_PWR_EN# 5 2N7002KDWH_SOT363-6 DIS@E C DIS@

0.01U_0402_25V7K
S

3
2N7002KDWH_SOT363-6 DIS@ DIS@ C789 1 1 C600 R490 Q28A 2 Q42 1
2 0.1U_0402_16V7K
2

DIS@ DIS@ DIS@ 820K_0402_5% Q28B B MMST3904-7-F_SOT323-3

0.01U_0402_25V7K
4.7U_0603_6.3V6K
2
1

+5VALW C791 C605 2 3V3_MAIN_EN# 5 2N7002KDWH_SOT363-6 DIS@ E

3
DIS@ DIS@ 2N7002KDWH_SOT363-6 DIS@ DIS@ C788
2 2 2 0.1U_0402_16V7K

2
1 2 DIS@

4
100K_0402_5% R485 +5VALW
DIS@
3

1 2
DIS@ 100K_0402_5% R486
Q30B DIS@

6
(36) 1.35V_PWR_EN 1.35V_PWR_EN 5
2N7002KDWH_SOT363-6 DIS@
Q30A
4

(36,54) 3V3_MAIN_EN 3V3_MAIN_EN 2

2N7002KDWH_SOT363-6

1
+3V3_AON +3V3_AON
B B
H_THRMTRIP# (18,5)
1
2

DIS@

2
R527 @
3

10K_0402_5% C786 DIS@ R528

2 0.1U_0402_16V7K D33
DIS@ 10K_0402_5%
Q44B 1 2 DIS@
(18,36,54) DGPU_PWROK
1

GPU_OVERT 5 RB751V-40_SOD323-2

1
2N7002KDWH_SOT363-6
D32
6

DIS@
4

DIS@ +1.05VS_DGPU_PGOOD 1 2
2N7002KDWH_SOT363-6 RB751V-40_SOD323-2
(36,37) GPU_OVERT# 2 1
Q44A +1.35VSG_PGOOD R519 1 20_0402_5% GPU_ALL_PGOOD
GPU_ALL_PGOOD (14)
@ DIS@
1

C785
2 0.1U_0402_16V7K

D
1

DIS@ DIS@
(14,36) DGPU_HOLD_RST# R5201 20_0402_5%
2 @ @
G Q40 3V3_MAIN_EN 2 R532 1 +1.05VS_DGPU_PGOOD 1.35V_PWR_EN2 R533 1 +1.35VSG_PGOOD
V0.2 1 S 2N7002K_SOT23-3 1K_0402_5% 10K_0402_5%
3

1 1
@ C793 C792
C787 @ 0.1U_0402_16V7K @ 0.1U_0402_16V7K
2 0.1U_0402_16V7K
2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/04/02 Deciphered Date 2012/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX DC-DC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-B111P
Date: Wednesday, October 30, 2013 Sheet 45 of 59
5 4 3 2 1
 5 4 3 2 1

JDCIN1 PF101 EMI@ PL101

VIN
1 APDIN 7A_24VDC_429007.WRML FBMA-L11-453215800LMA90T_2P
1 2 1 2 APDIN1 1 2
2 3 SM01000JF00
3 4
4 5

1000P_0402_50V7K

1000P_0402_50V7K
PC101 EMI@

PC102 EMI@

PC103 EMI@

PC104 EMI@
100P_0402_50V8J

100P_0402_50V8J
5
ACES_50299-00501-003_5P

1
CONN@
SP02000YD00

2
D
135W adaptor D

PR101
0_0402_5%
1 2
PQ101A
2N7002KDW-2N_SOT363-6
1 2 6 1

680P_0603_50V7K
+3VALW PR102 ADP_ID (31)

0.1U_0402_16V7K
750_0402_1%
A/D

1
PC105

PC106
2
PR103

2
100K_0402_5%

2N7002KDW-2N_SOT363-6
1 2
VIN

3
1
PR104

PQ101B
5
100K_0402_5% ADP_ID_CLOSE (31)

4
+CHGRTC
C PR105 C
1K_0603_5%
1 2
PD101 +3VLP
S SCH DIO BAS40CW SOT-323
2 +CHGRTC_R
+RTCVCC 1
3 PR106
1K_0603_5% JRTC1 CONN@
1 2 1
2 1
3 2
4 GND
GND
ACES_50271-0020N-001

GC02001DR00
RTC Battery BATT CR2032 3V 210MAH MB 5 W/C
30MM

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR DCIN / RTC Battery
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom BE_BDW 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 46 of 59
5 4 3 2 1
 5 4 3 2 1

EMI@ PL202
V0.2 SM01000AZ00_2P
VMB2 PF201 VMB 1 2
CONN@ PL201
JBATT1 12A_65V_451012MRL SM01000AZ00_2P
1 1 2 1 2
1 BATT+
2 EMI@
2 3 EC_SMCA
3 4 EC_SMDA EMI@
4 5 PC207 PC202

0.01U_0402_25V7K
5 6 EMI@ PC208 EMI@
6

1000P_0402_50V7K
7 EMI@
7

1
8

100_0402_1%

100_0402_1%
D 0.01U_0402_25V7K D
GND 9 PC201
GND 1000P_0402_50V7K

2
SUYIN_125017GA007G101ZL

PR201

PR211
2

2
LTCX005DC00

2S2P / 54W

EC_SMB_CK1 (31,48)

EC_SMB_DA1 (31,48)
1 2 +3VLP
PR212
6.49K_0402_1%
A/D
1 2
VCIN1_BATT_TEMP (31,47)
PR214
10K_0402_5%

+EC_VCCA
(31,48) ADP_I

12.7K_0402_1%
1
C (31) VCOUT1_PROCHOT# C

10K_0402_1%

PR215
1

2
8.45K_0402_1%
+5VL +3VALW

PR216

PR217

2
@ (31) VCIN0_PH1

1
2
+5VL PR218
(31) VCIN1_ADP_PROCHOT
2

1
PC204 PR219 100K_0402_1% PH201
1

2
100K_0402_1%_TSM0B104F4251RZ

6 1
1

0.01U_0402_25V7K 100K_0402_1%
BATT_OUT (48)
PR222 PR220 PR221
2

2
2

75K_0402_1% 47K_0402_1% 100K_0402_1%

PQ201A

1
2 2N7002KDW-2N_SOT363-6
2

ECAGND (31)
3

PC205
1

1
8

0.068U_0402_16V7K
(31,47) VCIN1_BATT_TEMP 3 PQ201B
P

+ 1 1 2 5 2N7002KDW-2N_SOT363-6
2 O
1N4148WS-7-F_SOD323-2

-
G

PU202A
PD201

4
1

AS393MTR-E1 SO 8P OP
4
2

PR227 PR226
1

100K_0402_1%
1

PC206 1.5M_0402_5%
ENE9022 Battery Voltage drop detection.
2

100P_0402_50V8J
1

+3VLP
Connect to ENE9022 pin64 AD1.
2

B B
PR228 B+
100K_0402_1%
D
1

2 PQ205
(31) BATT_LEN#

1
G 2N7002KW_SOT323-3
S PR12
3

51K_0402_1%

2
VCIN1_BATT_DROP (31)

1
2
@PC8
@ PC8 PR13

0.1U_0402_25V6 10K_0402_1%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom BE_BDW 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 47 of 59
5 4 3 2 1

AO4407AL Vds=-30V
Rds_on=12.7~17mohm@Vgs=-6V
ID = 10A (Ta=70C)
VIN
5 4 3 2 1
AO4423L Vds=-30V
Rds_on=9.4~12mohm@Vgs=-6V P3 Power Rating = 1W
B+ Need EC write ChargeOption() bit[8]=0
P2 ID = 12.1A (Ta=70C) VACP~VACN spec < 80.64mV to disable iFault_Hi function.
PQ301 SB00000DL10 PQ302 SB000012B00
AO4407AL 1P SO8 AO4455 1P SO8 SD00000K820
8 1 1 8 PR302
7 2 2 7 0.01_1206_1% EMI@ PL301 CHG_B+
6 3 3 6 1UH +-20% PH041H-1R0MS 3.8A
5 5 1 4 1 2 PQ303 SB000012B00
AO4455 1P SO8
2 3 SH00000MN00 1 8

4
3.8x3.8xH1.8 2 7

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
3 6
DCR: 20~25mohm

1
PQ304 5

PC304

PC305

@EMI@ PC306

@EMI@ PC307
D D
1 2 Idc / Isat: 3.8A
47K_0402_5%

@EMI@ PC303
1

1
10U_0805_25V6K

200K_0402_1%
0.1U_0603_25V7K

4
1
DTA144EUA_SC70-3 PC302 DISCHG_G
PR301

1
5600P_0402_25V7K

PC301

PR303

2
PR304
200K_0402_1%
ACDET
2

2
2 1 2
VIN

2
ACN

2ACOFF-1
1
1

ACP PR305

1DISCHG_G-1
47K_0402_1%

1SS355_UMD2-2
1

1
V1
P2-1 PR306

PD302
2
2 200K_0402_1%
PQ305 PC308 PC309 PQ306

1
0.1U_0402_25V6 0.1U_0402_25V6 DTC115EUA_SC70-3

2
DTC115EUA_SC70-3 PR307 1 2 1 2
20K_0402_1% PD303
3

1SS355_UMD2-2
2 2 1 2
6

2N7002KW_SOT323-3
1

charge current: 7.4A

150K_0402_1%

PQ309
1

PQ307A D PQ308 2N7002KW_SOT323-3

PR308

0.1U_0603_25V7K
discharge current: 9A

1
2 2N7002KDW-2N_SOT363-6 2 ACPRN# P2 D
BATT_OUT (47,48)

3
Hybrid: BATT limit 6.5A

1
G PC310 2PACIN_2

PC311
1 2 G
1

S VIN
3

2
S
0.1U_0402_25V6

3
392K_0402_1%
1
P2-2

PACIN_2 SB00000H800

5
C C

10_1206_5%
PR309
2N7002KDW-2N_SOT363-6

AON7408L 1N DFN
5

PR310
3

10x10xH4
PQ307B

ACOK

CMPOUT
CMPIN

ACP

ACN
PR311 PR312 (31,47) ADP_I PR313
DCR: 17~20mohm
2

21

PQ310
47K_0402_1% 59K_0402_1% 0_0402_5%
TP

2
PACIN 1 2 5 1 2 6
ACDET PC314
1 2 4 Idc: 8.5A
PC313 20 BQ24737VCC 1 2
Isat: 15A
VCC
4

PC312 1 2 7 SD00000K820
1 2 IOUT SH00000Q900 PR314
1U_0603_25V6K

3
2
1
1

PQ311 2200P_0402_25V7K 100P_0603_50V8 19 PL302 0.01_1206_1%

DTC115EUA_SC70-3
(31,47) EC_SMB_DA1
8
SDA
PU301 PHASE 4.7UH +-20% PCMB104T-4R7MS 8.5A BATT+
BQ24737RGRR_VQFN20_3P5X3P5 LX_CHG 1 2CHG 1 4
18 DH_CHG SB000010U00
HIDRV

5
1 PR315 2 ACOFF-1 2 9 2 3
SA00004RZ00

@EMI@ PR319
AON7752 1N DFN
(31) ACOFF (31,47) EC_SMB_CK1 SCL

1
PR317 PR318

4.7_1206_5%
10K_0402_1% 201K_0402_1% 2.2_0603_5% PC315
1

1 2 10 17 BST_CHG 1 2 1 2 SRP SRN

10U_0805_25V6K

10U_0805_25V6K
ILIM BTST
1

PR316 @ 196K_0402_1%

16251_SN
+3VLP PD301
3

PQ312
0.047U_0603_16V7K
PR320
0.01U_0402_25V7K

0_0402_5%

LODRV
PC316

2
1

1
16 2 1

PC317

PC318
GND
SRN
REGN

SRP
BM
2

VILIM=3.366V*(196/(196+200))

680P_0603_50V7K
RB751V-40_SOD323-2
2

2
2N7002KW_SOT323-3

@EMI@ PC320
=20*Ichg*10m　 11

1 12

13

14

15

3
2
1
1

1
10_0603_5%
6.8_0603_5%
Ichg=Idchg=8.33A

2
1

PQ313 D PC319

PR321
2
PR322
,48) BATT_OUT 1U_0603_16V7 BQ24737VDD

2
G

S 2
3

2
1

DL_CHG
PC321
B @PR323
@ PR323 B
10K_0402_5% 1 2

0.1U_0402_25V6
2

1
PC323
0.1U_0402_25V6 @PC322
@ PC322
2

+3VALW 2 0.1U_0402_25V6

BQ24737VDD

PR326
10K_0402_1%

1
1 2 ACIN (14,31)
PR325
MOSFET: 3x3 DFN PR324 10K_0402_1%
47K_0402_1%
H/S Rds(on): 22mohm(Typ), 34mohm(Max) PACIN

1 2
Idsm: 7.5A@Ta=25C, 5.5A@Ta=70C

1
L/S Rds(on): 8.2mohm(Typ), 14.5mohm(Max)
PR327
Idsm: 12A@Ta=25C, 15A@Ta=70C ACPRN# 2
12K_0402_1%

2
PQ314

DTC115EUA_SC70-3

3
A A
For disable pre-charge circuit

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Charger_BQ24737
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, October 30, 2013 Sheet 48 of 59

5 4 3 2 1
 A B C D E

1 1

PR401
499K_0402_1%
ENLDO_3V5V 1 2
B+

1
150K_0402_1%
PU401 PC403 PR403
B+ EMI@ PL401 7 1 3V5V_EN 0.01U_0402_25V7K 1K_0402_5%

PR404
HCB2012KF-121T50_0805 IN EN1 1 2 1 2
1 2 8 3

2200P_0402_50V7K
3V_VIN 3V_FB
IN EN2 PR405 PC404

2
6 1
BST_3V 2 1 2

10U_0805_25V6K

10U_0805_25V6K
@EMI@ PC405
0.1U_0402_25V6 BS
1

1
0_0603_5%

PC407
C407
0.1U_0603_25V7K
@EMI@ PC401

PC406
@
@P PL402
2

2
10 LX_3V 1 2
LX +3VALWP
9 4 1.5UH_PCMB053T-1R5MS_6A_20%
TDC=6A

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
GND OUT SH00000SC00

PR406
1

1
2 5
Iocp : 8A

PC408

PC409

PC410

PC411
680P_0603_50V7K 4.7_1206_5%
SPOK PG LDO +3VLP
5x5xH3

1
FSW : 750KHz

100K_0402_1%
SY8208BQNC_QFN10_3X3
DCR: 20~25mohm

2
@EMI@
SA000061M00 PC412

PR415
Idc: 6A

13V_SN
4.7U_0603_6.3V6M

2
Isat: 10A

2
+3VLP 3.3V LDO 150mA~300mA

@EMI@ PC413
2
2 PR407 2
2.2K_0402_5%
1 2
(31) EC_ON
@ PR408
1 2
(31) VCOUT0_MAIN_PWR_ON 0_0402_5%
@ PJ401
+3VALWP 1 2 +3VALW
MAINPWON 1 2
JUMP_43X118
3V5V_EN
1M_0402_1%

4.7U_0402_6.3V6M
1

1
PR410

PC414
2
2

B+ EMI@ PL403
HCB2012KF-121T50_0805
1 2 5V_VIN
2200P_0402_50V7K

PU402 PC415 PR412

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6

8 1 3V5V_EN 6800P_0402_25V7K 1K_0402_5%

IN EN1 1 2 1 2
1

3 5V_FB PR413 PC417

PC416

PC418

@EMI@ PC419

@EMI@ PC420

3 EN2 0_0603_5% 0.1U_0603_25V7K 3

6 BST_5V 1 2 1 2
BS
2

PL404
9 10 LX_5V 1 2 +5VALWP
GND LX
5V_VCC 5 4 1.5UH_PCMB053T-1R5MS_6A_20%
TDC=6A

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
VCC OUT
1

SH00000SC00
680P_0603_50V7K 4.7_1206_5%
@EMI@ PR414

1
2 7
Iocp : 9A

PC422

PC423

PC424

PC425
PG LDO +5VL
1

5x5xH3
PC421
4.7U_0603_6.3V6M

SY8208CQNC_QFN10_3X3
DCR: 20~25mohm FSW : 750KHz

2
15V_SN

SA000061N00 @PJ402
@ PJ402
2

Idc: 6A
1

+5VALWP 1 2 +5VALW
PC426
4.7U_0603_6.3V6M

1 2
Isat: 10A JUMP_43X118
2

@EMI@ PC427
2

5V LDO 150mA~300mA

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+3VALW/+5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom BE_BDW 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 49 of 59
A B C D E
 5 4 3 2 1

D D

EMI@ PL503
HCB2012KF-121T50_0805
1 2

EMI@ PL501
HCB2012KF-121T50_0805
B+ 1 2 1.35V_B+ PR501
0_0603_5%
BST_1.35V 1 2 BOOT_1.35V

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
+1.35VP
@EMI@ PC501

@EMI@ PC502
1

1
PC503

PC504

PC511
DH_1.35V +0.675VSP
2

1
SW_1.35V

10U_0805_6.3V6K

10U_0805_6.3V6K
PC505

1
0.1U_0603_25V7K

PC506

PC507
2
5

16

17

18

19

20
C PQ501 PU501 C

2
10x10xH4

AON6552 1N DFN

PHASE

UGATE

BOOT

VTT
VLDOIN
21

SB000010B00
DCR: 3~3.3mohm PAD
Idc: 18A 4 DL_1.35V 15
LGATE VTTGND
1
Isat: 28A
14 2
PL502 PR502 PGND VTTSNS

1
2
3
1UH_PCMB104T-1R0MH_18A_20% 11K_0402_1%
1 2 1 2 CS_1.35V 13 3
+1.35VP SH00000N800 PC508 CS RT8207MZQW_WQFN20_3X3 GND
1

SB000010G00 PQ502 1U_0603_10V6K

SF000003X00 PC510

AON6554 1N DFN5X6-8

5
TDC=17A (+VRAM) ESR 12mohm 1 2 12 4 +VTTREFP
390U 2.5V M C6 R10M SVPE H5.9

@EMI@ PR503 PR504 VDDP VTTREF

Iocp : 25A 1 4.7_1206_5% 5.1_0603_5%

1 2 VDD_1.35V 11 5
+5VALW VDD VDDQ
+1.35VP
1 2

1
+
FSW : 300KHz

PGOOD
4 1 2 PC509
+5VALW

TON
1
@EMI@ PC513 PR513 0.033U_0402_16V7K

FB
S5

S3
2

2
680P_0402_50V7K PC512 5.1_0603_5%
2

1U_0603_10V6K

10

6
+3VALW
1
2
3

1 2

FB_1.35V
EN_0.675VSP
TON_1.35V

EN_1.35V
PR505 100K_0402_5% PR506
8.2K_0402_1%
PR507 1 2 +1.35VP
887K_0402_1%
B 1.35V_B+ 1 2 B

1
MOSFET: 5x6 DFN Vout=0.75V* (1+Rup/Rdown)
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max) PR508
Idsm: 23A@Ta=25C, 18A@Ta=70C @ PR509 10K_0402_1%
1 2
(31,35) SYSON

2
Mode Level +0.675VSP VTTREF_1.35V 0_0402_5%
S5 L off off L/S Rds(on): 2.8mohm(Typ), 3.8mohm(Max)

1
@ PC514
S3 L off on Idsm: 33.5A@Ta=25C, 42A@Ta=70C 0.1U_0402_10V7K
S0 H on on

2
Note: S3 - sleep ; S5 - power off
@ PR510
1 2 @ PJ501
(31,34,35,51,52,53) SUSP# +1.35VP 1 2 +1.35V
0_0402_5% 1 2

1
JUMP_43X118
@ PC515 @ PJ502
0.1U_0402_10V7K 1 2
1 2

2
JUMP_43X118

PJ503 @
1 2
+0.675VSP 1 2 +0.675VS
JUMP_43X39
A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2011/06/24 Deciphered Date 2012/07/12
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, October 30, 2013 Sheet 50 of 59
5 4 3 2 1
 A B C D

1 1

+3VALW

1
PC603
1U_0402_6.3V6K

2
PU601 SA000034S00
APL5930KAI-TRG_SO8
6
2
5 VCNTL 3 2

9 VIN VOUT 4 +1.5VSP

VIN VOUT

22U_0603_6.3V6M
0.022U_0402_16V7K
1

1
PC602 8
EN

1
4.7U_0603_6.3V6K 7 2

PC605
PC604
GND
POK FB PR605

2
20K_0402_1%

2
FB=0.8V

2
PR601
0_0402_5%
(31,34,35,50,52,53) SUSP# 1 2 +1.5VSP_EN FB_1.5VSP_UMA

1
1
PR603
PC601 1M_0402_5% PR606
0.1U_0402_16V7K 22.6K_0402_1% @
PJ602

2
1 2
+1.5VSP 1 2 +1.5VS
JUMP_43X79

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.5VS
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, October 30, 2013 Sheet 51 of 59
A B C D
 5 4 3 2 1

D D

PR702
0_0402_5%
1 2
SUSP# (31,34,35,50,51,53)
C C

1
@ PC702
1M_0402_1%
0.22U_0402_10V6K

2
PR703 PJ701

2
+1.05VSP 1 2 +1.05VS
1 2
JUMP_43X118 @
@EMI@ PR704 @EMI@ PC703
4.7_1206_5% 680P_0603_50V7K
EMI@ PL701 1 2SNB_1.05VSP
1 2
HCB2012KF-121T50_0805 PU701
1 2 B+_1.05VS 8 1 PR705 PC704
B+ IN EN 0_0603_5% 0.1U_0603_25V7K
10U_0805_25V6K

10U_0805_25V6K

6 1
BST_1.05VS 2 1 2 PL702
@EMI@ PC701

@EMI@ PC705
2200P_0402_50V7K

0.1U_0402_25V6

BS
1

1UH_PCMB063T-1R0MS_12A_20%
PC706

PC707

3VLDO_1.05VS 9
GND LX
10 LX_1.05VS 1
SH00000PJ00
2
+1.05VSP
2

7x7xH3

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@ @
1

100K_0402_5%

330P_0402_50V7K
DCR: 6.7~7.4mohm

1
4 TDC=8A

PC709

PC710

PC711

PC712

PC715

PC716
PR707
FB Idc: 12A
PR706
Rup

PC708
0_0402_5% 3
ILMT_1.05VS
ILMT BYP
7
+3VALW Isat: 15A Iocp 12A

2
4.7U_0603_6.3V6K
2

2
ILMT_1.05VS
+3VS 1 2 +1.05VS_PGOOD 2
PG LDO
5 3VLDO_1.05VS
FSW 800KHz
1
PR701

PC714
4.7U_0603_6.3V6K
1

10K_0402_5% SY8208DQNC_QFN10_3X3
PC713

SA000061Q00
2

1
PR708
@
2

0_0402_5% PR709
Rdown
2

133K_0402_1%

2
(31) +1.05VS_PGOOD

B
The current limit is set to 8A, 12A or 16A when this pin B
is pull low, floating or pull high
VFB=0.6V
Vout=0.6V* (1+Rup/Rdown)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+1.05VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, October 30, 2013 Sheet 52 of 59
5 4 3 2 1
 5 4 3 2 1

D D

7x7xH3
DCR: 28~33mohm
PC1211 PR1207
Idc: 5.5A @EMI@ @EMI@
P-MOS Isat: 6.5A 2 1 2 1

SB00000TJ00 680P_0603_50V7K 4.7_1206_5%

PQ1201 AON7407_DFN8-5
1 PL1201 PD1201 EMI@ PL1202
2 4.7UH_PCMB063T-4R7MS_5.5A_20% HCB2012KF-121T50_0805
3 5 1 2 2 1 1 2
+5VALW SH00000PG00 +12VSP

10U_0805_25V6K
C C
1

1
1500P_0402_50V7K LX_12VSP SS1P4-M3-84A_DO-220AA2

100P_0402_25V8K
4
1

1
PC1205

PC1204

PC1214
1

88.7K_0402_1%

1
PR1204 PC1210
100K_0402_1% 0.022U_0402_25V7K 2 10U_0805_25V6K PR1203

2200P_0402_50V7K
10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2

PC1206

@EMI@ PC1213

@EMI@ PC1212
2

2
6

1
2 1 PU1201 @

PC1207

PC1208

PC1209
LX

LX
1

2
VIN_12VSP 8 2FB_12VSP
PR1205 Vin FB
10K_0402_1% PC1202 0.01U_0402_16V7K
FREQ_12VSP 9 10 1
SS_12VSP 2
FREQ SS
2

PQ1202

1
2N7002KW_SOT323-3 EN_12VSP 3 1COMP_12VSP
D EN COMP
1

@ PR1206 PR1202
1 2 2 10K_0402_1%
35,50,51,52) SUSP#

1
G

GND

GND
0_0402_5%

PAD
S SA00004JV00
3

2
1

@ PC1203 RT9297GQW_WDFN10_3X3 10K_0402_1%

0.1U_0402_10V7K PR1201

11

5
2

2
1
PC1201
4700P_0402_25V7K

2
B B

PJ1201 @
1 2
+12VSP 1 2 +12VS
JUMP_43X39

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/10/30 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
+12V-Boost
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A3 VPUAE 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 53 of 59
5 4 3 2 1
 A B C D

GPU_B+
EMI Part (47.1)
SUPPRE_ FBMA-L11-453215-800LMA90T_1812
PL901 EMI@
1 2
B+ GPU_B+

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
1
PR901

100U_25V_M
+ 2.2_0603_5%

PC1134

1
1
U2_BOOT1 2

@EMI@ PC902

@EMI@ PC903

PC904

PC905

PC901
2 PQ901
1

2
5
SB000010B00
1
PC906 1
0.22U_0603_25V7K

AON6552 1N DFN5X6
2

U2_UGATE1 1 2 4
For intel N15P-GX
PR902 7x7xH4 Imax: 51A
MOSFET: 5x6 DFN 0_0603_5%
DCR: 0.98mohm Peck current: 76.5A
H/S Rds(on): 5mohm(Typ), 8.5mohm(Max) Idc / Isat: 28A OCP: 91.8A

3
2
1
Idsm: 23A@Ta=25C, 18A@Ta=70C Frequency: 450KHz
PL902
0.22UH 20% PCME064T-R22MS0R985 28A +VGA_CORE
L/S Rds(on): 2.8mohm(Typ), 3.8mohm(Max) U2_PHASE1 1 2
Idsm: 33.5A@Ta=25C, 42A@Ta=70C SH00000OY00

PC907

PC909
AON6554 1N DFN5X6-8
5

SB000010G00 PQ902
1 1

560U 2V M D2 LESR4.5M SX H1.9

330U 2V D2 LESR9M EEFSX H1.9
1
PR903 @EMI@ +@ +
4.7_1206_5%

SGA20331E10

SGA00006J00
U2_LGATE1 4 2 2

2
@ PR904 1K_0402_5% ESR: 9mohm

1
1 2 PC911 @EMI@

14.3K_0402_1%
680P_0603_50V7K

PR905

3
2
1
@ PR906 1K_0402_5%

2
1 2 +3V3_AON Rocset +VGA_CORE

2
1 2
NVVDD_PWM_VID (36)
@ PR907 0_0402_1%

PC910
1

330U 2V D2 LESR9M EEFSX H1.9

+@
1

1
PC912 GPU_B+
Rref1

SGA20331E10
1U_0402_6.3V6K PR908 2
2

2 20K_0402_1% 2

PR909
Rboot Rrefadj 2.2_0603_5%

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
2

U2_BOOT2 1 2 PQ903

5
PR910 PR911 @ PR912 0_0402_1% SB000010B00

@EMI@ PC916
1

1
2K_0402_5% 20K_0402_1% 1 2 NVVDD_PSI (36)

@EMI@ PC917

PC918

PC919

PC914
AON6552 1N DFN5X6
1 2 1 2 PC913
@ PC915 47P_0402_50V8J 0.22U_0603_25V7K

2
1 2 2
18K_0402_1%
1

U2_UGATE2 1 2 4
2700P_0402_50V7K
0.01U_0402_16V7K

PR916 PR915
PR914

@ PC920

GPU_VID

1 1K_0402_5% 0_0603_5%
1

Rref2 1 2
PC921

3V3_MAIN_EN (36,45)
2

3
2
1
C PL903 +VGA_CORE
2

2
GPU_REFADJ

0.22UH 20% PCME064T-R22MS0R985 28A

U2_BOOT1
U2_UGATE1
1

U2_PHASE2 1 2
0_0402_5%

GPU_PSI
PR917

GPU_EN

SH00000OY00

PC923
1

AON6554 1N DFN5X6-8

330U 2V D2 LESR9M EEFSX H1.9

5
2

1
GPU_FBRTN PR918 @EMI@ +
4.7_1206_5%

SB000010G00 PQ904

SGA20331E10
2
6

PU901
PR919 +5VS U2_LGATE2 4
REFADJ

PSI

UGATE1

BOOT1
VID

EN

1 2
Rton 357K_0402_1%
GPU_B+ 1 2
1 GPU_REFIN 7 24 U2_PHASE1 PC926 @EMI@
REFIN PHASE1

1
@ PR920 680P_0603_50V7K

3
2
1

2
(37) VSSSENSE_VGA 0_0402_1% @PC925
@PC925 GPU_VREF 8 23 U2_LGATE1 PR921 +5VS
1 2 0.01UF_0402_25V7K VREF LGATE1
2.2_0603_1%
2 GPU_TON 9 22 U2_PWM3
TON GND/PWM3

1
1 2 GPU_FBRTN 10 21
RGND PVCC PR923
1

@ PR922 11 20 U2_LGATE2
TALERT/ISEN2

2.2_0603_1%
0.1U_0603_25V7K

VSNS LAGTE2
1

100_0402_1% @ PC927 PC928 GPU_B+

TSNS/ISEN3

VCC/ISEN1

3 47P_0402_50V8J GPU_COMP 12 19 U2_PHASE2 3

SS PHASE2
2

2
UGATE2

@ PR924
PGOOD

BOOT2

1 2 GPU_FB
0.1U_0603_25V7K
GND

PC929

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6
(37) VCCSENSE_VGA 0_0402_1% PQ905

5
@ PC930 RT8813AGQW_WQFN24_4X4 SB000010B00

@EMI@ PC931
25

13

14

15

16

17

18

1
1 2 Css 0.01U_0402_16V7K SA00005ZV00

@EMI@ PC932

PC933

PC934

PC935
1 2 PU902 SA00005Z710
GPU_TSNS/ISEN3

+VGA_CORE

AON6552 1N DFN5X6
@ PR925 PR927 8 3 U2_UGATE3 1
PR928 2
1 GPU_TALERT/ISEN2

VCC UGATE

2
GPU_VCC/ISEN1

100_0402_1% 1K_0402_5% 2.2_0603_5% PR926

1 2 1 4 1
U2_BOOT3 2 0_0603_5% 4
GPU_PGOOD1

+5VS EN BOOT
U2_UGATE2

0_0402_5% PR929
U2_BOOT2

U2_PWM3 1 2 5 2
PWM PHASE
1
6 7
GND LGATE

3
2
1
PC936 PL904 +VGA_CORE
0.22U_0603_25V7K 0.22UH 20% PCME064T-R22MS0R985 28A
TP 2
U2_PHASE3 1 2
PR930

PR931

PR932
1

RT9610BZQW_WDFN8_2X2
9

SH00000OY00

PC937
1

AON6554 1N DFN5X6-8

330U 2V D2 LESR9M EEFSX H1.9

5

1
+3V3_AON PR933 @EMI@ +
10K_0402_1%

10K_0402_1%

10K_0402_1%
2

4.7_1206_5%

SB000010G00 PQ906

SGA20331E10
2
10K_0402_1%
1

U2_LGATE3 4

1 2
PR934

V0.1A PC939 @EMI@

U2_PHASE3

U2_PHASE2

U2_PHASE1

680P_0603_50V7K
2

3
2
1

2
1 2 1 2
+3VLP
PR938 PH901 DGPU_PWROK (18,36,45)
1

8.66K_0402_1% 100K_0402_1%_NCP15WF104F03RC
PC908
7.68K_0402_1%
2

0.1U_0603_25V7K
2

PR935

4
PU903 4

1 8
VCC TMSNS1
1

2 7
GND RHYST1
3 6
(31) PWR_GPS_DOWN# OT1 TMSNS2
4 5
OT2 RHYST2
G718TM1U_SOT23-8
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2008/09/15 Deciphered Date 2012/07/11 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8813
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 54 of 59
A B C D
 A B C D

1 1

100K_0402_1%_B25/50 4250K
VREF

4700P_0402_16V7K
1

102K_0402_1%

100K_0402_1%

255K_0402_1%

36.5K_0402_1%
1

1
PH1102
EMI Part (47.1)

1
@ PR1102

PC1102

PR1103

@ PR1104

PR1105

PR1106
10K_0402_1%

2
2 SUPPRE_ FBMA-L11-453215-800LMA90T_1812

2
PL1101EMI@
1 2
B+ 1 1
CPU_B+

1000P_0402_16V7K

39K_0402_1%

150K_0402_1%

150K_0402_1%

20K_0402_1%

100U_25V_M

100U_25V_M
@ PR1112

SF000004L00

SF000004L00
1

1
8.06K_0402_5% + + 2.43K_0402_1%

PC1101

PC1135
1 CSP3-1 1 2

PR1107

PR1109

PR1110

PR1111
1
PR1108

PC1103 2 2
1

3.01K_0402_1%
1
PR1113
2

2
39K_0402_1%

PR1101
2

EMI Part (47.1) CSP3

11.8K_0402_1%

0.15U_0402_10V6K

0.15U_0402_10V6K
1
2

1
PR1114

PC1104

PC1105
10K_0402_1%_B25/50 3370K
2
CPU_B+

B-RAM
OCP-I
F-IMAX @EMI@ PC1106 PR1116@EMI@

2
1
SLEWA 680P_0402_50V7K 4.7_1206_5% @ CSN3

10U_0805_25V6K
PR1115

2
1 2 1 2

10U_0805_25V6K

PH1101
1
1 2 O-USR

PC1108
CPU_B+

1
PC1107
16

15

14

13

12

11
10K_0402_1% 10

2
9
PU1101

9
VBAT

SLEWA

THERM

IMON

B-RAMP
OCP-I

F-IMAX

O-USR
5 PGND2 4 1 4
VIN VSW +VCC_CORE
2 CSP1 17 8 1 2 6 3 2 3 2

CSP1 VR_ON VR_ON (31) BOOT_R PGND1

PR1117 2.2_0402_1%
CSN1 18 7 SKIP# 1 2 7 2 PL1104 SH00000U300
CSN1 SKIP# PC1109 .1U_0402_16V7K
BOOT VDD +5VS 0.15UH 20% PCME064T-R15MS0R667 36A

1
CSN2 19
CSN2 PWM1
6 PWM1 PWM3 8 PWM SKIP#
1 1 2 SKIP# 7x7xH4

1
PR1141
CSP2 20 5 PWM2 1.5K_0402_1% PU1104 SA000066Y00 @ PR1118
@PR1118 PC1110 DCR: 0.66mohm
CSP2 PWM2 CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% Idc: 36A
@ 1U_0402_6.3V6K

2
CSP3 21 TPS51633RSMR_QFN32_4X4 4 PWM3 Isat: 45A
CSP3 PWM3

2
CSN3 22 SA000073200 3
CSN3 PGOOD VGATE (31)
GFB 23 2 PR1120
@ PR1119
@PR1119 GFB VDD 2.43K_0402_1%
VR_HOT#

0_0402_5% VFB 24 1 VR_SVID_DAT CSP1-1 1 2

ALERT#
DROOP

VFB VDIO
COMP

1
1 2

10_0402_1%

3.01K_0402_1%
VREF

VCLK
GND

(9) VSSSENSE
PAD
V5A

1
PR1123

PR1122
1 2

PR1124
10K_0402_1%
(9) VCCSENSE
25

26

27

28

29

30

31

32

33

@ PR1121
@PR1121
EMI Part (47.1) EMI Part (47.1) CSP1

11.8K_0402_1%

0.15U_0402_10V6K

0.15U_0402_10V6K
2

1
0_0402_5% PC1111

10K_0402_1%_B25/50 3370K
VR_SVID_ALRT#

1
1U_0402_6.3V6K

PR1125

PC1112

@PC1113
VR_SVID_CLK

@ PC1115 CPU_B+

1
PC1117 @EMI@

PC1116 @EMI@
2.2P_0402_50V8C @EMI@ PC1114 PR1126@EMI@
VR_HOT#

2
1 2 CSN1

2200P_0402_50V7K
PR1127 680P_0402_50V7K 4.7_1206_5%
+3VS

10U_0805_25V6K

10U_0805_25V6K

PH1103
0.1U_0402_25V6

2
3.4K_0402_1% 1 2 1 2

1
PR1128 1 2

PC1118

PC1119
10K_0402_1%

2
1 2
2

2
VREF

9
PR1129 PC1120
10K_0402_1% 330P_0402_50V7K 5 PGND2 4 1 4
PR1130 VIN VSW +VCC_CORE
1

1 2 1 2
PC1121 1 2 6 3 2 3
0.33U_0402_10V6K PC1122 2.2_0402_1% BOOT_R PGND1
2

1 2 7 2 PL1102 SH00000U300
.1U_0402_16V7K
BOOT VDD +5VS 0.15UH 20% PCME064T-R15MS0R667 36A
PWM1 8 PWM SKIP#
1 1 2 SKIP# For intel SB 47W

1
PR1132 PU1102 SA000066Y00 @ PR1131
@PR1131 PC1123 TDC: 33A
10_0402_1% CSD97374CQ4M_SON8_3P5X4P5 0_0402_5%
3 1U_0402_6.3V6K Support Turbo: 95A 3

2
1 2
+5VS OCP setting: 114A
Frequency: 1MHz
1

PR1133
PC1124 2.43K_0402_1% DC_LL: -1.5mV/A
1U_0402_6.3V6K CSP2-1 1 2
2

3.01K_0402_1%
1
PR1134
+VCCIO_OUT EMI Part (47.1) CSP2

11.8K_0402_1%

0.15U_0402_10V6K

0.15U_0402_10V6K
1

1
PR1135

PC1125

@PC1126
10K_0402_1%_B25/50 3370K
2
CPU_B+
@EMI@ PC1127 PR1138@EMI@

2
1
680P_0402_50V7K 4.7_1206_5% CSN2
10U_0805_25V6K

10U_0805_25V6K

2
1

1 2 1 2
130_0402_1%
54.9_0402_1%

PH1104
1

1
PR1136

PR1137

PC1129

PC1130

PC1128
.1U_0402_16V7K
2

2
2

5 PGND2 4 1 4
(9) VR_SVID_CLK
VIN VSW +VCC_CORE
1 2 6 3 2 3
PR1139 2.2_0402_1% BOOT_R PGND1
(9) VR_SVID_ALRT# 1 2 7 2 PL1103 SH00000U300
(9) VR_SVID_DAT PC1131 .1U_0402_16V7K
BOOT VDD +5VS 0.15UH 20% PCME064T-R15MS0R667 36A
PWM2 8 PWM 1 1 2 SKIP#
SKIP#

1
VR_HOT#
(31) VR_HOT# PU1103 SA000066Y00 @ PR1140
@PR1140 PC1132
CSD97374CQ4M_SON8_3P5X4P5 0_0402_5% 1U_0402_6.3V6K

2
1

@ PC1133
@PC1133
47P_0402_50V8J
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CPU_CORE-47W
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
Custom 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Sheet 55 of 59
A B C D
 A
B
C
D

5
5

+VCC_CORE

2 1 2 1 2 1 2 1
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1327 PC1321 PC1311 PC1301

2 1 2 1 2 1 2 1

2
1
+
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1328 PC1322 PC1312 PC1302

+VCC_CORE
2 1 2 1 2 1 2 1

PC1331
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1329 PC1323 PC1313 PC1303

330U_D2_2VM_R9M
2 1 2 1 2 1 2 1
1U_0402_6.3V6K 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
PC1330 PC1324 PC1314 PC1304

2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
PC1338 PC1325 PC1315 PC1305

2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
PC1339 PC1326 PC1316 PC1306

4
4

2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
PC1336 PC1335 @ PC1317 PC1307

2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
@

PC1337 PC1334 PC1318 PC1308

2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
@

PC1340 PC1332 PC1319 PC1309

2 1 2 1 2 1 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M

@
@

PC1341 PC1333 PC1320 PC1310

Issued Date
Security Classification

3
3

2
1

2011/06/24
PC942
22U_0603_6.3V6M 2 1 2 1 2 1
2
1

1U_0402_6.3V6K PC970 PC961

PC947 PC1020 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
+VGA_CORE

22U_0603_6.3V6M 2 1 2 1 2 1
+VGA_CORE

2
1

1U_0402_6.3V6K PC968 PC954

PC948 PC1021 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
2
1

1U_0402_6.3V6K PC969 PC959

PC949 PC1022 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1

Compal Secret Data

Deciphered Date
2
1

1U_0402_6.3V6K PC967 PC946

PC951 PC1023 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1 2 1
2
1

1U_0402_6.3V6K PC966 PC940

PC952 PC1024 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M
22U_0603_6.3V6M 2 1 2 1
Near VGA Core

2
2

2
1

1U_0402_6.3V6K PC943
PC971 PC1025 4.7U_0603_6.3V6M
Under VGA Core

22U_0603_6.3V6M 2 1 2 1

2 1 1U_0402_6.3V6K PC958
2012/07/12

PC1026 4.7U_0603_6.3V6M
PC963 2 1 2 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

4.7U_0603_6.3V6M
2 1 1U_0402_6.3V6K PC944
PC1027 4.7U_0603_6.3V6M
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

PC953 2 1
4.7U_0603_6.3V6M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

2 1 PC965
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

4.7U_0603_6.3V6M
Title

Date:

PC964 2 1
Custom

4.7U_0603_6.3V6M
2 1 PC955
4.7U_0603_6.3V6M
PC960
4.7U_0603_6.3V6M
2 1
Size Document Number

PC962
4.7U_0603_6.3V6M
Wednesday, October 30, 2013
BE_BDW
1
1

Sheet
GB4B-128 package

Compal Electronics, Inc.

56
of
59
PWR-PROCESSOR_DECOUPLING
Rev
0.2
A
B
C
D
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Reason for change PG# Modify List Date Phase

1
D D

C C
9

10

11

12

13

14

B B

15

16

17
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/06/24 Deciphered Date 2012/07/12 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR (PWR)
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom 0.2
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
BE_BDW
Date: Wednesday, October 30, 2013 Sheet 57 of 59
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 4 for HW

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

D
1 D

3
4

C
9 C

10

11

12

13

14

15

16

B
17 B

18

19

20

21

22

23

24

25
A A

26

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2013/01/22 Deciphered Date 2014/01/22 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PIR-HW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 58 of 59
5 4 3 2 1
 5 4 3 2 1

Timing Diagram for G3 or S4-5/M-off (Suspend Well Off) to S0/M0 [non Deep S4/S5 Platform]
+3VLP

T1=NA
EC_ON

D D

T2>100 ms
ON_OFF

T5=110ms T6=100ms
PBTN_OUT#

EC_RSMRST#
T4=110ms

PM_SLP_S5#

PM_SLP_S4#

SYSON T7=0ms

C C

PM_SLP_S3#

T8=20ms
SUSP#

KB_RST# T9=20ms

EC_SCI

VR_ON
T10=100ms
12/11/20

VGATE

B B

PCH_PWROK T11=20ms

SYS_PWROK T12=40ms

H_CPUPWRGD

PM_DRAM_PWRGD

PLT_RST#

A A

Color Command

Signal Names Timing of these signals is set by PCH or processor

Signal Names Timing of these signals should be met by the platform (EC)

Signal Names Timing of these signals is set by IntelR MVP

Signal Names Voltage rails or chip-to-chip buses Security Classification

Issued Date 2013/01/22
Compal Secret Data
2014/01/22 Title
Compal Electronics, Inc.
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-B111P 0.2
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, October 30, 2013 Sheet 59 of 59
5 4 3 2 1