Chapter 3

The LC-3

Instruction Set Architecture

ISA = All of the programmer-visible components
and operations of the computer
• memory organization
 address space -- how may locations can be addressed?
 addressibility -- how many bits per location?
• register set
 how many? what size? how are they used?
• instruction set
 opcodes
 data types
 addressing modes
ISA provides all information needed for someone that wants to
write a program in machine language
(or translate from a high-level language to machine language).

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LC-3 Overview: Memory and Registers
Memory
• address space: 216 locations (16-bit addresses)
• addressability: 16 bits

Registers
• temporary storage, accessed in a single machine cycle
accessing memory generally takes longer than a single cycle
• eight general-purpose registers: R0 - R7
each 16 bits wide
how many bits to uniquely identify a register?
• other registers
not directly addressable, but used by (and affected by)
instructions
PC (program counter), condition codes
5-3

LC-3 Overview: Instruction Set

Opcodes
• 15 opcodes
• Operate instructions: ADD, AND, NOT
• Data movement instructions: LD, LDI, LDR, LEA, ST, STR, STI
• Control instructions: BR, JSR/JSRR, JMP, RTI, TRAP
• some opcodes set/clear condition codes, based on result:
N = negative, Z = zero, P = positive (> 0)
Data Types
• 16-bit 2’s complement integer
Addressing Modes
• How is the location of an operand specified?
• non-memory addresses: immediate, register
• memory addresses: PC-relative, indirect, base+offset

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 5-5

Operate Instructions
Only three operations: ADD, AND, NOT

Source and destination operands are registers

• These instructions do not reference memory.
• ADD and AND can use “immediate” mode,
where one operand is hard-wired into the instruction.

Will show dataflow diagram with each instruction.

• illustrates when and where data moves
to accomplish the desired operation

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NOT (Register)

Note: Src and Dst

could be the same register.
5-7

NOT: Bitwise Logical NOT

Assembler Inst.
NOT DR, SR ; DR = NOT SR

Encoding
1001 DR SR 111111

Example
NOT R2, R6

• Note: Condition codes are set.

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NOT data path
NOT R3, R5

5-9

this zero means “register mode”

ADD/AND (Register)

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5
 this one means “immediate mode”
ADD/AND (Immediate)

Note: Immediate field is

sign-extended.

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ADD: Two's complement 16-bit Addition

Assembler Instruction
ADD DR, SR1, SR2 ; DR = SR1 + SR2 (register addressing)
ADD DR, SR1, imm5 ; DR = SR1 + Sext(imm5) (immediate addressing)

Encoding
0001 DR SR1 0 00 SR2
0001 DR SR1 1 imm5

Examples
ADD R1, R4, R5
ADD R1, R4, # -2

• Note: Condition codes are set

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ADD data path
ADD R1, R4, # -2

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AND: Bitwise AND

Assembler Instruction
AND DR, SR1, SR2 ; DR = SR1 AND SR2
AND DR, SR1, imm5 ; DR = SR1 AND Sext(imm5)

Encoding
0101 DR SR1 0 00 SR2
0101 DR SR1 1 imm5

Examples
AND R2, R3, R6
AND R2, R2, #0 ; Clear R2 to 0
Question: if the immediate value is only 6 bits, how can it mask the whole of R2?

• Note: Condition codes are set.

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Data Movement Instructions
Load -- read data from memory to register
• LD: PC-relative mode
• LDR: base+offset mode
• LDI: indirect mode

Store -- write data from register to memory

• ST: PC-relative mode
• STR: base+offset mode
• STI: indirect mode

Load effective address -- compute address,

save in register
• LEA: immediate mode
• does not access memory

5-15

PC-Relative Addressing Mode

Want to specify address directly in the instruction
• But an address is 16 bits, and so is an instruction!
• After subtracting 4 bits for opcode
and 3 bits for register, we have 9 bits available for address.

Solution:
• Use the 9 bits as a signed offset from the current PC.

9 bits:  256  offset  255

Can form any address X, such that: PC  256  X  PC 255

Remember that PC is incremented as part of the FETCH phase;

This is done before the EVALUATE ADDRESS stage.
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LD (PC-Relative)

5-17

LD: Load Direct

Assembler Inst.
LD DR, LABEL ; DR <= Mem[LABEL]

Encoding
0010 DR PCoffset9

Examples
LD R2, param ; R2 <= Mem[param]

Notes: The LABEL must be within +256/-255 lines of the instruction.

Condition codes are set.

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LD data path
LD R2, x1AF

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ST (PC-Relative)

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 ST: Store Direct
Assembler Inst.
ST SR, LABEL ; Mem[LABEL] <= SR

Encoding
0011 SR offset9

Examples
ST R2, VALUE ; Mem[VALUE] <= R2

Notes: The LABEL must be within +/- 256 lines of the instruction.
Condition codes are NOT set.

5-21

Indirect Addressing Mode

With PC-relative mode, can only address data
within 256 words of the instruction.
• What about the rest of memory?

Solution #1:
• Read address from memory location,
then load/store to that address.

First address is generated from PC and IR

(just like PC-relative addressing), then
content of that address is used as target for load/store.

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LDI (Indirect)

5-23

LDI: Load Indirect

Assembler Inst.
LDI DR, LABEL ; DR <= Mem[Mem[LABEL]]

Encoding
1010 DR PCoffset9

Examples
LDI R2, POINTER ; R2 <= Mem[Mem[POINTER]]

Notes: The LABEL must be within +256/-255 lines of the instruction.

Condition codes are set.

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LDI data path

LDI R3, x1CC

5-25

STI (Indirect)

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 STI: Store Indirect

Assembler Inst.
STI SR, LABEL ; Mem[Mem[LABEL]] <= SR

Encoding
0011 SR offset9

Examples
STI R2, POINTER ; Mem[Mem[POINTER]] <= R2

Notes: The LABEL must be within +/- 256 lines of the instruction.
Condition codes are NOT set.

5-27

Base + Offset Addressing Mode

With PC-relative mode, can only address data
within 256 words of the instruction.
• What about the rest of memory?

Solution #2:
• Use a register to generate a full 16-bit address.

4 bits for opcode, 3 for src/dest register,

3 bits for base register -- remaining 6 bits are used
as a signed offset.
• Offset is sign-extended before adding to base register.

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LDR (Base+Offset)

5-29

LDR: Load Base+Index

Assembler Inst.
LDR DR, BaseR, offset ; DR <= Mem[ BaseR+SEXT( IR[5:0] )]

Encoding
0110 DR BaseR offset6

Examples
LD R2, R3, #15 ; R2 <= Mem[(R3)+15]

Notes: The 6 bit offset is a 2’s complement number, so range is -32 to +31.
Condition codes are set.

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LDR data path

LDR R1, R2, x1D

5-31

STR (Base+Offset)

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STR: Store Base+Index

Assembler Inst.
STR SR, BaseR, offset6 ; Mem[BaseR+SEXT(offset6)] <= (SR)

Encoding
0111 SR BaseR offset6

Examples
STR R2, R4, #15 ; Mem[R4+15] <= (R2)

Notes: The offset is sign-extended to 16 bits.

Condition codes are not set.

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Load Effective Address

Computes address like PC-relative (PC plus signed offset)
and stores the result into a register.

Note: The address is stored in the register,

not the contents of the memory location.

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LEA (Immediate)

5-35

LEA: Load Effective Address

Assembler Inst.
LEA DR, LABEL ; DR <= LABEL

Encoding
1110 DR offset9 (i.e. address of LABEL = (PC) + SEXT(offset9)

Examples
LEA R2, DATA ; R2 gets the address of DATA

Notes: The LABEL must be within +/- 256 lines of the instruction.
Condition codes are set.

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LEA data path
LEA R5, # -3

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Example
PC = x30F6
Address Instruction Comments

x30F6 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 1 R1  PC – 3 = x30F4

x30F7 0 0 0 1 0 1 0 0 0 1 1 0 1 1 1 0 R2  R1 + 14 = x3102

M[PC - 5]  R2
x30F8 0 0 1 1 0 1 0 1 1 1 1 1 1 0 1 1 M[x30F4]  x3102

x30F9 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0

x30FA 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 1 R2  R2 + 5 = 5

M[R1+14]  R2
x30FB 0 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 M[x3102]  5

R3  M[M[x30F4]]
x30FC 1 0 1 0 0 1 1 1 1 1 1 1 0 1 1 1 R3  M[x3102]
R3  5

opcode
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Addressing Examples
What is the EA (Effective Adress) for the following instructions?
Given:
PC = x2081, R6 = x2035, LOC = x2044, Mem[x2044] = x3456

LDI R2, LOC ADD R1, R3, R2

Encoding: Register addressing:
1010 010 1 1100 0011 DR = R1, SR1 = R3, SR2 = R2
DR <= ?
Indirect addressing:
EA = Mem[x2044] = x3456 ADD R5, R1, #15
Immediate addressing:
LDR R1, R6, #12 DR = R5, SR1 = R1, S2 = 15
Encoding: DR <= ?
0110 001 110 00 1100
Base+Offset addressing: LD R1, LOC
EA = (R6)+12 = x2035 + x000C Direct addressing:
= x2041 DR <= ?

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Control Instructions
Used to alter the sequence of instructions
(by changing the Program Counter)

Conditional Branch
• branch is taken if a specified condition is true
signed offset is added to PC to yield new PC
• else, the branch is not taken
PC is not changed, points to the next sequential instruction

Unconditional Branch (or Jump)

• always changes the PC

TRAP
• changes PC to the address of an OS “service routine”
• routine will return control to the next instruction (after TRAP)
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Condition Codes
LC-3 has three condition code registers:
N -- negative
Z -- zero
P -- positive (greater than zero)

Set by any instruction that writes a value to a register

(ADD, AND, NOT, LD, LDR, LDI, LEA)

Exactly one will be set at all times

• Based on the last instruction that altered a register

5-41

Branch Instruction
Branch specifies one or more condition codes.
If the set bit is specified, the branch is taken.
• PC-relative addressing:
target address is made by adding signed offset (IR[8:0])
to current PC.
• Note: PC has already been incremented by FETCH stage.
• Note: Target must be within 256 words of BR instruction.

If the branch is not taken,

the next sequential instruction is executed.

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 BR (PC-Relative)

5-43
What happens if bits [11:9] are all zero? All one?

BR: Conditional Branch

Assembler Inst.
BRx LABEL
where x = n, z, p, nz, np, zp, or nzp
Branch to LABEL if the selected condition code are set

Encoding
0000 n z p PCoffset9

Examples
BRzp LOOP ; branch to LOOP if previous op returned zero or positive.

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 BR data path
BRz x0D9

5-45

Building loops using BR

Counter control Sentinel control

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Using Branch Instructions
Compute sum of 12 integers.
Numbers start at location x3100. Program starts at location x3000.

R1  x3100
R3  0
R2  12

R4  M[R1]
R3  R3+R4
R2=0?
NO R1  R1+1
R2  R2-1

YES

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Sample Program
Address Instruction Comments
x3000 1 1 1 0 0 0 1 0 1 1 1 1 1 1 1 1 R1  x3100 (PC+0xFF)

x3001 0 1 0 1 0 1 1 0 1 1 1 0 0 0 0 0 R3  0

x3002 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0

x3003 0 0 0 1 0 1 0 0 1 0 1 0 1 1 0 0 R2  12

x3004 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 If Z, goto x300A (PC+5)

x3005 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 Load next value to R4

x3006 0 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 Add to R3

x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 Increment R1 (pointer)

X3008 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 1 Decrement R2 (counter)

x3009 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 0 Goto x3004 (PC-6)

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JMP (Register)
Jump is an unconditional branch -- always taken.
• Target address is the contents of a register.
• Allows any target address.

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JMP: Jump or Go To

Assembler Inst.
JMP BaseR
Take the next instruction from the address stored in BaseR

Encoding
1100 000 BaseR 00 0000

Example
JMP R5 ; if (R5) = x3500, the address x3500 is written to the PC

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TRAP

Calls a service routine, identified by 8-bit “trap vector.”

vector routine
x23 input a character from the keyboard
x21 output a character to the monitor
x25 halt the program

When routine is done,

PC is set to the instruction following TRAP.
(We’ll talk about how this works later.)

5-51

TRAP: Invoke a system routine

Assembler Inst.
TRAP trapvec

Encoding
1111 0000 trapvect8

Examples
TRAP x23

Note: R7 <= (PC) (for eventual return)

PC <= Mem[Zext(trapvect8)]

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Another example
Count the occurrences of a character in a file
• Program begins at location x3000
• Read character from keyboard
• Load each character from a “file”
 File is a sequence of memory locations
 Starting address of file is stored in the memory location
immediately after the program
• If file character equals input character, increment counter
• End of file is indicated by a special ASCII value: EOT (x04)
• At the end, print the number of characters and halt
(assume there will be less than 10 occurrences of the character)

A special character used to indicate the end of a sequence

is often called a sentinel.
• Useful when you don’t know ahead of time how many times
to execute a loop.

5-53

Flow Chart

Count = 0
(R2 = 0) YES
Convert count to
Done?
(R1 ?= EOT)
ASCII character
(R0 = x30, R0 = R2 + R0)

Ptr = 1st file character NO

(R3 = M[x3012])
Print count
YES Match? NO (TRAP x21)
(R1 ?= R0)
Input char
from keybd
(TRAP x23)

HALT
Incr Count (TRAP x25)

Load char from file (R2 = R2 + 1)

(R1 = M[R3])

Load next char from file

(R3 = R3 + 1, R1 = M[R3])

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Program (1 of 2)
Address Instruction Comments
x3000 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 R2  0 (counter)

x3001 0 0 1 0 0 1 1 0 0 0 0 1 0 0 0 0 R3  M[x3012] (ptr)

x3002 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 Input to R0 (TRAP x23)

x3003 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 R1  M[R3]

x3004 0 0 0 1 1 0 0 0 0 1 1 1 1 1 0 0 R4  R1 – 4 (EOT)

x3005 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 If Z, goto x300E

x3006 1 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 R1  NOT R1

x3007 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 1 R1  R1 + 1

X3008 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 R1  R1 + R0

x3009 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 If N or P, goto x300B

5-55

Program (2 of 2)
Address Instruction Comments
x300A 0 0 0 1 0 1 0 0 1 0 1 0 0 0 0 1 R2  R2 + 1

x300B 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 R3  R3 + 1

x300C 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 R1  M[R3]

x300D 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 0 Goto x3004

x300E 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 R0  M[x3013]

x300F 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 R0  R0 + R2

x3010 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 Print R0 (TRAP x21)

x3011 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0 1 HALT (TRAP x25)

X3012 Starting Address of File

x3013 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 ASCII x30 (‘0’)

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 LC-3
Data Path
Revisited

Filled arrow
= info to be processed.
Unfilled arrow
= control signal.

5-57

Data Path Components

Global bus
• special set of wires that carry a 16-bit signal
to many components
• inputs to the bus are “tri-state devices,”
that only place a signal on the bus when they are enabled
• only one (16-bit) signal should be enabled at any time
control unit decides which signal “drives” the bus
• any number of components can read the bus
register only captures bus data if it is write-enabled by the
control unit

Memory
• Control and data registers for memory and I/O devices
• memory: MAR, MDR (also control signal for read/write)
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Data Path Components
ALU
• Accepts inputs from register file
and from sign-extended bits from IR (immediate field).
• Output goes to bus.
used by condition code logic, register file, memory

Register File
• Two read addresses (SR1, SR2), one write address (DR)
• Input from bus
result of ALU operation or memory read
• Two 16-bit outputs
used by ALU, PC, memory address
data for store instructions passes through ALU

5-59

Data Path Components

PC and PCMUX
• Three inputs to PC, controlled by PCMUX
1. PC+1 – FETCH stage
2. Address adder – BR, JMP
3. bus – TRAP (discussed later)

MAR and MARMUX

• Two inputs to MAR, controlled by MARMUX
1. Address adder – LD/ST, LDR/STR
2. Zero-extended IR[7:0] -- TRAP (discussed later)

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Data Path Components
Condition Code Logic
• Looks at value on bus and generates N, Z, P signals
• Registers N, Z, P are set only when control unit enables them
(LD.CC)
only certain instructions set the codes
(ADD, AND, NOT, LD, LDI, LDR, LEA)

Control Unit – Finite State Machine

• On each machine cycle, changes control signals for next phase
of instruction processing
who drives the bus? (GatePC, GateALU, …)
which registers are write enabled? (LD.IR, LD.REG, …)
which operation should ALU perform? (ALUK)
…
• Logic includes decoder for opcode, etc. 5-61

HOMEWORK

Input two values from 0-9 to R2 and R3.

Compute the product and put it in R4, then
print it out on screen.

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 Conclusion!

5-63

Three Basic Constructs

There are three basic ways to decompose a task:

Task

True Test False

Test False
condition
Subtask 1 condition

True
Subtask 1 Subtask 2
Subtask 2 Subtask

Sequential Conditional Iterative

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Sequential
Do Subtask 1 to completion,
then do Subtask 2 to completion, etc.

Get character
input from
keyboard

Count and print the Examine file and

occurrences of a count the number
character in a file of characters that
match

Print number
to the screen

6-65

Conditional
If condition is true, do Subtask 1;
else, do Subtask 2.

True file char False

= input?

Test character.
If match, increment Count = Count + 1
counter.

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Iterative
Do Subtask over and over,
as long as the test condition is true.

more chars False

to check?
Check each element of
the file and count the
True
characters that match.

Check next char and

count if matches.

6-67

Problem Solving Skills

Learn to convert problem statement
into step-by-step description of subtasks.

• Like a puzzle, or a “word problem” from grammar school math.

What is the starting state of the system?
What is the desired ending state?
How do we move from one state to another?

• Recognize English words that correlate to three basic constructs:

“do A then do B”  sequential
“if G, then do H”  conditional
“for each X, do Y”  iterative
“do Z until W”  iterative

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LC-3 Control Instructions
How do we use LC-3 instructions to encode
the three basic constructs?

Sequential
• Instructions naturally flow from one to the next,
so no special instruction needed to go
from one sequential subtask to the next.

Conditional and Iterative

• Create code that converts condition into N, Z, or P.
Example:
Condition: “Is R0 = R1?”
Code: Subtract R1 from R0; if equal, Z bit will be set.
• Then use BR instruction to transfer control to the proper subtask.
6-69

Code for Conditional

PC offset to
Exact bits depend address C
on condition
being tested

Unconditional branch
to Next Subtask
PC offset to
address D

Assuming all addresses are close enough that PC-relative branch can be used.
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Code for Iteration
PC offset to
Exact bits depend address C
on condition
being tested

Unconditional branch
to retest condition
PC offset to
address A

Assuming all addresses are on the same page.

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