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tmp100 q1 PDF
tmp100 q1 PDF
TMP100-Q1, TMP101-Q1
SBOS581A – SEPTEMBER 2011 – REVISED MAY 2017
TMP100-Q1 and TMP101-Q1 Temperature Sensor With I2C and SMBus Interface with
Alert Function in SOT-23 Package
1 Features 3 Description
1• AEC-Q100 Qualified with the Following Results: The TMP100-Q1 and TMP101-Q1 devices are digital
temperature sensors ideal for negative temperature
– Temperature Grade 1: −55°C to +125°C coefficient (NTC) and positive temperature coefficient
Operating Temperature Range (PTC) thermistor replacement. The devices offer a
– HBM ESD Component Classification Level 2 typical accuracy of ±1°C without requiring calibration
– CDM ESD Component Classification Level C5 or external component signal conditioning. Device
temperature sensors are highly linear and do not
• Digital Output: SMBus™, Two-Wire, and I2C require complex calculations or look-up tables to
Interface Compatibility derive the temperature. The on-chip, 12-bit ADC
• Resolution: 9 to 12 Bits, User-Selectable offers resolutions down to 0.0625°C. The devices are
• Accuracy: available in 6-Pin SOT-23 packages.
– ±1°C (Typical) from –55°C to 125°C The TMP100-Q1 and TMP101-Q1 devices feature
– ±2°C (Maximum) from –55°C to 125°C SMBus, Two-Wire, and I2C interface compatibility.
The TMP100-Q1 device allows up to eight devices on
• Low Quiescent Current: 45-μA, 0.1-μA Standby one bus. The TMP101-Q1 device offers an SMBus
• Wide Supply Range: 2.7 V to 5.5 V Alert function with up to three devices per bus.
• TMP100-Q1 Features Two Address Pins The TMP100-Q1 and TMP101-Q1 devices are ideal
• TMP101-Q1 Features One Address Pin and an for extended temperature measurement in a variety of
ALERT Pin communication, computer, consumer, environmental,
• 6-Pin SOT-23 Package industrial, and instrumentation applications.
The TMP100-Q1 and TMP101-Q1 devices are
2 Applications specified for operation over a temperature range of
−55°C to 125°C.
• Power-Supply Temperature Monitoring
• Battery Management Device Information(1)
• Thermostat Controls PART NUMBER PACKAGE BODY SIZE (NOM)
• Automotive: TMP100-Q1 SOT-23 (6) 2.90 mm × 1.60 mm
– Head Unit TMP101-Q1 SOT-23 (6) 2.90 mm × 1.60 mm
– Cluster (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Body Electronics
– Lighting
4 Simplified Schematics
Temperature Temperature
Diode Diode
1 Control 6 1 Control 6
SCL Temp. SDA SCL Temp. SDA
Logic Logic
Sensor Sensor
∆Σ ∆Σ
2 Serial 5 2 Serial 5
GND ADC ADD0 GND ADC ADD0
Interface Interface
Converter Converter
Config Config
3 4 3 4
ADD1 OSC and Temp V+ ALERT OSC and Temp V+
Register Register
TMP100-Q1 TMP101-Q1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP100-Q1, TMP101-Q1
SBOS581A – SEPTEMBER 2011 – REVISED MAY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 14
2 Applications ........................................................... 1 8.5 Programming........................................................... 15
3 Description ............................................................. 1 9 Application and Implementation ........................ 19
4 Simplified Schematics........................................... 1 9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 19
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 21
7 Specifications......................................................... 4 11 Layout................................................................... 21
11.1 Layout Guidelines ................................................. 21
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Examples................................................... 21
7.2 ESD Ratings ............................................................ 4
7.3 Recommended Operating Conditions....................... 4 12 Device and Documentation Support ................. 23
7.4 Thermal Information ................................................. 4 12.1 Related Links ........................................................ 23
7.5 Electrical Characteristics........................................... 5 12.2 Receiving Notification of Documentation Updates 23
7.6 Timing Requirements ................................................ 6 12.3 Community Resources.......................................... 23
7.7 Typical Characteristics .............................................. 7 12.4 Trademarks ........................................................... 23
12.5 Electrostatic Discharge Caution ............................ 23
8 Detailed Description .............................................. 8
12.6 Glossary ................................................................ 23
8.1 Overview ................................................................... 8
8.2 Functional Block Diagram ......................................... 8 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................... 9
Information ........................................................... 24
5 Revision History
Changes from Original (September 2011) to Revision A Page
• Added the Device Information table, Pin Configuration and Functions section, Handling Ratings table, Timing
Requirements table, Switching Characteristics tableFeature Description section , Device Functional Modes section,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
DBV Package
6-Pin SOT-23
Top View
TMP100-Q1
SCL 1 6 SDA
GND 2 5 ADD0
ADD1 3 4 V+
TMP100-Q1
DBV Package
6-Pin SOT-23
Top View
TMP101-Q1
SCL 1 6 SDA
GND 2 5 ADD0
ALERT 3 4 V+
TMP101-Q1
Pin Functions
PIN
NO. I/O DESCRIPTION
NAME
TMP100-Q1 TMP101-Q1
ADD0 5 5 I Address select. Connect to GND, V+, or leave floating.
ADD1 3 — I Address select. Connect to GND, V+, or leave floating.
ALERT — 3 O Overtemperature alert. Open-drain output; requires a pullup resistor.
GND 2 2 — Ground
SCL 1 1 I Serial clock. Open-drain output; requires a pullup resistor.
SDA 6 6 I/O Serial data. Open-drain output; requires a pullup resistor.
V+ 4 4 I Supply voltage, 2.7 V to 5.5 V
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Power supply, V+ 7.5 V
(2)
Input voltage –0.5 7.5 V
Operating temperature –55 125 °C
Junction temperature, TJ 150 °C
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input voltage rating applies to all TMP100-Q1 and TMP101-Q1 input voltages.
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
70 1
0.9
0.8
60 0.7
V+ = 5 V
0.6
ISD (µA)
I Q (µA)
0.5
50
0.4
0.3
V+ = 27 V
0.2
40
0.1
0
Serial Bus Inactive
30 −0.1
−60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
1.5
Temperature Error (°C)
Conversion Time (ms)
1.0
350
V+ = 5 V 0.5
0.0
−0.5
300
V+ = 2.7 V
−1.0
−1.5
NOTE: 12−bit resolution. 3 Typical Units NOTE: 12−bit resolution.
250 −2.0
−60 −40 −20 0 20 40 60 80 100 120 140 −60 −40 −20 0 20 40 60 80 100 120 140
Temperature (°C) Temperature (°C)
160
125°C
140
25°C
120
I Q (µA)
100
125°C
80
25°C −55°C
60
40
−55°C
20
FAST MODE Hs MODE
0
10k 100k 1M 10M
SCL Frequency (Hz)
8 Detailed Description
8.1 Overview
The TMP100-Q1 and TMP101-Q1 devices are digital temperature sensors optimal for thermal management and
thermal protection applications. The TMP100-Q1 and TMP101-Q1 devices are Two-Wire, SMBus, and I2C
interface-compatible. These devices are specified over a operating temperature range of −55°C to 125°C. The
Functional Block Diagram section shows the internal block diagrams of the TMP100-Q1 and TMP101-Q1
devices.
The temperature sensor in the TMP100-Q1 and TMP101-Q1 devices is the chip itself. Thermal paths run through
the package leads as well as the plastic package. The package leads provide the primary thermal path because
of the lower thermal resistance of the metal. The GND pin of the TMP100-Q1 or TMP101-Q1 is directly
connected to the metal lead frame, and is the best choice for thermal input.
Temperature Temperature
Diode Diode
1 Control 6 1 Control 6
SCL Temp. SDA SCL Temp. SDA
Logic Logic
Sensor Sensor
∆Σ ∆Σ
2 Serial 5 2 Serial 5
GND ADC ADD0 GND ADC ADD0
Interface Interface
Converter Converter
Config Config
3 4 3 4
ADD1 OSC and Temp V+ ALERT OSC and Temp V+
Register Register
TMP100-Q1 TMP101-Q1
The TMP101-Q1 device features one address pin and an ALERT pin, allowing up to three devices to be
connected per bus. Pin logic levels are described in Table 3. The address pins of the TMP100-Q1 and TMP101-
Q1 devices are read after reset or in response to an I2C address acquire request. Following reading, the state of
the address pins is latched to minimize power dissipation associated with detection.
SCL
SDA
t(BUF)
tRD tFD
P S S P
1 9 1 9
SCL …
SDA 1 0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Master TMP100-Q1 orTMP101-Q1 TMP100-Q1 or TMP101-Q1
Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte
1 9 1 9
SCL
(Continued)
SDA
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
ACK By ACK By Stop By
TMP100-Q1 or TMP101-Q1 TMP100-Q1 or TMP101-Q1 Master
Frame 3 Data Byte 1 Frame 4 Data Byte 2
1 9 1 9
SCL …
SDA 1 0 0 1 A2 A1 A0 R/W 0 0 0 0 0 0 P1 P0 …
Start By ACK By ACK By
Master TMP100-Q1orTMP101-Q1 TMP100-Q1or TMP101-Q1
Frame 1 I2C Slave Address Byte Frame 2 Pointer Register Byte
1 9 1 9
SCL …
(Continued)
SDA
1 0 0 1 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 …
(Continued)
Start By ACK By From ACK By
Master TMP100-Q1orTMP101-Q1 TMP100-Q1orTMP101-Q1 Master
Frame 3 I2C Slave Address Byte Frame 4 Data Byte 1 Read Register
1 9
SCL
(Continued)
SDA
D7 D6 D5 D4 D3 D2 D1 D0
(Continued)
From ACK By Stop By
TMP100-Q1orTMP101-Q1 Master Master
Frame 5 Data Byte 2 Read Register
ALERT
1 9 1 9
SCL
SDA 0 0 0 1 1 0 0 R/W 1 0 0 1 A2 A1 A0 S ta tu s
8.5 Programming
8.5.1 Pointer Register
Figure 10 shows the internal register structure of the TMP100-Q1 and TMP101-Q1 devices. The 8-bit Pointer
Register of the TMP100-Q1 and TMP101-Q1 devices is used to address a given data register. The Pointer
Register uses the two LSBs to identify which of the data registers respond to a read or write command. Table 4
identifies the bits of the Pointer Register byte. Table 5 describes the pointer address of the registers available in
the TMP100-Q1 and TMP101-Q1 devices. The power-up reset value of P1 and P0 is 00.
Pointer
Register
Temperature
Register
SCL
Configuration
Register
I/O
Control
Interface
TLOW
Register
SDA
THIGH
Register
THIGH
Measured
Temperature
TLOW
TMP101-Q1ALERT PIN
(Comparator Mode)
POL = 0
TMP101-Q1ALERT PIN
(Interrupt Mode)
POL = 0
TMP101-Q1ALERT PIN
(Comparator Mode)
POL = 1
TMP101-Q1ALERT PIN
(Interrupt Mode)
POL = 1
All 12 bits for the Temperature, THIGH, and TLOW registers are used in the comparisons for the ALERT function for
all converter resolutions. The three LSBs in THIGH and TLOW can affect the ALERT output even if the converter is
configured for 9-bit resolution.
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
TMP100-Q1 TMP101-Q1
Two-Wire 1 6 Two-Wire 1 6
Host Controller SCL SDA Host Controller SCL SDA
2 5 2 5
GND ADD0 GND ADD0
3 4 3 4
ADD1 V+ ALERT V+
Figure 12. Typical Connections of the TMP100-Q1 Figure 13. Typical Connections of the TMP101-Q1
75
70
65
60
55
50
45
40
35
30
25
-1 1 3 5 7 9 11 13 15 17 19
Time (s)
11 Layout
Pull-Up Resistors
SCL SDA
GND ADD0
Supply Voltage
ADD1 V+
Supply Bypass
Capacitor
Heat Source
Pull-Up Resistors
SCL SDA
GND ADD0
Supply Voltage
ALERT V+
Supply Bypass
Capacitor
Heat Source
12.4 Trademarks
E2E is a trademark of Texas Instruments.
SMBus is a trademark of NXP Semiconductors.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 6-Feb-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)
TMP100AQDBVRQ1 ACTIVE SOT-23 DBV 6 3000 Green (RoHS SN Level-2-260C-1 YEAR -40 to 125 100Q
& no Sb/Br)
TMP101NAQDBVRQ1 ACTIVE SOT-23 DBV 6 3000 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 DUGQ
& no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 6-Feb-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214840/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.15 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214840/B 03/2018
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214840/B 03/2018
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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