electronics

Article
An Accurate DDS Method Using Compound
Frequency Tuning Word and Its
FPGA Implementation
Yuqing Hou, Changlong Li and Sheng Tang *
School of Information Science and Technology, Northwest University, Xi’an 710000, China;
houyuqin@nwu.edu.cn (Y.H.); licongg@stumail.nwu.edu.cn (C.L.)
* Correspondence: tangsheng@nwu.edu.cn; Tel.: +86-132-0169-3218




Received: 2 October 2018; Accepted: 14 November 2018; Published: 16 November 2018


Abstract: Because of its high resolution, low cost, small volume, low power dissipation and less
conversion time consumption, the direct digital synthesizer (DDS) method has been applied more and
more in the fields of frequency synthesis and signal generation. However, only a limited number of
precise frequency signals can be synthesized by the traditional DDS, for the reason that its accumulator
modulus is fixed, and its frequency tuning word must be integer. In this paper, a precise DDS method
using compound frequency tuning word is proposed, which improves the accuracy of synthesized
signals at any frequency points on the premise of guaranteeing the stability of synthesized signals.
In order to verify the effectiveness of the new method, a DDS frequency synthesizer based on FPGA
is designed and implemented. Taking the rubidium atomic clock PRS10 as standard frequency
source, the experiments shows that the frequency stability of the synthesized signal is better than
8.0 × 10−12 /s, the relative frequency error is less than 4.8 × 10−12 , and that the frequency accuracy is
improved by three orders of magnitude compared with the traditional DDS method.

Keywords: direct digital synthesizer (DDS); frequency tuning word (FTW); stability; accuracy

1. Introduction
With the development of society, the functionality and complexity of electronic devices is
increasing. Frequency synthesizer, as a common signal generator, has been widely applied in many
fields. Related researches have more and more requirements for the accuracy and stability of the
frequency synthesizer, especially in the fields of satellite positioning, aerospace, surveying and
mapping, guidance and high-speed communication [1,2]. The signal generator is a kind of instrument
with a long history. With the birth of electronic technology, signal generation circuits have appeared
in the 1920s. By the 1940s, there were standard signal generators that were mainly used to measure
various receivers, and pulse signal generators were invented. Since the 1960s, signal generators have
developed rapidly. In this period, analog electronics technology was generally used. The circuit of
signal generators was composed of discrete components. RC and LC signal generation circuits play an
important role in the development process. The RC circuit composed of resistor R and capacitor C can
produce sine waves with continuous amplitude and adjustable frequency. The LC signal generating
circuit composed of inductor L and capacitor C can produce less high-order harmonics and better
output waveform. With the development of science and technology, digital circuits have entered the
field of signal synthesis, and the way of signal synthesis has made rapid progress, many signal synthesis
methods have been designed. Modern synthetic signal methods include direct analog frequency
synthesis, phase-locked frequency synthesis and direct digital frequency synthesis. There are three
kinds of synthesized frequency methods: direct analog frequency synthesis, phase-locked frequency

Electronics 2018, 7, 330; doi:10.3390/electronics7110330 www.mdpi.com/journal/electronics

Electronics 2018, 7, 330 2 of 14

synthesis and direct digital frequency synthesis [3]. Direct analog frequency synthesis uses one or
more different transistors to design RC oscillator or LC oscillator as reference signal sources, and the
output signals are directly generated by frequency doubling, frequency division and mixing, and the
signals obtained by this method have the characteristics of high frequency stability and fast frequency
conversion. But both of the hardware debugging and the spurious suppression are not easy in the
implementation of this method. Phase-locked frequency synthesis, also known as indirect synthesis
method, uses one or more standard frequency sources to generate a large number of harmonics or
combined frequencies by mixing and dividing harmonic generators. Then, the phase-locked loop
(PLL) is used to lock the frequency of the voltage controlled oscillator (VCO) to a certain harmonic or
combination frequency. The required frequency output is indirectly generated by a voltage-controlled
oscillator. The advantage of this method is that the phase-locked loop is equivalent to a narrow
band tracking filter. Therefore, it can select the desired frequency signal well, suppress the spurious
components, and avoid the use of a large number of filters, which are conducive to integration and
miniaturization. The disadvantage of this method is slow response [4,5]. Direct digital frequency
synthesis is based on the concept of phase to synthesize frequencies and adopts the technology of
digital sampling and storage. Because the direct digital synthesizer (DDS) is an open-loop system
without any feedback link, the frequency conversion time is very short. Besides, the method can be
realized digitally and conveniently, and it is small and light in weight. The DDS method in the design
of frequency synthesizer has gradually become a mainstream method in the current field of electronic
measurement and testing [6].
Normally there are two main ways to design and implement a real frequency synthesizer. One is
to use a dedicated DDS integrated chip to synthesize frequency. The other is to use FPGA to achieve
DDS frequency synthesis. The first method is usually realized by using a microprocessor to drive
the DDS integrated chip. In the given working mode of the DDS integrated chip, the internal circuit
calculates the operating parameters of the kernel and synthesizes the frequency. Then, the analog
signal is obtained by further processing by the later stage [7,8]. Due to the technical limitation of the
DDS integrated chip, there are unavoidable performance defects in this kind of frequency synthesizer.
The dedicated DDS integrated chip has a fixed number of phase accumulator bits and lacks flexibility.
The number of its phase accumulators is relatively small, and the frequency resolution is relatively low.
For example, we often use chip AD9913 to generate frequency signals. The bit width of its internal
phase accumulator is 32 bits. When the reference frequency is 100 MHz, the resolution is 0.023 Hz.
Even though 0.023 Hz is not a bad resolution for most applications, the typical accumulator-based DDS
is not capable of generating some useful frequencies (like precisely 10 MHz) and cannot meet the high
precision requirements of some special equipment or engineering [9]. When expecting to get precisely
10 MHz, the AD9913 can only produce an approximate frequency of 9.999999986030161380 MHz.
FPGA is a new type of digital circuit. Its circuit function is programmable and customizable,
which is different from the traditional integrated circuit with the structure and function of a fixed
circuit. FPGA technology has overturned the traditional design, tape-out and packaging process of
digital circuits. New digital circuits are developed directly on the finished FPGA chip. It overcomes
the shortcomings of the internal structure of the DDS chip and improves the flexibility of the chip,
which enlarges the user range and application fields of special digital circuits. Each logic gate in the
FPGA chip performs a logical operation at every clock cycle. Therefore, FPGA is essentially a very
large-scale parallel computing device, which is very suitable for developing DDS devices with high
speed, high accuracy and high flexibility [10]. The DDS device based on FPGA is usually composed of
a phase accumulator, a waveform memory and a digital multiplier [11,12]. The phase accumulator
accumulates the frequency tuning word loop to get the phase address; the size of the frequency
tuning word determines the output frequency value; waveform memory stores a sampling point for a
periodic output waveform; the phase address of the phase accumulator acts as the reading address
of the waveform memory, from which the waveform sample points are taken out to form the digital
waveform, and then the analog signal is obtained by further processing [13].
Electronics 2018, 7, x FOR PEER REVIEW 3 of 14

of the waveform
Electronics 2018, 7, 330memory, from which the waveform sample points are taken out to form the digital 3 of 14
waveform, and then the analog signal is obtained by further processing [13].
As mentioned above, the frequency synthesis principles of the dedicated DDS integrated chip
and theAs FPGA
mentionedmethod above, the frequency
are basically synthesis
the same. Both ofprinciples
them useof thethe dedicated
phase DDS integrated
accumulator chip
to recursively
and the FPGA method are basically the same. Both of them use the
sum the clock rate and frequency tuning word, and synthesize the frequency by means of the phase accumulator to recursively
sum the table.
look-up clock rate
The and frequency
phase tuning
accumulator word, and
modulus synthesize the
of traditional DDSfrequency
is usuallybya means of the and
fixed value, look-up
the
table. The phase accumulator modulus of traditional DDS is usually a fixed
frequency tuning words must also be positive integers, so this method can only synthesize a limited value, and the frequency
tuning words
number must frequency
of precise also be positive integers,
signals. However, so this
somemethod can only
practical synthesize
projects a limited
and systems (as number
shown in of
precise frequency
Figure 1) usuallysignals.
requireHowever,
precise some practical
frequency projects and
synthesizers tosystems
generate (astheir
shown in Figurefrequency
reference 1) usually
signals. Sometimes, these reference frequency signals must have a special frequency value.these
require precise frequency synthesizers to generate their reference frequency signals. Sometimes, For
reference frequency signals must have a special frequency value. For
example, in the communication system, in order to ensure the accuracy and effectiveness of example, in the communication
system, in order
information to ensureeach
transmission, the accuracy
base stationandgenerally
effectiveness needs of to
information
configure transmission,
a communication eachclock
base
station generally needs to configure a communication clock subsystem.
subsystem. The communication clock subsystem is the basic guarantee for efficient and orderly The communication clock
subsystemofis the
operation the whole
basic guarantee
system. Afor efficient
5 MHz or 10 and orderly
MHz operation
frequency of the whole
synthesizer system.
is usually theAfrequency
5 MHz or
10 MHz frequency synthesizer is usually the frequency reference of these
reference of these clock subsystems. Another example, the reference frequencies onboard satellite clock subsystems. Another of
example, the reference frequencies onboard satellite of some navigation
some navigation satellite systems is 10.23 MHz. Any frequency error or deviation in the referencesatellite systems is 10.23 MHz.
Any frequency
frequency willerror or deviation
directly in the
affect the reference frequency
navigation will directly
satellite system’s affect the navigation
performance and suchsatellite
errors
system’s performance and such errors accumulated over time will
accumulated over time will result in a significantly large user ranging error varying up toresult in a significantly large user
several
ranging[14].
meters errorThese
varying up to several
special frequencymeters [14].such
signals Theseasspecial
5 MHz, frequency
10 MHzsignals such as
and 10.23 MHz5 MHz, 10 MHz
are hard to
and 10.23 MHz are hard to generate accurately by traditional DDS methods
generate accurately by traditional DDS methods and devices. To solve this problem, a DDS method and devices. To solve this
problem,
using a DDS method
compound usingtuning
frequency compound word frequency
is designedtuning andword is designed in
implemented andthis
implemented
paper, which in this
is
paper, which is expected to further improve the accuracy of synthetic frequency
expected to further improve the accuracy of synthetic frequency under the condition of guaranteeing under the condition of
guaranteeing
frequency frequency stability.
stability.

Figure 1. Applications of high precision DDS.

Figure 1. Applications of high precision DDS.
2. Defects of Traditional DDS
2. Defects of Traditional DDS
The traditional DDS relies on the accumulator to recursively sum the frequency tuning word at the
clockThe
rate,traditional
obtaining DDS relies on the accumulator
the instantaneous to recursively
value of the signal by means sum
of athe frequency
look-up table tuning
[15]. Asword
shownat
the clock rate,
in Figure 2, theobtaining the instantaneous
method produces a time seriesvalue of the signal
of digital words by means
at the outputof aoflook-up table [15].that
the accumulator As
shown in Figure 2, the method produces a time series of digital words
C
increases linearly until the accumulator rolls over at its maximum value of 2 . Hence, the accumulator at the output of the
C
accumulator
output has a fixedthat increases
modulus linearly untilthe
2C . Usually the accumulator
accumulator rolls is
output over at its maximum
truncated valueonly
to P-bits (using of 2the .
C
Hence, the accumulator output has a fixed modulus 2 . Usually the
MSBs) to reduce the size and complexity of the angle-to-amplitude conversion block that immediately accumulator output is
truncated
follows theto P-bits (using
accumulator. only the
This causes MSBs)
the time to ofreduce
series the size
digital words and complexity
produced of the
by the accumulator
angle-to-amplitude conversion block that immediately follows the accumulator.
to appear at the input to the angle-to-amplitude converter as P-bits words ranging in value from This causes the time0
series
P of digital words produced by the accumulator to appear at
P the input
to (2 − 1) [16]. The accumulator output sequence range 0 to (2 − 1) maps to one revolution on the to the angle-to-amplitude
converter
unit circle,asthat
P-bits
is, words ranging
it linearly mapsinbinary
value from
values 0 to ( 2P 01to) [16].
from (2P −The accumulator
1) to radian angles output sequence
from 0 to 2π.
range 0 to ( 2P 
This mapping 1) maps to one
arrangement revolution
allows on the unit circle,
the angle-to-amplitude that is, to
converter it linearly
translatemaps binary
the P-bits values
words to
Y-bits amplitude P values (Y) in a very efficient manner, and finally a low-pass filter is used to obtain a
from 0 to ( 2 1 ) to radian angles from 0 to 2π. This mapping arrangement allows the
desired sinusoidal signal [17].
Electronics 2018, 7, x FOR PEER REVIEW 4 of 14

angle-to-amplitude
Electronics 2018, 7, 330converter to translate the P-bits words to Y-bits amplitude values (Y)
4 ofin
14 a very
efficient manner, and finally a low-pass filter is used to obtain a desired sinusoidal signal [17].

Phase P Bits Angle to Y Bits Fout

FTW Accumulator Amplitude DAC LPF

Fsysclk

Figure 2. Functional block diagram of traditional DDS method.

Figure 2. Functional block diagram of traditional DDS method.
The Y-bits digital amplitude sequence signal output by the converter is converted into an analog
signal by a Y-bit DAC (Digital to Analog Converter, DAC) chip, and finally a low-pass filter is used to
The Y-bits digital amplitude sequence signal output by the converter is converted into an
obtain a desired sinusoidal signal. We see the translation process relied on Equation (1):
analog signal by a Y-bit DAC (Digital to Analog Converter, DAC) chip, and finally a low-pass filter
is used to obtain a desired sinusoidal signal. 2kπ
x =We see
A sin ( the)translation process relied on Equation
(1) (1):
2P
2k
x  A sin(
where: A is the signal amplitude; P is the number ) from the accumulator; k is the binary (1)
of bitsPtaken
2
value of those bits at any given instant; x is the amplitude value corresponding to the address at a
given
where: A istime.
the signal amplitude; P is the number of bits taken from the accumulator; k is the binary
The following Equation expresses the frequency of the sinusoid that appears at the DAC output
value of those bits at any given instant; x is the amplitude value corresponding to the address at a
for a traditional accumulator-based DDS [18]:
given time.
FTW of the sinusoid that appears at the DAC output
The following Equation expresses theF frequency
out = C
Fsysclk (2)
for a traditional accumulator-based DDS [18]: 2
where: Fout is the synthesized frequency; Fsysclk is the sampling frequency; FTW is the frequency
FTW
turning words; FTW < 2C−1 . Fout  C Fsysclk (2)
2
The integer, frequency turning words, is a determining condition for controlling the output
frequency. Since FTW, by definition, is an integer, then Fout is constrained to the following set of
where: Fout is the synthesized frequency; Fsysclk is the sampling frequency; FTW is the frequency
frequencies:
turning words; FTW  2C1 . ( )
2C − 1 Fsysclk


Fsysclk 2Fsysclk 3Fsysclk
The integer, frequencyFout ∈turning
0, words,
, is, a determining
,...... condition for controlling the
(3)output
2C 2C 2C 2C
frequency. Since FTW, by definition, is an integer, then Fout is constrained to the following set of
frequencies:
Inspection of the Equation (3) indicates that the modulus of the DDS accumulator, determines
both the frequency resolution of the DDS and the number of possible output frequencies. It can be
 Fsysclk 2to
seen that the ratio of the outputfrequency
Fout  0, C , C
Fsysclk 2C  1must
3Fsysclk frequency
the sampling
, , 

Fsysclk 
satisfy: 
C C  (3)
 2 2 2 2 
F
out FTW
= C (4)
F that the2 modulus of the DDS accumulator, determines
Inspection of the Equation (3) indicatessysclk
both the frequency resolution of
Because the accumulator bit the DDS
width and the
is fixed, thefrequency
number tuning
of possible output
word cannot befrequencies. It can be
decimal, and the
seen output
that the ratio ofcannot
frequency the output frequency
be arbitrary value.to the for
Now sampling frequencythat
output frequencies must
are satisfy:
integer submultiples
of the sample rate (for example, Fsysclk /10), Fout can be expressed as Fout = Fsysclk /Q (Q is an integer).
Fout FTW
Substituting Fsysclk /Q for Fout in Equation (4) leads to: C (4)
Fsysclk 2
1 FTW
= C (5)
Because the accumulator bit width is fixed,
Q the
2 frequency tuning word cannot be decimal, and
the output frequency cannot be arbitrary value. Now for output frequencies that are integer
Solving for FTW yields FTW = 2C /Q. Because FTW and Q must both be integers, the only values
submultiples of the sample rate (for example, FsysclkK 10 ), Fout can be expressed as Fout  Fsysclk Q (Q
of Q that satisfy Equation (5) can be expressed as 2 , where K is an integer. In practical applications,
is an the
integer).
frequency tuning wordFthat
Substituting Q for the
sysclk controls Foutoutput
in Equation
signal can(4)
beleads to: as:
expressed

1 FTW
 C (5)
Q 2
C
Solving for FTW yields FTW  2 Q . Because FTW and Q must both be integers, the only
values of Q that satisfy Equation (5) can be expressed as 2 K , where K is an integer. In practical
 2C
FTW   2C  K (6)
2K
Electronics 2018, 7, 330 5 of 14
In the specific DDS implementation, it can be divided into two categories:
I. When the Equation (6) is satisfied, the DDS can output an accurate frequency. To
demonstrate, assume that C is 32, Q = 16 = 2C , FTW 2C = C268,435,456, the available frequency turning
−K C
word is an integer, and the address covers range 2fromFTW = K
= 2
0 to 2 . When accumulating a loop, the (6)next
cycle returns
In thetospecific
the initial
DDSvalue and the exact
implementation, frequency
it can be dividedvalue can categories:
into two be output.
II. When the Equation (6) is not satisfied, the frequency tuning word is a decimal number, and
I. When the Equation (6) is satisfied, the DDS can output an accurate frequency. To demonstrate,
the actual
assumeaccumulation
that C is 32, Q =takes
16 = 2an integer.
C , FTW After onethe
= 268,435,456, cycle, the first
available sampling
frequency point
turning wordcannot return to
is an integer,
the initial
and the point, so the
address sampling
covers range frompoints
0 toof2Ceach
. When period are different
accumulating within
a loop, a certain
the next range,to
cycle returns resulting
the
in different waveform
initial value and the amplitudes
exact frequency and unstable
value can bewaveforms.
output. At the same time, there is phase loss
after accumulating
II. When theone cycle, (6)
Equation theiscycle increases,
not satisfied, thethe frequency
frequency tuningdecreases,
word is aand an error
decimal occurs.
number, and For
example, Fsysclk
the actual accumulation
= 100 MH,takesF
an Fout Fsysclkpoint
integer. After one cycle, the first sampling
out = 10 MHz. In this case,
 Fsysclk N return
cannot  1 10 to the
, FTW =
initial point, so the sampling points of each period are different within a certain range, resulting in
429,496,729.6. A traditional accumulator-based DDS, regardless of the capacity of its accumulator, is
different waveform amplitudes and unstable waveforms. At the same time, there is phase loss after
not capable of synthesizing exactly 10 MHz. The closest frequency that a 32-bit accumulator-based
accumulating one cycle, the cycle increases, the frequency decreases, and an error occurs. For example,
DDS Fcan get to 10 MHz with Fsysclk In= this
sysclk = 100 MH, Fout = 10 MHz.
100 case,
MHzFout
is /F
9.99999998603016138 MHz, which is smaller than
sysclk = Fsysclk /N = 1/10, FTW = 429,496,729.6.
A traditional
the expect accumulator-based
value and DDS,
has an absolute regardless
error of the capacity
of 0.01396983862 Hz. of its accumulator,
Such a frequencyiserror
not capable of
is intolerable
synthesizing exactly 10 MHz. The closest frequency
in some special precision equipment or engineering. that a 32-bit accumulator-based DDS can get to
10 MHz with Fsysclk = 100 MHz is 9.99999998603016138 MHz, which is smaller than the expect value
and hasDDS
3. Accurate an absolute
Method error of 0.01396983862
Using CompoundHz. Such a frequency
Frequency Tuning error
Word is intolerable in some special
precision equipment or engineering.
Because the phase accumulator modulus of the traditional DDS is a fixed value, the frequency
3. Accurate
tuning word mustDDSalso
Method
be aUsing Compound
positive integer,Frequency Tuningthe
which causes Word
traditional DDS method to only
synthesize a finite
Because thenumber of precisemodulus
phase accumulator frequency signals.
of the In response
traditional to this
DDS is a fixed problem,
value, this paper
the frequency
proposes
tuning a DDS
word method
must alsousing
be a compound frequency
positive integer, whichtuning
causes word. As visible
the traditional DDSin Figure
method3,tothe phase
only
synthesizerecursively
accumulator a finite number
sumsoftheprecise frequency
frequency signals.
tuning word In component
response to this
X atproblem,
a clock this
rate,paper
and the
proposes a DDS method using compound frequency tuning word. As visible
obtained value is combined with the frequency tuning word components A and B of the auxiliary in Figure 3, the phase
accumulator
accumulator recursively
in the address sums the frequency
generator. In thetuning
DDSword method using Xthe
component at acompound
clock rate, and the obtained
frequency tuning
value is combined with the frequency tuning word components A and B of the auxiliary accumulator in
word, the compound frequency tuning word has three parts: X, A and B. The main working process
the address generator. In the DDS method using the compound frequency tuning word, the compound
of the address generator is as follows: the frequency tuning word X is added with a value A after B
frequency tuning word has three parts: X, A and B. The main working process of the address generator
times of addition, and the subsequent operation is carried out on the basis of the new phase address.
is as follows: the frequency tuning word X is added with a value A after B times of addition, and the
The m-bits addresses
subsequent are is
operation obtained by on
carried out truncating
the basis the obtained
of the new phase address
address.to the
Thelow bit,addresses
m-bits and it is are
sent to
the phase-to-amplitude
obtained by truncating converter to output
the obtained addresstheto Y-bits
the lowamplitude ofsent
bit, and it is the to
address mapping. After the
the phase-to-amplitude
DA chip, the to
converter digital
outputsignal is converted
the Y-bits amplitudeinto
of theanaddress
analogmapping.
signal, and
Afterfinally
the DAthe signal
chip, is filtered
the digital signal and
amplified for output.
is converted into an analog signal, and finally the signal is filtered and amplified for output.

X Phase Address m Bits Angle to Y Bits Fout

Accumulator Generator DAC LPF Amplifier
Amplitude

A Auxiliary
B Accumulator
Fsysclk

Figure
Figure 3. 3. Functionalblock
Functional blockdiagram
diagram of
ofnew
newDDS
DDSmethod.
method.
The Equation for calculating the exact DDS output frequency of the compound frequency
The Equation for calculating the exact DDS output frequency of the compound frequency
tuning word:
tuning word:
Fout M
Fout = M (7)
Fsysclk  N (7)
Fsysclk N
Electronics 2018, 7, 330 6 of 14

where M, N are integers, M < N/2. The frequency ratio of the DDS method using compound frequency
tuning word is very similar to that of the traditional DDS, but N in the DDS of the compound frequency
tuning word is not required to be a power of 2, it can be any integer.
The relationship between the output frequency of the DDS method using compound frequency
tuning word and the sampling frequency is as follows:

Y
Fout M X+ N
= = C
, 0 < N < 2C (8)
Fsysclk N 2

In the Equation (8), the right end is a compound frequency tuning word, X represents an integer
part. After N sampling, the difference between the actual phase and the maximum phase is Y. In the
DDS method using compound frequency tuning word, the processing of the fractional part is mainly
added, so that the output frequency eliminates the error or minimizes the error. When the output
frequency and the system clock are determined, M and N are unique in Equation (7) (M and N are
mutual primes). The X value (integer part) can be obtained by the Equation of the conventional DDS.
Then find the remainder:
 h i
 X = 2C M
N
(9)
 Y = M2C − XN

In Equation (9), X is the frequency tuning word after rounding, the elements of X to the nearest
integers towards zero. After N sampling, the difference between the actual phase and the maximum
phase is the remainder, which will be further simplified:

Y A
= , A < B, B > 0 (10)
N B
In Equation (10), A and B are prime numbers, and both are integers. A and B are processed in the
auxiliary accumulator in the DDS method using compound frequency tuning word.
When M/N approximating M = 1, the corresponding N is a value near the actual number of
sampling or the actual number of sampling when the address is overflowed. Assuming that N 0 is
the actual number of sampling times for an address overflow, then N 0 is equal to the value near
N or N, that is, the number of sampling times N 0 in a cycle completes a summation from 0 to the
maximum address value, and when N 0 samples overflow for the next cycle, all sampling points in each
cycle are coincident, then A is 0, B can be any positive integer, and the compound frequency control
word FTW 0 = { X, 0, B} is obtained. The compound frequency tuning word DDS can accurately
output frequency. At this point, the phase difference between the two adjacent addresses is the phase
represented by the low 16 bits of the accumulator.
If the sampling points of each cycle cannot overlap, DDS cannot accurately output the desired
frequency. At this time:
I. If the simplification Equation (10) satisfies B < N 0 and the B value is a number less than 10,
the compound frequency tuning word is FTW 0 = { X, A, B}, after a period of sampling, the remainder
is divided into uniform B equal parts, it is evenly inserted into the whole sampling process, each time
A value is inserted, so that a period of sampling coverage range of 0 to 2C . All the sampling points
in the next cycle coincide with the first sampling point to ensure that the sampling points in each
cycle are exactly the same, and the DDS can output an accurate frequency. The method of inserting
A and B values is shown in Figure 4. For example, when the system clock = 100 MHz and the
output frequency = 10 MHz, C = 32, in this paper, the frequency tuning word = 429,496,729, Y = 6,
M = 1, N = 10, A = 3 and B = 5, they can be obtained, that is, the compound frequency tuning word
FTW = {429,496,729, 3, 5}. During the same period of sampling, the fourth sampling address is 4X.
The new sampling method is adopted, the fifth sampling address is (5X + 3), and (5X + 3) is the new
and (5X + 3) is the new addressing basis for the accumulation; The ninth sampling address is (9X +
3), the tenth sampling address is (10X + 6), that is the maximum value of the phase address, so that
the sampling points in a cycle cover 0 to 2C , can ensure that the next cycle to take the same sampling
points. Electronics 2018, 7, 330 7 of 14

II. If the simplification Equation (10) does not satisfy B  N  , then the Equation (9) is
addressing
approximately basis for
reduced tothe accumulation;
B less than 10 The
andninth sampling
a value of A address is (9X +At
is obtained. 3),this
the tenth
time,sampling
the compound
address is (10X + 6), that is the maximum value of the phase address, so that the sampling points in a
frequency tuning word is FTW    X , A, B , which ensures that the DDS synthesis frequency is
cycle cover 0 to 2C , can ensure that the next cycle to take the same sampling points.
closer to theII.expected
If the simplification
value. ForEquation (10)when
example, does not
the satisfy < N0, F
systemB clock then the Equation (9) is
sysclk = 100 MHz, the output
approximately reduced to B less than 10 and a value of A is obtained. At this time, the compound
frequency is required
frequency tuning be FisoutFTW
toword = 1.024 MHz,
0 = { X, A, B}the frequency
, which ensures tuning
that the word = 43,980,465
DDS synthesis can is
frequency be found.
closerY toNthe
We can get expected
 347 3125value. For example,
, and the constraintwhencanthe
besystem
used to clock Fsysclk
meet the= requirements
100 MHz, the output
of A B 1 9 .
frequency is required to be Fout = 1.024 MHz, the frequency tuning word = 43,980,465 can be found.
Finding Wethecan
compound
get Y/N =frequency
347/3125, andtuning word is
the constraint
FTW  {43,980,465,
can be used= to 1, 9}, weofcan
meet the requirements A/B get a relatively
= 1/9.
high precision.
Finding theIn compound
the two cases mentioned
frequency tuning wordabove,
is FTWWhen
0 the address
= {43,980,465, 1, 9}, weis only
can get aX-accumulating,
relatively high the
phase difference
precision. Inbetween the two
the two cases adjacent
mentioned sampling
above, When thepoints
addressisisthe
onlyphase represented
X-accumulating, by the lower
the phase
difference between the two adjacent sampling points is the phase represented
16-bits in the accumulator. When the sample address is (X + A), the phase difference between by the lower 16-bits in the two
the accumulator. When the sample address is (X + A), the phase difference between the two adjacent
adjacent sampling points is 16 bits plus A.
sampling points is 16 bits plus A.

Φ
(10X+6)
(10X+3)
(9X+3)

(5X+3)
5X
4X

0 n

Figure 4. Address sampling method of the new DDS method. Address sampling model of the new
Figure 4.DDS
Address sampling method of the new DDS method. Address sampling model of the new
method for outputting 10 MHz signal in 100 MHz reference clock.
DDS method for outputting 10 MHz signal in 100 MHz reference clock.
The main difference between the two methods is the different ways to generate addresses.
The address of traditional DDS relies on the accumulator to recursively sum the frequency tuning
The main difference between the two methods is the different ways to generate addresses. The
word at the clock rate; The DDS method using compound frequency tuning word is under the control
address of traditional
of the DDSWhen
reference clock. reliestheonfrequency
the accumulator
control wordtoX recursively sum
is accumulated, eachthe
timefrequency tuning word
B is accumulated,
at the clock
an Arate;
valueThe DDSto method
is added the address using
to getcompound
an adjustablefrequency
address. tuning word is under the control of
the reference clock. When the frequency control word X is accumulated, each time B is accumulated,
4. Development of DDS Frequency Synthesizer Based on FPGA
an A value is added to the address to get an adjustable address.
In order to verify the validity of the DDS method using compound frequency tuning word,
this paper
4. Development of designs
DDSand implements
Frequency an FPGA based
Synthesizer Basedfrequency
on FPGA synthesizer. Thanks to the flexible
programmability of FPGA, the traditional DDS method and the DDS method proposed by this
In order
paper to verify
using the validity
compound of tuning
frequency the DDS wordmethod using compound
can be repeatedly frequency
erased on the platform totuning word, this
facilitate
comparison experiments. The frame structure of frequency synthesizer
paper designs and implements an FPGA based frequency synthesizer. Thanks to the flexible based on FPGA is shown in the
Figure 5, which specifically consists of the reference clock module, the FPGA module, the DA module,
programmability of FPGA, the traditional DDS method and the DDS method proposed by this paper
the filter module and the amplification driver module. The Modules of DDS frequency synthesizer
using compound
based on FPGA frequency
is showntuning
as Figureword
6 (Thecan
size be repeatedly
of the circuit board erased on62the
is 142 × mm).platform to facilitate
The reference
comparison
clockexperiments.
module uses SRS’sTherubidium
frame structure
atomic clock of PRS10,
frequency
whosesynthesizer based
sine wave output hason FPGA is ofshown in
a frequency
− 12
1.52 × 10 clock
the Figure 5, which
10 MHz, specifically
the amplitude is 0.7 consists of theofreference
V, and a stability /s (asmodule,
shown in the FPGA
Figure 7). Themodule,
10 MHz the DA
output signal of rubidium atomic clock is processed by frequency
module, the filter module and the amplification driver module. The Modules of DDS division module in FPGA to obtainfrequency
100 MHz clock signal as sampling clock of frequency synthesizer. The FPGA module adopts Altera’s
synthesizer based on FPGA is shown as Figure 6 (The size of the circuit board is 142 × 62 mm). The
reference clock module uses SRS’s rubidium atomic clock PRS10, whose sine wave output has a
frequency of 10 MHz, the amplitude is 0.7 V, and a stability of 1.52 × 10−12/s (as shown in Figure 7).
The 10 MHz output signal of rubidium atomic clock is processed by frequency division module in
FPGA to obtain 100 MHz clock signal as sampling clock of frequency synthesizer. The FPGA module
 Electronics 2018, 7, x FOR PEER REVIEW 8 of 14
ElectronicsElectronics
2018, 7, 2018,
x FOR PEER REVIEW
7, 330 8 of 14 8 of 14

accumulator, address generator and phase-to-amplitude converter are designed and implemented in
accumulator, address generator and phase-to-amplitude converter are designed and implemented in
EP1C12Q240I7.
EP1C12Q240I7. TheAllDAofmodule useslogic
the digital Maxim’s
circuits16-bit
such parallel
as phaseinput DAC chip
accumulator, (MAX5885)
auxiliary to convert
accumulator,
EP1C12Q240I7.
address The DA
generator andmodule uses Maxim’s
phase-to-amplitude 16-bit
converter areparallel
designed input
and DAC
implemented
the digital waveform output from the EP1C12Q240I7 into an analog waveform output. The filter
chip in(MAX5885)
EP1C12Q240I7. to convert
the module
digital
The iswaveform
DAdesigned output
moduletouses from
filterMaxim’s
out theand
16-bit
clutter EP1C12Q240I7
parallel input DAC
other interfering into
chipan(MAX5885)
signals analog
in waveform
to convert
the output waveform output.
the the The
digital
of DACfilter
module is designed
waveform
module. a to
It usesoutput filter
fromout
seventh-order the clutter
ellipticand
EP1C12Q240I7 other
filter into
to interfering
an analog
improve signalsof
the waveform
quality inoutput.
thesynthesized
the output waveform
The filter module of
waveform. is the
TheDAC
module. designed
It uses to filter out
a seventh-order clutter and other
ellipticandinterfering
filter signals
to improvebythein the output waveform of the DAC module.
amplifier driver module is designed implemented TI’squality of the
ultra-low synthesized
noise waveform. The
integrated operational
It uses a seventh-order elliptic filter to improve the quality of the synthesized waveform. The amplifier
amplifier driver
amplifier module
OPA847, which is makes
designed the and
device implemented by TI’scapability,
has a large driving ultra-lowand noise integrated
the output operational
synthesized
driver module is designed and implemented by TI’s ultra-low noise integrated operational amplifier
frequency
amplifier signal
OPA847,
OPA847, whichhas
whichan amplitude
makesmakes of
thehas
the device not less
device than
a largehas 3 Vpp
a large
driving under
driving
capability, a load of 50
andcapability, Ω. and the output
the output synthesized synthesized
frequency
frequency signal
signal hasamplitude
has an an amplitude of not
of not less thanless than
3 Vpp 3 Vpp
under under
a load of 50aΩ.
load of 50 Ω.
100MHz Fout
Reference FPGA DA Filter Amplifier
100MHz
Clock Fout
Reference FPGA DA Filter Amplifier
ClockFigure 5. Block diagram of DDS frequency synthesizer based on FPGA.

Figure
Figure 5. Block
5. Block diagramofofDDS
diagram DDS frequency
frequency synthesizer basedbased
synthesizer on FPGA.
on FPGA.

(a)

(a)

(b)

Figure
Figure 6. Modules
6. Modules of of
DDSDDS frequencysynthesizer
frequency synthesizer based
based on
onFPGA.
FPGA.(a)(a)
Standard frequency
Standard source
frequency source
rubidium
rubidium atomic
atomic clock
clock PRS10;
PRS10; (b)(b)FPGA
FPGAimplementation
implementation platform ofof
platform DDS.
DDS.

(b)

Figure 6. Modules of DDS frequency synthesizer based on FPGA. (a) Standard frequency source
rubidium atomic clock PRS10; (b) FPGA implementation platform of DDS.
 Electronics 2018, 7, 330 9 of 14
Electronics 2018, 7, x FOR PEER REVIEW 9 of 14

10MHz
-11
10

-12
10
Allan Deviation

-13
10

-14
10 0 1 2 3 4
10 10 10 10 10
Averaging Time (s)

Figure7.
Figure Stability of
7. Stability ofrubidium
rubidiumatomic clock
atomic PRS10.
clock PRS10.
5. Experimental Results and Analysis
5. Experimental Results and Analysis
In the fields of power electronics and frequency standards, there are special requirements for
In the
the fields synthesizer
frequency of power electronics and frequency
output frequency. standards,
For example, in orderthere are special
to meet the needsrequirements
of battery for
the monitoring
frequency synthesizer
and management output frequency.
of electric For Kadirvel
vehicles, example,K.inetorder to meetanthe
al. proposed IC needs of battery
chip, whose
monitoring
maximum and management
recommended clockofdrive
electric
valuevehicles, Kadirvel
is just 2.048 MHz [19].K. In
et order
al. proposed
to reduce thean influence
IC chip, ofwhose
the Dick effect, Wang et al. selected a 5 MHz signal with ultra-low phase noise as
maximum recommended clock drive value is just 2.048 MHz [19]. In order to reduce the influence of a reference of their
microwave
the Dick effect,generator
Wang etinal.the study ofa the
selected influence
5 MHz signalof with
Dick effect in cold
ultra-low atomic
phase clockasinaan
noise integrating
reference of their
sphere [20].
microwave generator in the study of the influence of Dick effect in cold atomic clock in an
But in practical engineering applications, a traditional DDS cannot accurately synthesize a
integrating sphere [20].
standard frequency signal. Suppose that the phase accumulator of the traditional DDS is 32 bits,
But in practical engineering applications, a traditional DDS cannot accurately synthesize a
the closest output frequency and its error when synthesizing special frequency points such as
standard frequency
1.024 MHz, signal.
2.048 MHz Suppose
5 MHz, and 10that
MHztheare
phase
shownaccumulator
in Table 1. of the traditional DDS is 32 bits, the
closest output frequency and its error when synthesizing special frequency points such as 1.024
MHz, 2.048 MHz 5 MHz,
Table 1.and 10 MHz
Output areofshown
capability in Table
traditional DDS in1.special frequency points.

Special Frequency
Table
Points Example (MHz) 1.Frequency
OutputTuning Word ofTheoretical
capability traditionalValue
DDSof Output Frequency
in special (MHz) points.
frequency Frequency Error (Hz)

Special 1.024
Frequency 43,980,465 1.023999997414648523 0.00258535146
2.048 Frequency Tuning Word
87,960,930 Theoretical2.047999994829297065
Value of Output Frequency (MHz) Frequency Error (Hz)
0.00517070293
Points Example (MHz)
5 214,748,364 4.999999981373548548 0.01864645149
1.024
10 43,980,465
429,496,729 1.023999997414648523
9.999999986030161380 0.00258535146
0.01396983861
2.048 87,960,930 2.047999994829297065 0.00517070293
5 214,748,364 4.999999981373548548 0.01864645149
10
As shown 429,496,729
in the third column 9.999999986030161380
of Table 1, the frequency 0.01396983861
values represent the theoretical outputs of
traditional DDS. In order to test the real performance of traditional DDS and the output stability and
As shown
accuracy in the
of the newthird
DDS column of Table in
method proposed 1, this
the frequency values represent
paper, we designed the theoretical
an experimental outputs
platform just
of traditional
as Figure 8 DDS.
shown. In order to test the real performance of traditional DDS and the output stability
The platform
and accuracy of themainly
new includes
DDS methodreference clock PRS10,
proposed distribution
in this paper,amplifier HP5087A,
we designed an the FPGA
experimental
implementation platform
platform just as Figure 8 shown. of DDS, Keysight 53220A counter, TimeLab test software and Stable32 test
software.
The platform mainly includes reference clock PRS10, distribution amplifier HP5087A, the isFPGA
The photograph of the real experimental platform is shown as Figure 8b. After the system
powered on for about 9 min, the frequency-locked circuit indicates that the rubidium clock outputs
implementation platform of DDS, Keysight 53220A counter, TimeLab test software and Stable32 test
stable reference signal and can start the follow-up operation. The standard frequency source of the
software. The photograph of the real experimental platform is shown as Figure 8b. After the system
rubidium atomic clock is sent through a distribution amplifier to get two signals, one of which is input
is powered on for about 9 min, the frequency-locked circuit indicates that the rubidium clock
to the FPGA implementation platform of DDS as its standard frequency source. The other is input to
outputs stable reference
the counter signal
as its standard and cansource.
frequency start the
Thefollow-up operation.
device under test andThe standard
measuring frequency
equipment source
with
of the rubidium
common atomic
standard clock issource
frequency sent through a distribution
can ensure the credibilityamplifier to get two results.
of the measurement signals, one of which
is input to the FPGA implementation platform of DDS as its standard frequency source. The other is
input to the counter as its standard frequency source. The device under test and measuring
equipment with common standard frequency source can ensure the credibility of the measurement
results.
Electronics
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Standard FPGA
Standard
Frequency FPGA
Implementation Analysis
10MHz Implementation
Platform of DDS Analysis
Software
Frequency
Source
Source
Rubidium 10MHz Distribution 10MHz Platform of DDS Software 1.28
TimeLabV
Rubidium 10MHz Distribution
Amplifier 10MHz TimeLabV 1.28
and Analysis
Atomic Amplifier 10MHz
HP5087A
Atomic
Clock HP5087A Universal and Software
Analysis
Clock Universal
Frequency Counter Software V1.5
Stable32
PRS10 Frequency Counter Frequency Stable32 V1.5
PRS10 Keysight53220A Frequency
Difference
Keysight53220A Difference
(a)
(a)

(b)
(b)

Figure 8. Experimental
Figure 8.
8. Experimental platform
platform for
platform testing
for testing
testingthe
thecharacteristics
characteristicsofofthe
theDDS.
DDS. Block
(a)(a) diagram
Block
Block diagram
diagram thethe
of
of the
experimental platform; (b) Photograph
experimental platform; (b) Photograph of
Photographofofthethe experimental
theexperimental platform.
experimentalplatform.
platform.

Then, the
Then, the DDS
DDS
DDS method
method using
method using the
using the compound
compoundfrequency
compound frequencytuning
tuningword
wordis is
used
used to to
synthesize
synthesize
synthesize thethe
frequencypoints
frequency points ofof 1.024
1.024 MHz,
MHz, 2.048
2.048 MHz,
MHz,55MHz MHzand and1010MHz.
MHz.After
Afternearly
nearly 1111h of measurement,
h of measurement,
its characteristics are analyzed. According
its characteristics are analyzed. According
According to to the test data, Stable32 is used to
to the test data, Stable32 is used to analyzeanalyze thethe
stability
stability
index of our new method. At the same time, experiments in Figure 9 show that the DDS using
index
index of
ofour
our new
new method.
method. At the
At same
the sametime, experiments
time, experiments in Figure
in 9 show
Figure 9 that
show the
thatDDS
the method
DDS method
method
compound
usingcompound frequency
compound tuning tuning
frequency word has better stability. The stability test resultstest
forresults
different frequency
using frequency tuning word
word has
has better
betterstability.
stability.The
Thestability
stability test resultsforfor
different
different
points show
frequency that the
points shownew DDS
that themethod proposed inproposed
this paper has a paper
good stability index (shortindex
term
frequency points show that the new
new DDS
DDS method
method
− 12
proposedininthisthis paperhashas a good
a good stability
stability index
stability
(short termas an example,
stability better
as an than 8.0
example, × 10than/s).
better 8.0 × 10 /s).
−12
(short term stability as an example, better than 8.0 × 10−12/s).
-10 1.024MHz
10 1.024MHz
-10
10

New DDS Method

New DDS Method
-11 Traditional DDS Method
10
Deviation

-11 Traditional DDS Method

10
Deviation
Allan
Allan

-12
10
-12
10

-13
10 0 1 2 3 4
10 10 10 10 10
-13
10 0 1 Averaging Time
2 (s) 3 4
10 10 10 10 10
Averaging Time (s)
(a)
(a)

Figure 9. Cont.
Electronics 2018,7,7,330
Electronics2018, x FOR PEER REVIEW 11 of11
14of 14

2.048MHz
-10
10

New DDS Method

-11
10
Traditional DDS Method

Allan Deviation
-12
10

-13
10

-14
10 0 1 2 3 4
10 10 10 10 10
Averaging Time (s)

(b)
5MHz
-11
10

New DDS Method

-12 Traditional DDS Method

10
Allan Deviation

-13
10

-14
10 0 1 2 3 4
10 10 10 10 10
Averaging Time (s)

(c)
10MHz
-11
10

New DDS Method

-12 Traditional DDS Method

10
Allan Deviation

-13
10

-14
10 0 1 2 3 4
10 10 10 10 10
Averaging Time (s)

(d)

Figure 9.
Figure 9. Stability
Stabilityof
ofdifferent
differentfrequency
frequencypoints.
points.
(a)(a) Stability
Stability of of 1.024
1.024 MHz;
MHz; (b)(b) Stability
Stability of 2.048
of 2.048 MHz;
MHz;
(c) Stability
(c) Stabilityofof55MHz;
MHz;(d)(d)Stability
Stabilityofof
1010 MHz.
MHz.

By
By using
using the
thesame
sameexperiment
experimentplatform
platformshown
shownininFigure 7, 7,
Figure thethe
accuracy
accuracyindexes of the
indexes DDSDDS
of the
method using compound frequency tuning word and the traditional DDS frequency
method using compound frequency tuning word and the traditional DDS frequency synthesis synthesis method
are obtained
method and compared.
are obtained The experiment
and compared. results are shown
The experiment resultsinare
Figure
shown10, in
theFigure
abscissa
10,represents
the abscissa
the average time of measurement and the ordinate represents the relative
represents the average time of measurement and the ordinate represents the relative frequency difference.
frequency
The experimental results show that the relative frequency deviation of the synthesized frequency is
difference. The −experimental results show that the relative frequency deviation of the synthesized
about 4.80 × 10 12 , which is three orders of magnitude lower than the traditional DDS frequency
frequency is about 4.80 × 10−12, which is three orders of magnitude lower than the traditional DDS
synthesis method (the relative frequency deviation is about 2.00 × 10−9 ). It can be proved that the DDS
frequency synthesis method (the relative frequency deviation is about 2.00 × 10−9). It can be proved
using compound frequency tuning word has higher frequency output accuracy than the traditional
that the DDS using compound frequency tuning word has higher frequency output accuracy than
DDS method.
the traditional DDS method.
 Electronics 2018, 7, 330 12 of 14
Electronics 2018, 7, x FOR PEER REVIEW 12 of 14

(a)

(b)

(c)

Figure 10. Cont.

Electronics 2018, 7, x FOR PEER REVIEW 13 of 14
Electronics 2018, 7, 330 13 of 14

(d)

Figure
Figure 10. Measurement
Measurement ofof accuracy.
accuracy. (a) 1.024 MHz
MHz signal
signal accuracy;
accuracy; (b)
(b) 2.048
2.048 MHz
MHz signal
signal accuracy;
accuracy;
(c)
(c) 5 MHz signal accuracy; (d) 10 MHz signal accuracy.
accuracy.

6. Conclusions
6. Conclusions
This paper
This paper proposed
proposed aaprecise
preciseDDSDDSmethod
methodusing usingthe compound
the compound frequency
frequency tuning
tuning wordwordandandthe
implementation scheme of FPGA. In this method, the compound frequency
the implementation scheme of FPGA. In this method, the compound frequency tuning word is tuning word is flexible and
changeful,
flexible andwhich overcomes
changeful, whichseveral defects of
overcomes typicaldefects
several DDS, such as the phase
of typical DDS,accumulator
such as the modulus
phase
is fixed value, the frequency tuning word must be positive integer,
accumulator modulus is fixed value, the frequency tuning word must be positive integer, andand synthesizing only a limited
number of accurate
synthesizing only asignals.
limitedThen the proposed
number of accurate DDSsignals.
methodThen of compound
the proposed frequencyDDStuning
method wordof
is realized by using FPGA. By adding an auxiliary accumulator and an
compound frequency tuning word is realized by using FPGA. By adding an auxiliary accumulator address generator to process
the relevant
and an address data, the method
generator of accumulating
to process the relevantphase address
data, the methodin synthetic frequency
of accumulating phaseis adjusted
address in to
improve the quality of synthetic frequency signal. Taking advantage of
synthetic frequency is adjusted to improve the quality of synthetic frequency signal. Takingthe flexibility of FPGA in digital
circuit design
advantage andflexibility
of the the advantages
of FPGA ofinparallel
digitalcomputing
circuit designarchitecture design, theof
and the advantages new method
parallel and the
computing
traditional method can be implemented alternately on the FPGA platform
architecture design, the new method and the traditional method can be implemented alternately on the to facilitate comparison
experiments.
FPGA platformThe experimental
to facilitate measurement
comparison andThe
experiments. analysis of the experimental
experimental measurementdata and show
analysisthatof the
the
proposed DDS method using compound frequency tuning word has higher
experimental data show that the proposed DDS method using compound frequency tuning word has accuracy of the synthesis
frequency
higher under
accuracy of the premise of
the synthesis ensuring
frequency the stability
under the premise index. The related
of ensuring methods
the stability index.and technical
The related
schemes proposed in this paper are expected to provide references
methods and technical schemes proposed in this paper are expected to provide references for for high-precision frequency
synthesizer orfrequency
high-precision signal generator engineering.
synthesizer or signal generator engineering.
The accuracy of the frequency
The accuracy of the frequency signal signal isis always
always an an important
important target
target inin the
the field
field ofof frequency
frequency
standard comparison.
standard comparison.Researchers
Researchershave havebeen
beenlooking
looking forfor various
various methods
methods to to improve
improve thethe quality
quality of
the synthesized signal. The most direct way to improve the signal quality is to increase the bit the
of the synthesized signal. The most direct way to improve the signal quality is to increase widthbit
width
and and improve
improve the resolution
the resolution of the accumulator,
of the accumulator, but thisbut this method
method requires
requires the chip thetochip
have to ahave
largea
large memory space. With the same memory space of ROM, a new
memory space. With the same memory space of ROM, a new algorithm can be designed to improve algorithm can be designed to
improve the amplitude quantization to improve the accuracy of synthetic
the amplitude quantization to improve the accuracy of synthetic signals. At the same time, the signals. At the same time,
the influence
influence of noise
of noise on on signal
signal synthesis
synthesis is also
is also great.We
great. Weshould
shouldsynthesize
synthesizethe theprevious
previous frequency
frequency
synthesis methods. A new method of frequency synthesis and some noise
synthesis methods. A new method of frequency synthesis and some noise reduction algorithms are reduction algorithms are
designed to improve the quality of frequency synthesis. These are also the
designed to improve the quality of frequency synthesis. These are also the focus of our work in the focus of our work in the
future. We
future. We hope
hope to to make
make breakthroughs
breakthroughs as as soon
soon as as possible.
possible.
Author Contributions: All of the authors were working together very tightly. The theoretical works on the design
Author Contributions: All of the authors were working together very tightly. The theoretical works on the
of the DDS using compound frequency tuning word were mainly driven by S.T. and Y.H. The transformation of the
design of theinto
DDS method DDS using compound
FPGA-synthesizer wasfrequency tuning
done by C.L. C.L. word were
was also mainly for
responsible driven by S.T.the
performing and Y.H. The
experiments.
transformation of the DDS
S.T. and C.L. analyzed method intoresults
the experimental FPGA-synthesizer
and wrote thewas done
paper by C.L. C.L. was also responsible for
together.
performing
Funding: ThetheProject
experiments. S.T.by
supported and C.L. analyzed
Natural Science the experimental
Basic results
Research Plan and wrote
in Shaanxi the paper
Province together.
of China (Program
NO. 2018JM1025),
Funding: the service
The Project local special
supported plan project
by Natural Scienceof Basic
Shaanxi Education
Research Department
Plan (Program
in Shaanxi NO.of17JF027)
Province China
and the National Natural Science Foundation of China (Program NO. 11403018).
(Program NO. 2018JM1025), the service local special plan project of Shaanxi Education Department (Program
NO. 17JF027) and the National Natural Science Foundation of China (Program NO. 11403018).
Electronics 2018, 7, 330 14 of 14

Conflicts of Interest: The authors declare no conflict of interest.

References
1. Abdelfattah, O.; Gal, G.; Roberts, G.W.; Shih, I.; Shih, Y.C. A top–down design methodology encompassing
components variations due to wide-range operation in frequency synthesizer PLLS. IEEE Trans. Very Large
Scale Integr. Syst. 2016, 24, 2050–2061. [CrossRef]
2. Qiu, Y.; Zhao, L.; Zhang, F. Design of 0.35-ps RMS Jitter 4.4–5.6-GHz Frequency Synthesizer with Adaptive
Frequency Calibration Using 55-nm CMOS Technology. Circuits Syst. Signal Process. 2018, 37, 1479–1504. [CrossRef]
3. Zhang, Y.; Wang, H. Design of a System to Generate a Four Quadrant Signal at High-Frequency. Intell. Autom.
Soft Comput. 2017, 24. [CrossRef]
4. Taheri, H.E.; Ehsanian, M. A new adaptive bandwidth, adaptive jitter frequency synthesizer using
programmable charge pump circuit. Anal. Integr. Circuits Signal Process. 2018, 96, 373–384. [CrossRef]
5. Guo, S.; Gui, P.; Liu, T.; Zhang, T.; Xi, T.; Wu, G.; Fan, Y.; Morgan, M. A Low-Voltage Low-Phase-Noise
25-GHz Two-Tank Transformer-Feedback VCO. IEEE Trans. Circuits Syst. I Regul. Pap. 2018, 99. [CrossRef]
6. Rust, J.; Bärthel, M.; Paul, S. On high-accuracy direct digital frequency synthesis using linear function
approximation. In Proceedings of the 2016 24th European Signal Processing Conference (EUSIPCO),
Budapest, Hungary, 29 August–2 September 2016; pp. 672–676.
7. Du, Y.; Li, W.; Ge, Y.; Li, H.; Deng, K. Note: A high-frequency signal generator based on direct digital
synthesizer and field-programmable gate array. Rev. Sci. Instrum. 2017, 88, 096103. [CrossRef] [PubMed]
8. Delorme, N.; Blanc, C.L.; Dezzani, A.; Bély, M.; Ferret, A.; Laminette, S. A NEMS-Array Control IC for
Subattogram Mass Sensing Applications in 28 nm CMOS Technology. IEEE J. Solid-State Circuits 2015,
1, 249–258.
9. Leitner, S.; Wang, H.; Tragoudas, S. Design Techniques for Direct Digital Synthesis Circuits with Improved
Frequency Accuracy Over Wide Frequency Ranges. J. Circuits Syst. Comput. 2017, 26, 1750035. [CrossRef]
10. He, J.; Jiang, J.; Li, N. Design of DDS Signal Generator Based on FPGA. Comput. Meas. Control 2017, 2, 063.
11. Sotiriadis, P.P. Single-Bit All-Digital Frequency Synthesis Using Homodyne Sigma-Delta Modulation.
IEEE Trans. Ultrason. Ferroelectr. Freq. Control 2017, 64, 463–474. [CrossRef] [PubMed]
12. Kwiatkowski, P.; Różyc, K.; Sawicki, M.; Jachna, Z.; Szplet, R. 5 ps jitter programmable time
interval/frequency generator. Metrol. Meas. Syst. 2017, 1, 57–68. [CrossRef]
13. Hu, P.F.; Shen, L.; Han, F.; Yang, F.; Song, M.J.; Zhang, L. Development of the data acquisition system for
terahertz spectrometer. Trans. Inst. Meas. Control 2018, 3, 805–811. [CrossRef]
14. Khare, A.; Arora, R.; Banik, A.; Banik, A.; Mehta, S.D. Autonomous Rubidium Clock Weak Frequency Jump
Detector for Onboard Navigation Satellite System. IEEE Trans. Ultrason. Ferroelectr. Freq. Control 2016, 63,
326–335. [CrossRef] [PubMed]
15. Madheswaran, M. An Improved Direct Digital Synthesizer Using Hybrid Wave Pipelining and CORDIC
algorithm for Software Defined Radio. Circuits Syst. Signal Process. 2013, 3, 1219–1238. [CrossRef]
16. Huang, J.M.; Chen, Z.; Guo, H.; Han, K. FPGA Implementation of a Novel Type DDS Based on CORDIC
Algorithm. Adv. Intell. Soft Comput. 2011, 105, 183–188.
17. Ryabov, I.V.; Tolmachev, S.V.; Chernov, D.A. A direct digital synthesizer of compound wideband signals.
Instrum. Exp. Tech. 2014, 57, 420–425. [CrossRef]
18. Guo, X.; Wu, D.; Zhou, L.; Wu, J. A 2-GHz 32-bit ROM-based direct-digital frequency synthesizer in 0.13 µm
CMOS. Analog. Integr. Circuits Signal Process. 2018, 94, 127–138. [CrossRef]
19. Kadirvel, K.; Carpenter, J.; Huynh, P.; Ross, J.M. A stackable, 6-cell, Li-ion, battery management IC for
electric vehicles with 13, 12-bit Σ∆ ADCs, cell balancing, and direct-connect current-mode communications.
IEEE J. Solid-State Circuits 2014, 49, 928–934. [CrossRef]
20. Wang, X.M.; Meng, Y.L.; Wang, Y.N.; Wan, J.Y.; Yu, M.Y. Dick Effect in the Integrating Sphere Cold Atom
Clock. Chin. Phys. Lett. 2017, 34, 063702. [CrossRef]

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