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1.0 The Design of Datapath

Decoder 

The register file requires a 2‐line to 4‐line decoder with HI‐true outputs and one HI‐true
enable input as shown in the circuit.

Multiplexer

The register file also requires a  multiplexer.  A mux has 8-bit data inputs, 8-bit data output

and select line.

Register

The four registers R0, R1, R2 and R3 in the diagram below are to be implemented using the
VHDL code. Each register comprises 4 positive edge‐triggered D flipflops. The clock input
to all flipflops in the register is defined as Clk. Then we will design the register file using the
by connecting the multiplexer, decoder and four registers as shown below.

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Datapath

The register file forms the basis of a "datapath" which is a fundamental building block of a
computer. Data is selected from any register then stored back into any other register in the
register file, all in a single clock cycle ( a lo‐hi‐lo pulse applied to the load enable LE input).
A Quad 2:1 MUX included as shown below allows external data to be inserted into the
datapath. Data can thus be transferred between any two registers of our register file or any
register can be loaded with external data. This datapath can execute the following operations:

(a) any register can be loaded with external data from switches Rd ← data (4‐bits)

(where d=0,1,2 or 3)

(b) any register can be loaded with the data contained in any one of the other registers,

including itself (register‐to‐register transfer) Rd ← Rs (where d, s = 0, 1, 2 or 3)

The implementation is shown below. The inputs [ D1, D0, S1, S0, DS ] form a 5‐bit
"control" word which specifies the source (S1, S0) and destination (D1, D0) registers of the
register file and an operation (DS) that is to take place. For DS=0, external data from
switches is loaded into the destination register; for DS=1, data is transferred from the source
register to the destination register. Once the control word and data input (if appropriate) are
set on the level switches, execution is achieved by applying a load enable (LE) input to the
register file. This LE input may be considered as the clock to the entire system.

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ALU

An ALU is a combinational logic circuit that performs various arithmetic and logic operations
on n-bit data (operands). The number of bits on the "function select" input determines how
many operations may be performed on the operands.

Modifying the Register File

To be able to include an ALU in our datapath, we must first modify our register file design so
that it has the capability to select two registers as outputs (Source Register A and Source
Register B). This will allow the contents of any two registers to be applied to the A and B
inputs of the ALU. This is easily achieved by adding a second Quad 4:1 MUX to the design of
the register file as shown below:

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The inputs to this register file are now:

Destination register select (2 bits), source register A select (2 bits), source register B select (2
bits) and load enable (1 bit). The outputs are Data Out A and Data Out B (each 4 bits) as
shown above. 

Datapath with ALU

Now, the datapath design can be extended by including the ALU and the register file as
shown in the next figure:

The inputs [ D1, D0, SA1, SA0, SB1, SB0, s2, s1, s0, DS ] comprise a 10‐bit control word
which specifies a destination register (D1, D0) , the two source registers (SA1, SA0) and
(SB1, SB0), and the ALU function (s2, s1, s0) that operates on the source registers. The DS
input allows loading of the registers with external data via the Quad 2:1 MUX. For DS=0,
external data from switches is loaded into the destination register; for DS=1, data is
transferred from the ALU output to the destination register. Once the control word and data
input are set on the level switches, execution is achieved by applying a load enable (LE) input
(pulse lo‐hi‐lo) to the register file. This LE input may be considered as the clock to the entire
system. You can view the results of each operation using four LEDs connected to the output
of the ALU as shown. The function that is executed in response to a control word and a LE
clock input is called a microoperation. A series of microoperations applied to a datapath is
called a microprogram.

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2.0 Implemention using VHDL

2.1 Objective

 To gain insight into the internal logic for data movement between registers in a
computer
 To introduce the concept of a control word for implementing an elementary set of
micro‐operations.
 To gain experience with the use of VHDL constructs
 To gain experience with incremental, modular design

2.2 Design approach

A quad 2-to-1 multiplexer is attached to each of the two address inputs to the register file, to
select between an address from the microcontroller and an address from the instruction.

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There is a 5-bit signal in the microcontroller for the combined destination and source address
DSA, in addition another 5-bit signal for the B address SB. The first bit of each of these fields
selects the register file address source. If the first bit is 0 it selects the microcontroller(MC),
else it selects the instruction(IR). If an instruction is selected, whether it is DST or SRC is
determined by an additional quad 2-to-1 multiplexer. This 1 multiplexer is controlled by the
second bit of the DSA or SB field, depending on which of them has 1 as the first bit. Only one
of the signals DSA and SB is allowed to have a 1 in the first bit, thereby ensuring that the
proper second bit is used to determine the register address. A 0 is appended to the left of the
3-bit fields DST and SRC to cause them to address R0 through R7. In addition to the first bit,
which selects the address source, the addresses from the microcontroller contain four bits so
that all 16 registers can be reached. The final change to the register is to replace the storage
elements for R0 in the file with open circuits on the lines that were their inputs and with
constant zero values on the lines that were their outputs.

The block diagram and symbol for a 16x16 Register file is showing in figure below:

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For the function unit, we can use the ALU and shift register designs you created before. The
block diagram of a function unit is showing below:

Datapath block diagram shown below:

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2.3 VHDL Source Codes

2.3.1 : 2 to 1 Mux VHDL source codes

-- 2 to 1 mux

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--use IEEE.STD_LOGIC_ARITH.ALL;

--use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux2 is port (

s: in std_logic; ---- select line

d1, d0: in std_logic_vector(7 downto 0); ---- data bus input

y: out std_logic_vector (7 downto 0)); ---- data bus output

end mux2;

architecture behavioral of mux2 is

begin

process(s, d1, d0)

begin

if (s='0') then

y <= d0;

else

y <= d1;

end if;

end process;

end behavioral;

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2.3.2 : Register File VHDL source codes

-- register file

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

--use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity regfile is port (

clk: in std_logic; ---clock

we: in std_logic; ---write enable

wa: in std_logic_vector(1 downto 0); ---write address

input: in std_logic_vector(7 downto 0); ---input

rae: in std_logic; ---read enable port A

raa: in std_logic_vector(1 downto 0); ---read address port A

rbe: in std_logic; ---read enable port B

rba: in std_logic_vector(1 downto 0); ---read address port B

aout, bout: out std_logic_vector(7 downto 0)); ---output port A & B

end regfile;

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architecture behavioral of regfile is

subtype reg is std_logic_vector(7 downto 0);

type regarray is array (0 to 3) of reg;

signal rf: regarray; ---register file contents

begin

writeport: process (clk)

begin

if (clk'event and clk = '1') then

if (we = '1') then

rf(conv_integer(wa)) <= input;

end if;

end if;

end process;

readporta: process (rae, raa)

begin

if (rae = '1') then

aout <= rf(conv_integer(raa)); ---convert bit vector to integer

else

aout <= (others => '0');

end if;

end process;

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readportb: process (rbe, rba)

begin

if (rbe = '1') then

bout <= rf(conv_integer(rba)); ---convert bit vector to integer

else

bout <= (others => '0');

end if;

end process;

end behavioral;

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2.3.3 : ALU VHDL source codes

-- alu

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is port (

alusel: in std_logic_vector(2 downto 0); ---select for operations

a, b: in std_logic_vector(7 downto 0); ---input operands

f: out std_logic_vector(7 downto 0)); ---output

end alu;

Architecture behavior of alu is

begin

process(alusel, a , b)

begin

case alusel is

when "000" => ---pass A through

f <= a;

when "001" => ---AND

f <= a and b;

when "010" => ---OR

f <= a or b;

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when "011" => ---NOT

f <= not a;

when "100" => ---add

f <= a + b;

when "101" => ---subtract

f <= a - b;

when "110" => ---increment

f <= a + 1;

when others => ---decrement

f <= a - 1;

end case;

end process;

end behavior;

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2.3.4 : Shifter VHDL source codes

--shifter

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--use IEEE.STD_LOGIC_ARITH.ALL;

--use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shifter is port (

shsel: in std_logic_vector(1 downto 0); ---select for operations

input: in std_logic_vector(7 downto 0); ---input operands

output: out std_logic_vector(7 downto 0)); ---output

end shifter;

architecture behavior of shifter is

begin

process(shsel, input)

begin

case shsel is

when "00" => ---pass through

output <= input;

when "01" => ---shift right

output <= input(6 downto 0) & '0';

when "10" => ---shift left

output <= '0' & input(7 downto 1);

when others => ---rotate right

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output <= input(0) & input(7 downto 1);

end case;

end process;

end behavior;

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2.3.5 : Tri-State Buffer VHDL source codes

-- tri-state buffer

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--use IEEE.STD_LOGIC_ARITH.ALL;

--use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tristatebuffer is port (

e: in std_logic;

d: in std_logic_vector(7 downto 0);

y: out std_logic_vector(7 downto 0));

end tristatebuffer;

architecture behavioral of tristatebuffer is

begin

process (e, d)

begin

if (e= '1') then

y <= d;

else

y <= (others => 'Z' );

end if;

end process;

end behavioral;

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2.3.6 : Top Model VHDL source codes

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--use IEEE.STD_LOGIC_ARITH.ALL;

--use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity datapath is port (

clock: in std_logic;

input: in std_logic_vector (7 downto 0);

ie, we: in std_logic;

wa: in std_logic_vector (1 downto 0);

rae: in std_logic;

raa: in std_logic_vector (1 downto 0);

rbe: in std_logic;

rba: in std_logic_vector (1 downto 0);

alusel: in std_logic_vector (2 downto 0);

shsel: in std_logic_vector (1 downto 0);

oe: in std_logic;

output: out std_logic_vector(7 downto 0));

end datapath;

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architecture structural of datapath is

component mux2 port (

s: in std_logic; ---select lines

d1, d0: in std_logic_vector(7 downto 0); ---data bus input

y: out std_logic_vector(7 downto 0)); ---data bus output

end component;

component regfile port (

clk: in std_logic; ---clock

we: in std_logic; ---write enable

wa: in std_logic_vector(1 downto 0); ---write address

input: in std_logic_vector(7 downto 0); ---input

rae: in std_logic; ---read enable ports A & B

raa: in std_logic_vector(1 downto 0); ---read address ports A & B

rbe: in std_logic; ---read enable ports A & B

rba: in std_logic_vector(1 downto 0); ---read address ports A & B

aout, bout: out std_logic_vector(7 downto 0)); ---output port A & B

end component;

component alu port (

alusel: in std_logic_vector(2 downto 0); ---select for operations

a, b: in std_logic_vector(7 downto 0); ---input operands

f: out std_logic_vector(7 downto 0)); ---output

end component;

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component shifter port (

shsel: in std_logic_vector(1 downto 0); ---select for operations

input: in std_logic_vector(7 downto 0); ---input operands

output: out std_logic_vector(7 downto 0)); ---output

end component;

component tristatebuffer port (

e: in std_logic;

d: in std_logic_vector(7 downto 0);

y: out std_logic_vector(7 downto 0));

end component;

signal muxout, rfaout, rfbout: std_logic_vector(7 downto 0);

signal aluout, shiftout, tristateout: std_logic_vector(7 downto 0);

begin

u0: mux2 port map (ie, input, shiftout, muxout);

u1: regfile port map (clock,we,wa,muxout,rae,raa,rbe,rba,rfaout,rfbout);

u2: alu port map(alusel, rfaout, rfbout, aluout);

u3: shifter port map(shsel,aluout,shiftout);

u4: tristatebuffer port map (oe, shiftout, tristateout);

output <= tristateout;

end structural;

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2.4 Logic Simulation

2.4.1 MUX

RTL Schematic

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Technology Schematic

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2.4.2 Register File

RTL Schematic

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Technology Schematic

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2.4.3 ALU

RTL Schematic

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Technology Schematic

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2.4.4 Shifter

RTL Schematic

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Technology Schematic

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2.4.5 Tri-state buffer

RTL Schematic

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Technology Schematic

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2.4.6 Top Model

RTL Schematic

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Technology Schematic

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Waveform

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waveform

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3.0 Discussion

The multiplexer circuit is typically used to combine two or more digital signals onto a
single line, by placing them there at different times. Technically, this is known as time-
division multiplexing.This is a digital circuit with multiple signal inputs, one of which is
selected by separate address inputs to be sent to the single output. It's not easy to describe
without the logic diagram, but is easy to understand when the diagram is available. Input A is
the addressing input, which controls which of the two data inputs, X0 or X1, will be
transmitted to the output. If the A input switches back and forth at a frequency more than
double the frequency of either digital signal, both signals will be accurately reproduced, and
can be separated again by a demultiplexer circuit synchronized to the multiplexer.
Multiplexers are not limited to two data inputs. If we use two addressing inputs, we can
multiplex up to four data signals. With three addressing inputs, we can multiplex eight
signals.

Arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical
operations. Most ALUs can perform the following operations such as Integer arithmetic
operations (addition, subtraction, and sometimes multiplication and division, though this is
more expensive) , Bitwise logic operations (AND, NOT, OR, XOR) , Bit-shifting operations
(shifting or rotating a word by a specified number of bits to the left or right, with or without
sign extension). Shifts can be interpreted as multiplications by 2 and divisions by 2. An ALU
must process numbers using the same format as the rest of the digital circuit. The format of
modern processors is almost always the two's complement binary number representation.
Early computers used a wide variety of number systems, including one's complement, sign-
magnitude format, and even true decimal systems, with ten tubes per digit.ALUs for each one
of these numeric systems had different designs, and that influenced the current preference for
two's complement, as this is the representation that makes it easier for the ALUs to calculate
additions and subtractions. The two's-complement number system allows for subtraction to be
accomplished by adding the negative of a number in a very simple way which negates the
need for specialised circuits to do subtraction.

A register file is an array of processor registers in a central processing unit (CPU).

When it comes to coding up the design, there are a couple of key choices to make -
behavioural or structural coding style. We trod the structural path as this allowed me to play
with a variety of VHDL coding techniques. It also seemed that a behavioural approach
wouldn't be as challenging.From the code, we can see that quite a few generate statements are
used. Sometimes the generate loop uses an array attribute, sometimes it uses a constant for the
loop parameter. Many of the internal signals required the definition of their own data type.
This was a synthesis tool constraint rather than a modelling decision, but that's another story.
we also decided to mix multi-dimensional array indexing approaches. The register file ports
and the latch actual signals are 2-index arrays whereas most of the other signals are arrays of
vectors.To implement the register file in a reasonably efficient way, we opted to use latches as
the storage elements rather than flip-flops. There is no write address port conflict arbitration
as yet.

Tri-state buffer is buffer's output is defined as z = x. Thus, if the input, x is 0, the

output, z is 0. If the input, x is 1, the output, z is 1. It's a common misconception to think that
0 is nothing, while 1 is something. In both cases, they're something. If you read the discussion
in What's a Wire, you'll see that a wire either transmits a 0, a 1, or "Z", which is really what's
nothing. It's useful to think of a wire as a pipe, and 0 as "red kool aid" and 1 as "green kool

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aid" and "Z" as "no kool aid". A tri-state buffer is a useful device that allows us to control
when current passes through the device, and when it doesn't. A tri-state buffer has two inputs:
a data input x and a control input c. The control input acts like a valve. When the control input
is active, the output is the input. That is, it behaves just like a normal buffer. The "valve" is
open. When the control input is not active, the output is "Z". The "valve" is open, and no
electrical currentflows through. Thus, even if x is 0 or 1, that value does not flow through.
The behavior of a active-high tri-state buffer in this situation, when the output is Z, that
means it's high impedance, neither 0, nor 1, i.e., no current.

Shift register is a cascade of flip flops, sharing the same clock, which has the output of
any one but the last flip-flop connected to the "data" input of the next one in the chain,
resulting in a circuit that shifts by one position the one-dimensional "bit array" stored in it,
shifting in the data present at its input and shifting out the last bit in the array, when enabled
to do so by a transition of the clock input. More generally, a shift register may be
multidimensional, such that its "data in" input and stage outputs are themselves bit arrays: this
is implemented simply by running several shift registers of the same bit-length in
parallel.Shift registers can have both parallel and serial inputs and outputs. These are often
configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also
types that have both serial and parallel input and types with serial and parallel output. There
are also bi-directional shift registers which allow shifting in both directions: L→R or R→L.
The serial input and last output of a shift register can also be connected together to create a
circular shift register. One of the most common uses of a shift register is to convert between
serial and parallel interfaces. This is useful as many circuits work on groups of bits in parallel,
but serial interfaces are simpler to construct. Shift registers can be used as simple delay
circuits. Several bi-directional shift registers could also be connected in parallel for a
hardware implementation of a stack.

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4.0 CONCLUSION

In conclusion, we had done completed this miniproject succefully. We had learn about VHDL
code for modeling the complex general datapath circuit such as 2 to 1 multiplexer, register
file, arimetric logic unit, shifter, tri-state buffer and top model. VHDL software is also an
excellent software to simulate any logic devices, either by RTL circuit of I/O waveform
before implementing it. The language or coding is also very similiar to C language, making it
easier to learn, because C language is the basic language of progarmming language. With
VHDL software, the logic that was simulate is easy in making it because its internal logics
can be seen by this software. This software also can educate people of the datapath of an
ALU, register file and others. Any VHDL code can also be connected or combined to make
one logic unit act as one.

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