Functionality Sharing

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
entity HW is
port (
a,b :in std_logic_vector(7 downto 0);
ctrl:in std_logic;
r : out std_logic_vector(7 downto 0));
end HW;
architecture Behavioral of HW is
signal src0,src1,sum :signed(8 downto 0);
signal b_tmp: std_logic_vector(7 downto 0);
signal cin : std_logic;

begin

src0 <= signed(a & '1');

b_tmp <= (b) when ctrl='0' else
not b ;
cin <= '0' when ctrl='0' else
'1';