Analysis of SRAM cell design: A Better Perspective for Reducing

the chip area and power consumption by increasing the stability of

SRAM cell
Tripti Sharma
Krishan Mehra†
Electronics and
Electronics and
Communication
Communication
Engineering
Engineering
Chandigarh University,
Chandigarh University,
Mohali
Mohali, Punjab
krishanmehra374@gmail.com triptisharma.ece@cumail.in

ABSTRACT The area of SRAM is the basic factor of consideration because

In the semiconductor industry, while designing digital system
memory section plays a significant role on chip. For a long time
now, we have been working on the memory designing but the
process needs modifications every year. Initially we are
working on designing of CMOS based SRAM, following which
we worked on multigate transistor such as design of FinFET
based SRAM. Presently we are working on the latter, because
with the rise in number of transistors, the on-chip region also
increases, which is why we are working on reducing the chip
area as well as the power consumption these days. With the
technology scaling the size of the transistor is decreased but this
will affect instability of SRAM cell. As the technology scaling is
done the SRAM cell is operated below threshold region. The
major concern with operating SRAM below threshold region is
the process variation effects which will cause to transistor
mismatch and also degrade the static noise margin.
KEYWORDS
SRAM, Transistor, subthreshold, threshold voltage, WSNM,
RSNM, VTC, bit lines
1 Introduction
In the semiconductor industry almost all the devices need
information stored in digital form. Memories are used to store
information. The semiconductor memory array can stock a
huge amount of data. The requirement for large storage is
motivating the memory design to denser. The capacity for
storing the information doubles every year (Moore’s law) [1].
The semiconductor circuits design growths the usage of SRAM.
SRAM cell’s area contributes on a large scale to the silicon area.
The semiconductor memories are divided into two groups that
are volatile and non-volatile. Volatile memories are those in
which stored information is missing when power is turned off
whereas in non-volatile data remain the same after getting
power off.
RAM is volatile memory in which we can do read and write
process in the memory cell and ROM is non-volatile memory in
which we can only perform the read operation on the memory
cell. one memory cell has the ability to store one-bit data only.
RAM is classified into two categories i.e. SRAM and DRAM. The
major difference between SRAM and DRAM is that DRAM needs
periodical refresh but it is not required SRAM. In SRAM cell 1-
bit data is stored in the bistable latch (data is either 0 or
1depending on the operation of SRAM cell).
1.1 SRAM design
SRAM cells are designed with various techniques by using the
different number of the transistor (4T-11T) [3] but the 6T
SRAM cell is preferred for the construction of large-scale
memory. 6T SRAM cell contains of two crosses coupled CMOS
inverter used as a bistable latch which save the data shown in
Fig 1.

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https://doi.org/10.1145/3339311.3339338 Fig 1: 6T SRAM cell’s schematic [4]
 ICAICR’19, June ,2019, Shimla H.P India Krishan Mehra et al.

transistor is also a way to rise the constancy of a cell. In 8T

NM2 and NM3 are the access transistor used to access the BIT SRAM cell with a separate path for reading and writing to
and BIT BAR are two-bit lines. once the word line WL is made improve cell, stability is also one method but, the number of
equal to 1(high) both of the transistor NM2 and NM3 get turned transistors will be increased. In [9] CNTFET based SRAM design
on. is advised for highly stable with low power consumption and
less read and write time. TFET base SRAM cell also has low
1.2 Mode of operation: leakage current because TFET has the capacity to attain
subthreshold slopes below 60 mV/decade [10]. Basically, there
are many techniques to estimate the stability of SRAM cell. Two
1.Read mode 2. Write mode 3. Hold mode
most common technique to check the stability is though
measure static noise margin (by butterfly curve) and by N
1). Read mode: In reading operation basically, read the curve method. By achieving high stability, the SRAM cell is safe
information from memory cell throughout the read process it is towards the noise and the flip occurs during reading and writes
necessary to make the WL equal to 1 access the bit lines across the process.
transistor NM2 and NM3. The bit line BL make high and BLB
make low. The output of both BIT and BITBAR is sent to a sense 2.1 SRAM cell with body biasing:
amplifier which is used as a comparator which compares the
voltage. SRAM perform read 1 operation if the voltage difference The threshold voltage of a CMOS transistor can be adjusted by
is high. And when the voltage difference is at low then 0 is read the body biasing technique. Because the difference between body
from SRAM cell [5]. voltage and source voltage affects the Vth of transistor. The body
voltage also effects on the threshold voltage (Vth) of any transistor.
2). Write mode: In write mode basically write the data into The body biasing is a technique which is employed to enhance the
SRAM cell, for writing the data into SRAM cell first make WL constancy of the memory cell. The threshold voltage is decreased
high. To write ‘1’ BIT is at high and BIT BAR is at low voltage. with a drop-in body voltage and increase with a rise in body
And for writing ‘0’ into SRAM cell, BLB is at high and BL at low voltage. Generally, biasing is of two types one is forward body
voltage [5]. biasing and other is reverse body biasing. Threshold (Vth) voltage
reduce in case of forward biasing which allows the transistor to turn
3). Hold mode: In hold mode, WL is at low. And in this mode on speedily and Vth increase in reverse biasing [4].
In SRAM circuits some transistors are operating in on state and
read or write operation will not be performed due to WL is at low
some are in off state. Above 6T SRAM cell is originated with the
voltage both the access transistors are in off state. The memory is
constant bias voltages on devices are forward body biased and off
in the hold state and stored data in this mode remain the same.
devices are reverse body biased by applying such technique the
overall leakage current will be reduced. As the leakage current due
2. Stability to threshold variation reduced to a sufficient level and will also
increase the stability of the circuit. Fig.2 shows 6T SRAM cell
The SRAM cell stability during the read, write and in hold mode Body biasing in which body of every transistor is biased.
is an essential constraint in VLSI field. As the physical dimension
of a transistor is scaled down it will lead to threshold voltage and
leakage current variation and also reduce the supply voltage. The
SRAM cell become less stable with reduced power supply voltage
increases the leakage current. The variability because of random
dopant fluctuation [6] and sub-wavelength lithography is also
reducing the stability of SRAM cell when operated subthreshold
region. The nanodevices are more sensitive to these variations,
these variations effects badly on large SRAM array.
Stability (constancy) of SRAM cell is also depending on NBTI
[7] (Negative bias temperature instability) and PBTI (positive bias
temperature instability) these are the aging phenomena observed in
MOS devices. These phenomena decrease the drain to source
current and increase the propagation delay and leakage power [8].
These two phenomena become main reliability concern because
they deteriorate MOSFET which effects badly on the functioning
of SRAM cells this will cause the degradation instability of
memory cell.
There are many methods in literature to enhance memory Fig.2: 6TSRAM cell with body biasing [4]
functioning and stability. The dimensions of the transistors are
also affecting the constancy of the cell. The appropriate size of
ICAICR’19, June ,2019, Shimla H.P India
2.2 8 Transistor based SRAM cell
The 8-transistor based SRAM cell increases the number of
transistors but this will also increase the constancy of the cell. Here
8T SRAM cell with different path for read and write process are
utilized to boost the functioning of the memory cell. By using such
type of structure there is no cell degradation. As the number of
transistors increases in 8T SRAM cell consumes 30% extra area
then 6T based memory cell. This 30% area is because of the
connection area of WWL and RWL as presented in Fig.3. The 7T
transistor-based memory cell is also mentioned in [11] to increase
the read noise margin and for low Vdd and it will consume less
area.
Fig.3: 8T SRAM CELL with distinct read and write path [11]
2.3 Power gating in SRAM cell
Power gating is another method to shrink standby leakage in
the SRAM cell. In [12] SRAM design a PMOS transistor is placed
between SRAM cell and supply voltage as shown in Fig.4. This
transistor lessens the supply voltage towards the SRAM cell.
Here PMOS transistor self-biased and act as the resistance
between supply and cell. The resistance produced by this PMOS
transistor is decreased by increasing the width of the
transistor.
Fig.4: SRAM cell with power gating technique by using PMOS
[12]
Krishan Mehra et al.
In [12] another circuit is proposed in which an NMOS is placed
between ground and 6T SRAM cell as shown in Fig.5. This
design reduces the subthreshold seepage current because it
will improve the ground level during SRAM operation. This
NMOS transistor is self-biased and works as the resistance
between ground and SRAM cell. Resistance produced by NMOS
is decrease by increasing the width of the transistor.
Fig.5: SRAM cell with power gating technique by using NMOS
[12]
3.Static Noise Margin:
Static noise margin is basically a metrics to determine the
constancy of the memory cell. It defines the highest DC noise
voltage tolerated by a single memory cell with not affecting in
the stored data bit. Static noise margin is noted by the graphical
way that is butterfly curve method. In SRAM cell we use two
cross-coupled inverters either CMOS based or resistive load
[13] inverter and response of the inverter circuit is obtained
through VTC (Voltage transfer characteristics) curve. The
graphical method to estimate the SNM of a memory cell by
plotting the VTC curve for both the inverter by using the square
fitting method. In Square fitting scheme the greatest square is
being fixed in the middle of two intersected VTC curve.
3.1. Dependence of SNM:
Table 1: Effects of various parameters on static noise margin
[14]
 ICAICR’19, June ,2019, Shimla H.P India
Parameter Description
1.VDD SNM varies with VDD of SRAM cell
Temperature At high temperature SNM of SRAM
cell decrease in sub threshold due to
degradation in gain of inverter. And
another reason is that at higher
temperature PMOS weakens.
Random variation Randomness in number of doping
atoms in MOSFET will cause the
mismatch in transistors and effect
badly on the read and write margin
[27].
sizing The static noise margin is also
depending on the transistor’s size.
WSNM of a SRAM cell is depends on
PR and RSNM of SRAM cell is based
on cell ratio [19].
3.2 Write static noise margin (WSNM):
WSNM define the writing stability of the SRAM cell throughout
the writing process. The capability of an SRAM cell to change its
level is known as write SNM [15]. Throughout the writing
process the voltage across both the bit line are opposite. In [18]
the method to measure the WSNM by the bit line voltage. The
voltage of bit line of the node piles the level ‘1’ and swept
downward throughout imitation and bit line voltage, at which
pile up values flips [16,17]. The voltage on the bit line at low-
level value pulls down the VTC curve and require only one root
[18].
The PR ratio affects the write margin [19]. Here PR is given as
PR= (fraction of pull up (PMOS) transistor) / (fraction of access
(NMOS) transistor)
3.3 Read static noise margin (RSNM):
RSNM is the capacity of the required voltage to change the state
throughout the read action. In the reading procedure, SRAM
cell act as a bistable latch and there are two stable states so it
becomes necessary there is the presence of is three separate
roots at voltage characteristics [18]. To study the read noise
margin, the two rectangles are obtained between the VTC
curves. These VTC curves are also called butterfly curve.
As the SRAM cell operates mainly in two modes that are read
and write. In performing read and write there is some delay
exist between these operations, in [20] multi-sized cell
assignment is used and to condense the seepage power
different threshold voltage is used for the different transistor.
Krishan Mehra et al.
Cell proportion disturbs the SNM of SRAM cell throughout the
read operation. With rise in cell ratio the physical dimensions
of driver transistor of SRAM cell are also increase this will cause
increase in current and also the speed of SRAM. Cell ratio is
ratio among the physical dimension of the driver transistor and
load transistor given as
Cell ratio = (size of driver transistor) / (size of load transistor)
4.Power dissipation in SRAM circuit
The scaling of CMOS devices increases in each technology
generation. Scaling is done to accomplish the motive to
accomplish better integration density and functioning.
However, with the increase in scaling leakage current is also
increase. Due to leakage power, there is a decrease observed in
the total power of the IC.
The two major components of leakage in SARM circuits are
subthreshold leakage and gate leakage in a transistor. There is
a number of transistors assembled in large memory array so
this leakage power is rise with the increase in transistors. In
subthreshold leakage, leakage current drifts from drain to
source. The phenomenon responsible for gate leakage is the
tunneling of electrons from the substrate to gate through the
gate oxide. Another reason for leakage is with the technology
scaling the Vth is also reduce due to this small geometry effects
such as DIBL, punch through occurs which results in
exponentially increase in subthreshold current.
Techniques to condense the leakage power
reduction
1.Double threshold CMOS
In the dual threshold, the subthreshold leakage current is
reduced by allocating high Vth to some transistor through a
non-critical path.
2.The doping profile of transistor
The threshold voltage also increases with increasing the
channel doping densities and the process requires a couple of
additional masks.
3. Power reduction by adding sleep transistor
In this technique leakage power is condensed by adding the
sleep transistor [28] means that in 6T SRAM two extra
transistor is added those are ON during active mode and turn
off in hold state of memory. The PMOS transistor is added
between the power supply and latch and NMOS transistor is
added between latch and ground as shown in the figure.
There are two methods for adding the sleeping transistor in the
SRAM circuit.
1.The first method in which the PMOS transistor is added
between the power supply and latch and NMOS transistor is
assembled between latch and ground as shown in Fig.6.
ICAICR’19, June ,2019, Shimla H.P India Krishan Mehra et al.

During active mode, the input of the PMOS(M7) transistor is
low and input of NMOS (M8) is high and in this, both of these
transistors are getting turned on. Both of the transistors are
turned off in hold state. So, the leakage power is reduced in hold
mode because in this mode both the transistors are turned off.
to VTH and input at the gate of PMOS(M8) is approximately
equal to (VDD-VTH). Both are turned off in hold state due to
this there is a reduction in power consumption in the SRAM
circuit [28].

Fig 6: 6T SRAM cell with sleep transistor (NMOS connected to

Fig 7: 6T SRAM cell with sleep transistor (PMOS connected to
ground and PMOS connected to VDD) [28]
ground and NMOS connected to VDD) [28]
1. In the second method which the NMOS transistor is added
between the power supply and latch and PMOS transistor is
assembled between latch and ground as shown in Fig.7. Both of
the sleep transistors are turned on in the active mode. The
input voltage at the gate of NMOS (M7) is approximately equal
 ICAICR’19, June ,2019, Shimla H.P India Krishan Mehra et al.

Table 2: summary sheet of various SRAM design

Sr.no. Reference Supply Technology Static noise margin Number of

voltage node transistors

1. [1] 1.1V 50nm WSNM=380mV 6T

RSNM=315Mv

2. [4] 400mv 45nm WSNM=60Mv 6T

3. [5] 0.7V 130nm RSNM 1=0.266V 8T

RSNM2=0.169V
WSNM1=0.400V
WSNM2=0.423V
4 [12] 0.V-1.1V 45nm RSNM=40mV 6T (With
WSNM=300mV
power gating
transistor)
5. [18] 300mV, 130nm WSNM=300mV 8T,10T
350mV

6. [19] - 45nm RSNM=565mV 7T

WSNM=580mV
7. [21] 0.4-1.2V - 0.20-0.21V 6T

8. [22] Vth=140mV 65nm,16nm SNM 8T=233mV 6T,8T

SNM 6T=125mV

9. [23] 0.35V 32nm SNM=0.33V,0.35V 6T

10. [24] - 45nm - 6T

11. [25] 1.2V- 65nm - 6T

200mV

12. [26] 0.5V 7nm HSNM=213Mv 7T

RSNM=213mV
WSNM=123mV

5.Conclusion: increase. Temperature effects badly the WSNM and RSNM as

the temperature increases both of these will decrease.
From the above review, it is clear that as the number of Transistor’s size matching is also a major concern during the
transistors rises the stability of SRAM memory cell will also designing of SRAM. To minimize the power consumption of
ICAICR’19, June ,2019, Shimla H.P India Krishan Mehra et al.

SRAM cell Power gating is a successful technique. 8 transistor- is a need to advance the SNM and power consumption of 6T
based SRAM cell has good SNM but due to area concern, it is not memory cell. By increasing stability and improving the static
preferred for a large memory array in industrial level. So, there noise margin, 6T transistor becomes preferable for high speed

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