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    CHAITANYH Er
    34 views4 pages
    The document contains code for setting up clocks and timing constraints in a synthesis tool. It creates a clock with period 100ns, adds uncertainty of 0.1ns for setup and 0.05ns for hold, generates divided clocks, and sets multicycle paths and input/output delays.

    Original Description:

    Basic sdc commands

    Original Title

    sdc_commands

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    The document contains code for setting up clocks and timing constraints in a synthesis tool. It creates a clock with period 100ns, adds uncertainty of 0.1ns for setup and 0.05ns for hold, generates divided clocks, and sets multicycle paths and input/output delays.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    34 views4 pages

    SDC Commands

    Uploaded by

    CHAITANYH Er
    The document contains code for setting up clocks and timing constraints in a synthesis tool. It creates a clock with period 100ns, adds uncertainty of 0.1ns for setup and 0.05ns for hold, generates divided clocks, and sets multicycle paths and input/output delays.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 4

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 200 [get_ports clk]

    #clock uncertainity

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 100 [get_ports clk]

    #clock uncertainity

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    set_input_delay -max 40 -clock clk [get_ports data_in]

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 200 [get_ports clk]

    #clock uncertainity

    create_generated_clock -name "clk_div2" -divide_by 2 -source clk [get_pins clk_div2_reg/o]


    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    #multicycle path

    set_multicycle_path 1 -setup -end -from clk_div2 -to clk

    set_multicycle_path 0 -hold -start -from clk_div2 -to clk

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 200 [get_ports clk]

    #clock uncertainity

    create_generated_clock -name "clk_div2" -divide_by 2 -source clk [get_pins clk_div2_reg/o]

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    #multicycle path

    set_multicycle_path 1 -setup -end -from clk -to clk_div2

    set_multicycle_path 0 -hold -start -from clk -to clk_div2

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 200 [get_ports clk]

    #clock uncertainity

    create_generated_clock -name "clk_div2" -divide_by 2 -source clk [get_pins clk_div2_reg/o]


    create_generated_clock -name "clk_div3" -multiply_by 3 -source clk_div2 [get_pins clk_div3_reg/o]

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    #multicycle path

    set_multicycle_path 1 -setup -end -from clk -to clk_div3

    set_multicycle_path 0 -hold -start -from clk -to clk_div3

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 100 [get_ports clk]

    #clock uncertainity

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    set_input_delay -max 40 -clock clk [get_ports data_in1]

    set_input_delay -max 50 -clock clk [get_ports data_in2]

    set_output_delay -max 3 -clock clk [get_ports data_out]


    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 100 [get_ports clk]

    #clock uncertainity

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    #create clock --> 100ns (as i saw the cell delay to be very high)

    #create_clock -period 100 [get_ports clk]

    create_clock -period 100 [get_ports clk]

    #clock uncertainity

    #setup

    set_clock_uncertainty -setup 0.1 [get_clocks clk]

    #hold

    set_clock_uncertainty -hold 0.05 [get_clocks clk]

    set_input_delay -max 40 -clock clk [get_ports data_in1]

    set_input_delay -max 50 -clock clk [get_ports data_in2]

    set_output_delay -max 3 -clock clk [get_ports data_out]

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