This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2015.2498118, IEEE
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A Novel Pulse Width Modulation Method for Reactive

Power Generation on a CoolMOS and SiC Diode Based
Transformerless Inverter
Baifeng Chen, Student Member, IEEE, Bin Gu, Member, IEEE, Lanhua Zhang, Student Member, IEEE,
Jih-Sheng Lai, Fellow, IEEE
Abstract—For efficiency considerations in the photovoltaic topologies have been adopted [7]-[13]. The H-bridge single-
(PV) power generation, high efficiency CoolMOS and SiC-diode phase inverter, as shown in Fig. 1, utilizes insulated-gate-
based transformerless inverters have been proposed and studied bipolar-transistors (IGBTs) as the power device in commercial
in the previous literatures, but the reactive power generation
products. The advantages of this inverter topology are its
capability to meet the upcoming standards has never been
discussed. By reviewing the high efficiency converters with simple structure and its capability to produce reactive power.
CoolMOS and SiC-diodes, this paper improves a previous The main drawback for this inverter design is it requires the
transformerless inverter circuit and presents related operating use of bipolar PWM modulation to avoid common mode (CM)
modes for reactive power generation. A novel pulse width voltage [7]. As a result, the efficiency suffers due to high
modulation (PWM) method for this improved inverter topology switching loss on the IGBTs, high current ripple induced core
is then proposed for reactive power generation. The ground loop
and associated losses on the output filter inductor. The
voltage of this inverter under the proposed PWM method is also
derived with common mode and differential mode circuit commercial string inverter product adopts this IGBT based H-
analyses, which indicate that high-frequency voltage components bridge topology. Its maximum efficiency is 97.1%, and the
can be minimized with symmetrical design of inductors. A 250- California Energy Commission (CEC) weighted efficiency is
W inverter hardware prototype has been designed and 96.5% [14]. The CEC efficiency suffers because IGBT has a
fabricated. Steady state and transient operating conditions are fixed voltage drop that significantly reduces the light-load
tested to demonstrate the validity of the improved inverter and
efficiency and also the low switching speed.
proposed PWM method for reactive power generation, and the
high-frequency-free ground loop voltage.
Index Terms— Reactive power, transformerless inverter,
CoolMOS, SiC diode, photovoltaic.

I. INTRODUCTION

W ith an increasing amount of PV installations, the PV

output create a significant impact to the entire power
grid [1]-[3]. In order to fully utilize the PV inverter
capabilities to improve the grid stability, reliability, quality,
and efficiency [4]-[6], IEEE 1547a [4] and The California’s
Electric Tariff Rule 21 [5] are proposing the role of the
distributed energy resource systems to include PV generation.
The main requirements of upcoming standards in the United
States for PV inverters are summarized as follows:
1. Providing reactive power with a fixed power factor.
2. Providing dynamic reactive power injection through
autonomous responses to local voltage measurements.
3. Providing “soft-start” methods for reconnection.
Thus, future PV inverters need to have reactive power
capability, which highly impacts transformerless inverter
design.
In recent years, single-phase transformerless PV inverter
products are becoming increasingly popular. For efficiency
considerations and standards compliance, a variety of inverter
Manuscript received April 04, 2015; revised June 18, 2015 and August 7,
2015; accepted August 29, 2014.
Copyright (c) 2015 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
This work was supported by the U.S. Department of Energy under Award
Number DE-EE0004681.
The authors are with the Future Energy Electronics Center, Virginia Tech,
Blacksburg, VA 24061 USA (e-mail: bfchen@vt.edu; gubin@vt.edu;
lhzhang@vt.edu; laijs@vt.edu),
Fig. 1. IGBTs based H-bridge inverter
The super-junction metal oxide semiconductor field effect
transistor’s (SJ-MOSFET or CoolMOS) voltage drop is
resistive and is preferred for maintaining high efficiency under
light-load conditions and also for fast switching speed.
However, high-voltage CoolMOS suffers from slow reverse
recovery of its snappy body diode, which not only produces
high dv/dt, di/dt, and high power loss, but also creates phase-
leg shoot through risk [15]-[20]. Therefore, high-voltage
MOSFETs based phase-leg with top and bottom
complimentary devices are not suitable for hard switching
applications. The bidirectional phase-leg with complimentary
CoolMOS is shown in Fig. 2 (a).
High efficiency power converters can be achieved by using
CoolMOS and Silicon Schottky Carbide (SiC) diode. Typical
examples are boost converters (as shown in Fig. 2(b)) and
buck converters (as shown in Fig. 2(c)); in which, the snappy
body diode will not conduct current under unidirectional
current flowing. The reverse recovery can be avoided with the
SiC diode, and high efficiency can be achieved with high
switching speed and low conduction loss of CoolMOS.
The high-efficiency power convertion method with
CoolMOS and SiC diode can also be applied in the ac to dc

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power factor correction (PFC) rectifier. As shown in Fig. 3, disable the MOSFET body diode. This MOSFET based phase-
the dual boost bridgeless PFC topology with CoolMOS and leg method avoids the MOSFET body diode reverse recovery.
SiC diode is widely used in off-line AC-DC power adapters, The inverter phase-leg method is shown in Fig. 5.
electrical vehicle chargers and so on[21]-[24]. Single-phase transformerless inverter in [26] only supports
unity power factor operation and has 3 limitations for reactive
S1 D S
L power generation. The first limitation is the diodes D1 through
L L
D4 in the circuit proposed are small clamping diodes D1
S through D4, which can only support unity power factor
S2 D
conditions. The second limitation is the circuit operating
(a) (b) (c) modes for reactive power generation is not described, which
Fig. 2. (a) Bidirectional phase-leg with CoolMOS; (b) Boost converter with should contain the ac to dc boost operation mode for reactive
CoolMOS and SiC diode; (c) Buck converter with CoolMOS and SiC diode. power generation. The third limitation is it is not capable of
iLoad
implementing reactive power generation with the PWM
D1 D2
Li1
modulation method proposed in [26], or the traditional
unipolar or bipolar modulation method.
Vac Cf
Li2 Buck Boost
CO
converter
Load converter S1 D2
D4 S1 S2
D3 Lph L

Fig. 3. Dual boost bridgeless PFC rectifier

D1 S2
IPV S1 S2
Li1
Fig. 5. Phase-leg method in reference [26]
Cf Vac
Cpv Li2 IPV S1 D2 D4 S3
Lo1 2 Lo2 Iac
1
D1 D2 S3 S4
D5 S6 +
Cdc
Cf Vac
Fig. 4. Dual buck transformerless inverter
S5 4 Lo4D6 3 -
For the PV transformerless inverter application, a dual Lo3
circuit of the dual boost bridgeless PFC is shown in the Fig. 4, D1 S2 S4 D3
which can be named as dual buck transformerless inverter.
This dual buck transformerless inverter is used in a Fig. 6. CoolMOS/SiC-diode based transformerless inverter in reference [26]
commercial product [25]. As shown in the Fig. 4, the dual In summary, by using the IGBTs in the transformerless PV
buck inverter needs four CoolMOS and two Schottky diodes, inverter, it is less of an issue to meet future standards that
and the CoolMOS phase leg is split into two independent buck require the reactive power generation, but efficiency will
converters by two filter inductors (S1 and S3 are split with Li1; suffer due to slow switching speed and fixed conduction
S2 and S4 are split with Li2), so the body diode of CoolMOS voltage drop of the IGBTs. The use of CoolMOS with SiC
will not conduct, and the reverse recovery issues can be diode allows for inverter efficiency improvement, but it is
avoided. In addition, this inverter can use unipolar modulation difficult to implement reactive power generation due to
to achieve low common mode voltage. With CoolMOS / SiC- bidirectional power flowing requirement.
diode and unipolar modulation, the inverter can get 99% over This paper will improve CoolMOS/SiC-diode based
a wide load range [7]. The major drawbacks of this inverter transformerless PV inverter [26] circuit in Section II, and then
are (1) an additional large-size inductor, which has 50% of the describe its operation modes for reactive power generation
utilization because each inductor only conducts either positive condition. A novel PWM modulation scheme associated with
or negative line cycle, and (2) it is not possible to realize this identical inverter topology for reactive power generation
reactive power generation because it only allows will be described in Section III. The CM and DM voltage
unidirectional power flow from dc to ac. analysis of the ground loop voltage using the proposed PWM
Shown in Fig. 6, a high-efficiency single-phase modulation method will be analyzed and presented in Section
CoolMOS/SiC-diode based transformerless PV inverter has IV. Experimental waveforms and tested efficiency will be
been proposed in [26]. The key to achieving high efficiency shown in Section V to demonstrate the validity of improved
for this inverter is the same as that of the dual buck inverter and proposed PWM modulation method.
transformerless inverter in Fig. 4, in which a small phase-leg
splitting inductor Lph is adopted to split the MOSFET phase- II. OPERATING MODES OF THE IMPROVED INVERTER
leg into an independent buck converter and boost converter to
One limitation of the circuit proposed in [26] is the use of

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small clamping diodes D1 through D4, which can only support from dc to ac grid. As shown in Fig. 9(b), when S1 and S4 are
unity power factor condition (clamping diodes don’t conduct turned off, and freewheeling current will go through S5 and
current, are not power diode). In this paper, these clamping D5. In this buck operating mode, S1 and S4 are the active
diodes are replaced with Schottky power diodes and will switches, D5 is the freewheeling diode. The inductor voltage-
conduct current when energy is transferred from ac grid side second balance can be expressed as:
to dc side. As shown in Fig. 7, with the use of Schottky Vdc  Vac   D  Vac  (1  D)Vac  0 (1)
diodes, the improved circuit allows non-unity power factor
The relationship between duty cycle (D) of S1 and S4, input
power flowing.
dc voltage (VDC), and output ac voltage (Vac) is:
IPV S1 D2 D4 S3 D  Vac / Vdc (2)
Lo1 2 Lo2 Iac
1 S1 D2 D4 S3
IPV
+ Lo1 Lo2 iac
D5 S6 1 2
Cdc
Cf Vac D5 S6 +
Cdc Cf Vac
S5 4 Lo4D6 3 - D6
S5 4 Lo4 3 -
Lo3 Lo3
D1 S2 S4 D3 D1 S2 S4 D3

(a)
Fig. 7. Improved CoolMOS/SiC-diode based transformerless inverter
IPV S1 D2 D4 S3
Lo1 Lo2 iac
Vac 1 2
D5 S6 +
Iac Cdc Cf Vac
D6
S5 4 Lo4 3 -
0
Lo3
D1 S2 S4 D3

(b)
IV I II III
Fig. 9. Buck operating mode in the I region
Fig. 8. Four different regions in time domain under current lagging condition
IPV S1 D2 D4 S3
According to the direction of the inverter output voltage 1
Lo1
2 Lo2 iac

and output current, the inverter working condition under D5 S6 -

Cdc
reactive power generation can be divided in to four different D6
Cf Vac
+
regions, The sequence of four different regions under the S5 4 Lo4 3
Lo3
current lagging (overexcited power factor or generating D1 S2 S4 D3
reactive power) condition in one line cycle is shown in Fig. 8. (a)
As shown in Fig. 8, four different regions can be defined as
S1 D2 S3
follows. IPV
Lo1
D4
Lo2 iac
1 2
Region I: inverter output voltage and output current are
D5 S6 -
both positive, energy is transferred from dc side to ac grid Cdc Cf Vac
D6
side, and inverter should be operated under buck mode. S5 4 Lo4 3 +
Region II: inverter output voltage is negative and output Lo3
D1 S2 S4 D3
current is positive, energy is transferred from ac side to dc
side, and inverter should be operated under boost mode [22]- (b)
[23]. Fig. 10. Boost operating mode in the II region
Region III: inverter output voltage and output current are When the grid voltage is negative and the output current is
both negative, energy is transferred from dc side to ac grid positive, inverter works in region II. The inverter circuit will
side, and inverter should be operated under buck mode. be operated in boost mode with S5. Switch S5 operates in high
Region IV: inverter output voltage is positive and output frequency, and D1 and D4 are the freewheeling diodes. The
current is negative, energy is transferred from ac side to dc inverter operating mode is shown in Fig. 10. As shown in Fig.
side, and inverter should be operated under boost mode. 10(a), when S5 is turned on, diodes D1 and D4 will be turned
Based on the above analysis, four different inverter circuit off, ac grid voltage will charge the filter inductors. In Fig.
operating modes for four different regions will be proposed in 10(b), when S5 is turned off, freewheeling current will go
this part. When the grid voltage and the inverter output current through diodes D1 and D4, and the energy will be transferred
are both positive, the inverter works in region I. The inverter from ac side to dc side. In this boost operating mode, S5 is the
circuit will be operated in buck mode with S1, S4 and S5. S1 boost active switch, D1/D4 are the freewheeling diodes.
and S4 switch simultaneously in high frequency; S5 remains on The inductor voltage-second balance and duty cycle of S5
during this region. The inverter circuit operating mode is can be expressed as:
shown in Fig. 9. As shown in Fig. 9(a), when S1 and S4 are Vac  D  Vdc  Vac   (1  D)Vac  0  (3)
turned on, D5 will be turned off, the energy will be transferred

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D  1  Vac / Vdc (4) is the boost conversion active switch, and D2 and D3 are the
When the grid voltage and the output current are both freewheeling diodes. The duty cycle of S6 is:
negative, the inverter works in region III. The inverter circuit D  1  Vac / Vdc Vac  0 (6)
will be operated in buck mode with S2, S3 and S6. S2 and S3 In summary, the improved inverter circuit can be operated
will switch simultaneously in high frequency, and S6 remains in buck mode or boost mode to achieve any power factor
on. The inverter operating mode is shown in Fig. 11. As operating, but a proper PWM modulation is need to operate
shown in Fig. 11(a), when S2 and S3 are turned on, D6 will be this inverter circuit in these different modes for reactive power
turned off, and the energy will be transferred from dc to ac generation.
grid. As shown in Fig. 11(b), when S2 and S3 are turned off,
the freewheeling current will go through S6 and D6. S2 and S3 III. PROPOSED PWM METHOD AND REALIZATION
are the active switches for buck conversion, D6 is the As shown through Fig. 8 to Fig. 12, with a proper PWM
freewheeling diode. The duty cycle of S2 and S3 is: modulation, the inverter can work in any power factor
D  Vac / Vdc Vac  0 (5) condition, but traditional unipolar modulation, bipolar
modulation [7], and the modulation method proposed in [26]
IPV S1 D2 D4 S3 cannot be applied here. This section will propose a novel
Lo1 Lo2 iac
1 2 PWM realization method for reactive power generation and
Cdc
D5 S6 - related implementation method. The control system for
Cf Vac
D6
+
voltage reference generation is shown in Fig. 13. As compared
S5 4 Lo4 3
Lo3
with the traditional H-bridge inverters, the control system and
D1 S2 S4 D3 the sinusoidal voltage reference (Vref) generation in the
(a) proposed inverter is as same as [27]-[31]. The difference is
IPV S1 D2 D4 S3
after getting the voltage reference (Vref), there will be
1
Lo1
2 Lo2 iac individual duty cycle generator and individual PWM
D5 S6 - modulation for each switching device, which is shown in Fig.
Cdc Cf Vac
D6 14.
S5 4 Lo4 3 +
Grid Voltage
Lo3 Vac
D1 S2 S4 D3 Feedforward Control
PLL Vdc 
(b) 
cos  sin   Vref
Fig. 11. Buck operating mode in the III region Iac
Vdc Id_ref  Current
  PI Current Iref Ierr
IPV S1 D2 D4 S3 Feedback
1
Lo1
2 Lo2 iac 
Vdc_ref PF  cos 
Reference 
Generator Controller
D5 S6 +
Cdc Cf Vac Fig. 13. Control system for voltage reference generation
D6
S5 4 Lo4 3 - Duty Cycle d14
 Gating_S1&S4
Lo3 Generator (S1/S4)
D1 S2 S4 D3 

(a) Duty Cycle d5

 Gating_S5
Generator (S5)
IPV S1 D2 D4 S3 Vref 
Lo1 Lo2 iac
1 2 Duty Cycle d23
 Gating_S2&S3
D5 S6 + Generator (S2/S3)
Cdc Cf Vac 
D6 Duty Cycle d6
S5 4 Lo4 3 -  Gating_S6
Generator (S6)
Lo3 Vac
1 
D1 S2 S4 D3 Iref Vcarrier
0
(b)
Fig. 12. Boost operating mode in the IV region Fig. 14. Individual duty cycle generation and PWM modulation method

When the grid voltage is positive and the output current is
negative, inverter works in region IV and the inverter circuit
will be operated in boost mode with S6. Switch S6 operates in
high frequency, and D2 and D 3 are the freewheeling diodes.
The inverter operating mode is shown in Fig. 12. As shown in
Fig. 12(a), when S6 is turned on, diodes D2 and D3 will be
turned off, and the ac grid voltage will charge the filter
inductor; as shown in Fig. 12(b), when S6 is turned off,
freewheeling current will go through diodes D2 and D3, and
the energy will be transferred from ac side to dc side. The S6
As shown in Fig. 13, for a typical PV inverter, the control
system should consist of an outer loop that regulates the dc
input voltage and an inner loop that controls the ac output
current. The outer loop controller regulates the dc voltage Vdc
with a proportional-integral (PI) controller that provides the
active current reference Id_ref. Through the phase-locked-loop
(PLL), the phase angle information ( sin  ,cos  ) can be
obtained through the grid voltage Vac. By combining the
active current reference and power factor command cos, a
sinusoidal current reference Iref can be generated through the

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current reference generator module. Together with grid inverter operating under unity power factor condition with PF
voltage feedforward control loop and the grid current =1. In this condition, the inverter output voltage and current
feedback controller, a sinusoidal voltage reference (Vref) can follow the sequence of I  III, and only works in buck
then be generated for duty cycle generation and PWM operation in two different regions. The output PWM gating
modulation [7], [9], [27], [28]. pattern for unity power factor condition is as same as the
As shown in Fig. 14, proposed PWM method has an method presented in [26]. Fig. 16(b) depicts the simulation
individual duty cycle generator and PWM modulation module results for the inverter operating under current leading
for each pair of switches. Switches S1 and S4 obtain their duty condition with PF = –0.7. In this condition, the inverter
cycle reference d14 through a duty cycle generator (S1/S4), voltage and current follow the sequence of I  IV  III  II.
which will let inverter to be operated in buck mode in the I Fig. 16(c) depicts the simulation results for the inverter
region (refer to Fig. 9), and the duty cycle of the S1 and S4 is: operating under current lagging condition with PF = +0.7,
d1  d 4  Vref (7) inverter voltage and current will follow the sequence of IV 
Switch S5 obtains the duty cycle reference d5 through a duty I  II  III.
cycle generator (S5), which will let inverter to be operated in
buck mode in the I region and the boost mode in the II region
(refer to Fig. 10). The S5 will be constant on in I region, and
the duty cycle of S5 for the II region is:
d5  1  Vref (8)
Switches S2 and S3 obtain their duty cycle reference d23
through a duty cycle generator (S2/S3), which will let inverter
to be operated in buck mode in the III region (refer to Fig. 11),
and the duty cycle of S2 and S3 is,
d 2  d 3  Vref (9)
Switch S6 obtains the duty cycle reference d6 through a duty
cycle generator (S6), which will let inverter to be operated in
buck mode in the III region and boost mode in the IV region
(refer to Fig. 12). The S6 will be constant on in III region, and
the duty cycle of S6 for the IV region is:
d 6  1  Vref (10)
All four duty cycle generators can be easily realized in the
PWM module of a digital signal processor (DSP), and their
algorithms are described in Fig. 15. After these duty cycle
generators generate their duty cycle references (d14, d5, d23,
d6), the PWM gating signals for each devices can be generated
by comparing their duty cycle references with a triangular
carrier Vcarrier, as indicated in Fig. 14.

Fig. 16. Gating signals of S1/ S4, S5, S2/ S3, and S6 for: (a) unity power factor
condition; (b) current leading condition; (c) current lagging condition.

IV. GROUND LOOP VOLTAGE ANALYSIS

In the transformerless PV inverter system, there is a
parasitic capacitance existing between the PV array cells and
Fig. 15. Corresponding codes in DSP for duty cycle generator modules
the metal frame [32-37]. The PV array cells are connected to
the dc bus (point G in Fig. 17); the PV metal frame is still
The inverter system has been simulated with the proposed
grounded (point E in Fig. 17). So this parasitic capacitance,
duty cycle generator and PWM modulation method described
which is referred as CG-PV in the Fig. 17, will exist in the
in Fig. 13, Fig. 14 and Fig. 15. Simulation results in Fig. 16
ground loop. If the high frequency common mode voltage
shows the inverter output voltage, output current, gating
(CM) voltage and differential mode (DM) voltage are not well
signals: S1/ S4, S5, S2/ S3, and S6 for both unity power factor
controlled, there will be a high frequency ground loop voltage
condition, current leading condition, and lagging conditions
on this parasitic capacitor, and high frequency leakage current
respectively. Fig. 16(a) depicts the simulation results for the
will be generated in turn. This leakage current can cause

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distortion and harmonic, high losses, safety issue, fault VEG - II _ on  VV4 -G  VE -V4 
protection and electron magnetic interference. The (VDM - II _ on  Vac )  ( Lo 3  Lo 4 )
requirements for limiting ground loop leakage current and VCM -II_ on  0.5VDM - II _ on  (15)
Lo1  Lo 2  Lo 3  Lo 4
fault current can be referred to VDE0126-1-1, and UL
Vdc Vac  ( Lo3  Lo 4 )
1741[38], [39]. If inverter circuit and PWM modulation are  
not well designed, bulk CM filter and DM filter are need to 2 Lo1  Lo 2  Lo3  Lo 4
minimize the ground loop CM voltage. If the ground loop CM When S5 is turned off, the ground loop voltage VEG is:
voltage is free of high frequency voltage component, the CM (VDM -II _ off  Vac )  (Lo3  Lo4 )
VEGII _ off  VCM -II_ off  0.5VDM -II _ off 
filter and DM filter can be minimized designed to reduce the Lo1  Lo 2  Lo3  Lo 4
size and cost. This Section will analyze the ground loop (16)
(V  V )  (Lo3 +Lo4 )
 Vdc  dc ac
voltage of improved inverter under the proposed PWM Lo1 +Lo2 +Lo3 +Lo4
modulation method. Analysis results will guide the circuit
components design for low ground loop CM voltage. B. Equivalent circuit with CM and DM model in region IV
Idc D2 D4 S3 As shown in the Fig. 12, when the inverter is working in the
Lo1 Lo2 Iac
S1 region IV, the equivalent circuit with CM and DM model in is
V1 V2 + shown in Fig. 19.
D5 S6
Vdc Cf Vac V2 Lo2 Iac
D6
Lo4 - +
S5 V4 VCM 0.5VDM +
+ -
V3 Lo3 E Cf Vac
D1 S2 S4 D3 - + -
G 0.5VDM
-
G E
CG-PV V3 Lo3
CG-PV
Fig. 17. The inverter system with ground loop parasitic capacitor
Fig. 19. Equivalent circuit with CM and DM model in region IV
The equivalent circuit with CM and DM model in region I
and III has been analyzed in [26], thus the following analysis
will focus on the equivalent circuit in region II and IV. When S6 is turned on, as shown in Fig. 12 (a), the ground
loop voltage VEG is:
A. Equivalent circuit with CM and DM model in region II VEG - IV _ on  VV3 -G  VE -V3 
When the inverter is operating in the region II, as shown in
(VDM - IV _ on  Vac )  Lo3 Vdc Vac  Lo3 (17)
the in Fig. 10, the output terminals of the switch phase legs are VCM -IV_ on  0.5VDM - IV _ on   
V4 and V1, respectively. The equivalent circuit diagram with Lo 2  Lo3 2 Lo 2  Lo3
CM and DM representation in region II is shown in Fig. 18. When S6 is turned off, as shown in Fig. 12 (b), the ground
V4 Lo4 Lo3 loop voltage VEG is:
VCM + + E (VDM - IV _ off  Vac )  Lo3
+ -
0.5VDM VEG  IV _ off  VCM -IV_ off  0.5VDM - IV _ off 
Cf Vac Lo 2  Lo3
- +
0.5VDM (18)
- - (Vdc  Vac )  Lo3
G 
V1 Lo1 Lo2 Iac Lo 2  Lo3
CG-PV
In the inverter, if the inductances of Lo2 and Lo3 have the
same value, and Lo1 and Lo4 values are equal, the ground loop
Fig. 18. Equivalent circuit with CM and DM model in region II
voltage VEG comes out to be the same in different operating
When S5 is turned on, as shown in Fig. 10 (a), the CM and modes according to analysis results in[26] and (15), (16), (17),
DM voltages are: and (18).
VCM - II _ on  (V4  V1 ) / 2  Vdc / 2 (11) VEG - I _ on  VEG  I _ off  VEG - II _ on  VEG  II _ off 
VDM - II _ on  V4  V1  0 (12) Vdc  Vac (19)
VEG - III _ on  VEG  III _ off  VEG - IV _ on  VEG  IV _ off 
As shown in Fig. 10 (b), when S5 are turned off, the free- 2
wheeling current goes through D1 and D4. The CM and DM With proposed PWM modulation method, if the inductors
voltages in the circuit are: (Lo1 and Lo4) or inductors (Lo2 and Lo3) are not designed to
VCM - II _ off  (V4  V1 ) / 2  Vdc / 2 (13) have similar inductance, the DM and CM voltages will have
high-frequency components in the ground loop voltage VEG,
VDM - II _ off  V4  V1  Vdc (14) which will result in high-frequency ground loop leakage
So, when S5 is turned on, as shown in Fig. 10 (b), the current. In order to minimize this high frequency leakage
ground loop voltage VEG is: current, Lo2 and Lo3 are better to be designed with same value.
Similarly, Lo1 and Lo4 are also better to be designed with same
value. With this inductor value match, the ground loop voltage
VEG will be a line-frequency sinusoidal voltage with a dc

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offset, which is shown in (19). In the hardware, Lo2 and Lo3
are coupled together, Lo1 and Lo4 are also coupled together,
and the experimental waveform of VEG will be shown in
Section V to verify the validity of the analysis in this section.
V. EXPERIMENTAL RESULTS
Hardware experiments were conducted by using a 250 W
two-stage micro-inverter [26], [40]. Fig. 20 shows the picture
of the entire hardware prototype that consists of a dc-dc
converter on the left-hand side and the proposed dc-ac inverter
on the right-hand side. The dc-dc converter circuit is not the
main focused in this paper but can be referred to [40].
Fig. 20. 250W micro-inverter hardware prototype
This MOSFET based inverter is running at 30 kHz;
MOSFETs (S1~S6) are IPB65R190C7; diodes (D1~D6) are
IDK03G65C5; inductors Lo1 and Lo4 are coupled together with
0.086 mH, inductors Lo2 and Lo3 are coupled together with 3.7
mH; filter capacitor Cf is 0.47 uF.
Fig. 21. The PWM gating signals for unity power factor (PF=1) operation
Fig. 22. The PWM gating signals for current leading (PF=-0.7) operation
Fig. 23. The PWM gating signals for current lagging (PF=0.7) operation
With 30-kHz switching frequency, the PWM gating signals
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for unity power factor (PF=1) operation is shown in Fig. 21;
PWM gating signals for current leading (PF=-0.7) operation
are shown in Fig. 22; PWM gating signals for current lagging
(PF=0.7) operation are shown in Fig. 23. From the results, it
can be seen that when the output voltage and current are both
positive, S1 and S4 have the same high-frequency gating
signal, while S5 stays on with low-frequency switching.
When the output voltage is negative and current is positive, S5
will switch into high-frequency PWM operation. When the
output voltage and current are both negative, S2 and S3 have
the same high-frequency gating signal, while S6 will stays on
with low-frequency operation. When the output voltage is
positive, and the current is negative, S6 will operate in high-
frequency switching. With the proposed PWM modulation
method described in Fig. 13 and Fig. 14, the experimental
results (in Fig. 22, Fig. 23 and Fig. 24) match the simulation
results (in Fig. 16) reasonably well.
Fig. 24. Transient form unity power factor (PF=1) operation to reactive power
geneartion (PF=0.7) operation
Fig. 25. Transient form unity power factor (PF=1) operation to reactive power
absorbing (PF=-0.7) operation
Fig. 24 shows the voltage and current waveforms under
transition from unity power factor (PF=1) operation to current
lagging (PF=0.7) operation. The inverter dc bus voltage is
380V, and the ac grid voltage is 240V. Before the transition,
the inverter is operating under 250-W pure active power
condition, and the output voltage and output current are in
phase. After the transition, the inverter is operating under
current lagging (PF=0.7) condition, and the ac output power is
about 350 VA, which includes 250 W active power and 250
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VAR overexcited reactive power.
Fig. 25 shows the transition from unity power factor (PF=1)
to current leading (PF=-0.7) operation. Before the transient,
the inverter is also working under 250-W pure active power
condition. After the transient, the inverter is operating under
current leading (PF=-0.7) condition, the ac output power is
about 350 VA, which consists of 250W active power and 250
VAR under-excited reactive power.
As shown in the Fig. 20, the inductors (Lo2 and Lo3) are
coupled together, inductors (Lo1 and Lo4) are also coupled
together. As discussed in the section IV, if Lo2 and Lo3 are
designed to have similar inductance, and Lo1 and Lo4 are
designed to have similar inductance, the waveform of the
ground loop voltage VEG, which is between the ground of grid
and the negative terminal of PV cells, should be a 60 Hz
sinusoidal wave with a dc offset, which can be expressed in
(19). The experiment waveforms in the Fig. 24 and Fig. 25
clearly show that the ground loop voltage VEG is a 60 Hz
sinusoidal wave on top of a dc offset in both steady state and
transient conditions.
The in-house measurement result of a commercial
polycrystalline 240-W solar panel is around 0.6 nF. A 10 nF
equavalent parasitic capacitance is added into the ground loop
for the worst case. The ground loop leakage current is shown
in Fig. 26, which indicates a less than 3 mA peak value.
Therefore, with the proposed inverter circuit and the
symmetrical design of inductors, the ground loop leakage
current can be minimized by using the above proposed PWM
modulation method.
The inverter uses the CoolMOS IPB65R190C7 and SiC
diode IDK03G65C5. YOKOGAWA WT1600 digital power
meter is used to measure the voltages, currents, and efficiency
of the proposed transformerless inverter (not including
auxiliary power loss, DSP power losses, and first stage dc-dc
converter). The efficiency measurement is based on measuring
the inverter output ac power and the inverter dc input power.
The CEC weighted efficiency of proposed inverter power
stage, which is calculated at 10%, 20%, 30%, 50%, 75%, and
100% of the rated power level [8], is 99.01 %, and the
efficiency profile is shown in Fig. 27.
Fig. 26. Ground loop leakage current waveform
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8
Fig. 27. Efficiency test results of proposed transformless inverter
VI. CONCLUSION
A high efficiency CoolMOS and SiC diode based
transformerless PV inverters have been proposed in the
previous literature, but can only operate in unity power factor
condition. In this paper, a novel PWM modulation method is
proposed for reactive power generation. Four different
buck/boost operating modes, a novel PWM algorithm, and the
PWM implementation method for reactive power generation
are proposed and described in detail. The CM and DM model
analyses clearly indicated that under reactive power
generation conditions, the circuit with proposed PWM method
can also avoid high frequency ground loop voltage and current
by symmetrically coupling the inductors. The hardware
prototype of a 250-W micro-inverter has been constructed and
tested under active and reactive power operation, as well as
steady state and dynamic operations to verify the proposed
method.
With verification of hardware testing, the proposed high
efficiency CoolMOS/SiC-diode based transformeless inverter
can be applied in two-stage isolated or non-isolated micro-
inverter and single-stage string inverters, and so on.
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Transactions on Industrial Electronics
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Baifeng Chen(S’11) received the B.S. degree in
Hydropower and Digital Engineering from
Huazhong University of Science and Technology,
and the M.S. degree in Electrical Engineering
from Wuhan University, Wuhan, China, in 2008
and 2010, respectively. Since 2010, he has been a
Graduate Research Assistant and Ph.D. student in
Future Energy Electronics Center (FEEC),
Virginia Tech, Blacksburg, VA.
His research interests include design high-
efficiency converters with wide bandgap power devices and their application
in photovoltaic system, battery charger, and motor driver and so on.
Bin Gu (M’14) received the B.S. degree from
Northeast Dianli University, Jilin, China, in 2002;
the M.S. degree from Zhejiang University,
Zhejiang, China, in 2005; and the Ph.D. degree
from Virginia Polytechnic Institute and State
University, Blacksburg, VA, USA, in 2013 all in
electrical engineering. He is currently working
with Texas Instruments, Santa Clara, USA as a
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TIE.2015.2498118, IEEE
Transactions on Industrial Electronics

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system/applications engineer in GaN thrust group. He is the author or

coauthor of more than 30 technical articles published in various IEEE journals
and conferences.

Lanhua Zhang (S’12) received his B.S. degree

and M.S. degree both in electrical engineering
from Shandong University, China, in 2009 and
2012 respectively. Since 2012, he has been a
Graduate Research Assistant and Ph.D. student in
Future Energy Electronics Center (FEEC),
Virginia Tech, Blacksburg, VA. His research
interests include soft-switching inverter for
renewable energy application, high-efficient
DC/DC converter, and non-linear current control
technology.

Jih-Sheng Lai (F’07) received M.S. and Ph.D.

degrees in electrical engineering from the
University of Tennessee, Knoxville, in 1985 and
1989 respectively. From 1980 to 1983. In 1996,
he joined Virginia Polytechnic Institute and State
University. He is currently the James S. Tucker
Professor and the Director of the Future Energy
Electronics Center. His main research areas are
in high efficiency power electronics conversions
for high power and energy applications. He has
published more than 265 technical papers and 2 books and received 20 U.S.
patents).

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