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Experiment No 1: Full Adder Using Half Adder
Experiment No 1: Full Adder Using Half Adder
1.
module full_adder(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire s1,c1,c2;
or o1 (cout,c1,c2);
endmodule
2.
module halfm (a,b,sum,carry);
input a,b;
output sum,carry;
xor x1 (sum,a,b);
and a1 (carry,a,b);
endmodule
Test – Bench :
module fa_tb();
logic a,b,c,s,cout,s1,cout1;
full_adder f1(a,b,c,s,cout);
always@(*)
begin
{cout1,s1}=a+b+c;
else
end
initial
begin
a=0;b=0;c=0;
#5 a=0;b=0;c=1;
#5 a=0;b=1;c=0;
#5 a=0;b=1;c=1;
#5 a=1;b=0;c=0;
#5 a=1;b=0;c=1;
#5 a=1;b=1;c=0;
#5 a=1;b=1;c=1;
end
endmodule
Output :
Sucess
Fail condition