CS226 LAB 14

Name:Abhay Singh
Roll No:1801CS66
Task1:
Code:
module fsm_snail(smile,clk,reset,in);
input clk, reset;
input in;
output smile;
reg [2:0] next_state;
reg[2:0] state;
parameter [2:0] ZERO=3'b000;
parameter [2:0] FIRST= 3'b001;
parameter [2:0] SECOND= 3'b010;
parameter [2:0] THIRD = 3'b011;
parameter [2:0]FOURTH=3'b100;
always @(posedge clk) // sequential
begin
if (reset) state <= ZERO;
else state <= next_state;
end
always @(state,in) // combinational
begin
case(state)
ZERO:
if (in)
next_state =FIRST;
else
next_state= ZERO;
FIRST:
if (in)
next_state = SECOND;
else
next_state = ZERO;
SECOND:
if (in)
next_state = SECOND;
else
next_state = THIRD;
THIRD:
if (in) next_state = FOURTH;
else
next_state = ZERO;
FOURTH:
if(in)
next_state=SECOND;
else
next_state=ZERO;
endcase
end
// output logic described using continuous assignment
assign smile = (state == FOURTH);
endmodule
Test bench:
module tb_p1();
wire smile;
reg in,clk=1,reset;
always
begin
#5 clk = ~clk;
end
fsm_snail uut(smile,clk,reset,in);
initial
begin
reset=1;
#10;
reset=0;
in=1;
#10;
in=1;
#10;
in=1;
#10;
in=0;
#10;
in=1;
#10;
in=1;
#10;
in=0;
#10;
in=1;
#10;
in=0;
#10;
in=0;
#10;
in=1;
#10;
in=0;
#10;
in=0;
#10;
in=1;
#10;
in=1;
#10;
in=0;
#10;
in=1;
#10;
end
endmodule
Simulation:
Task 2:
Code:
module fsm_counter(state,upper,clk,reset);
input clk, reset;
output [3:0] state;
output upper;
reg [3:0] next_state;
reg[3:0] state;
always @(posedge clk) // sequential
begin
if (reset) state <= 4'b0000;
else state <= next_state;
end
always @(state) // combinational
begin
case(state)
4'b0000:
next_state =4'b0001;
4'b0001:
next_state =4'b0010;
4'b0010:
next_state =4'b0011;
4'b0011:
next_state =4'b0100;
4'b0100:
next_state =4'b0101;
4'b0101:
next_state =4'b0110;
4'b0110:
next_state =4'b0111;
4'b0111:
next_state =4'b1000;
4'b1000:
next_state =4'b1001;
4'b1001:
next_state =4'b1010;
4'b1010:
next_state =4'b1011;
4'b1011:
next_state =4'b1100;
4'b1100:
next_state =4'b1101;
4'b1101:
next_state =4'b1110;
4'b1110:
next_state =4'b1111;
4'b1111:
next_state =4'b0000;
endcase
end
// output logic described using continuous assignment
assign upper = (state >= 4'b1000);
endmodule
Test bench:
module tb_p2();
wire [3:0] state;
wire upper;
reg clk=1,reset;
fsm_counter uu(state,upper,clk,reset);
always
begin
#5 clk=~clk;
end
initial
begin
reset=1;
#10;
reset=0;
end
endmodule
Simulation:
Task 3:
Part a:
Part b:
Code:
module p3_b(out1,out2,res,sela,selb,op,seld,in,clk);
output [7:0] res,out1,out2;
input [2:0] sela,selb,seld,op;
input [7:0] in;
input clk;
reg [7:0] register [1:7];
reg [7:0] out1;
reg [7:0] out2;
reg [7:0] res;
always@(*)
begin
case(sela)
3'b000: out1 = in;
3'b001: out1 = register[1];
3'b010: out1 = register[2];
 3'b011: out1 = register[3];
3'b100: out1 = register[4];
3'b101: out1 = register[5];
3'b110: out1 = register[6];
3'b111: out1 = register[7];
default: out1 = 1'b0;
endcase
end
always@(*)
begin
case(selb)
3'b000: out2 = in;
3'b001: out2 = register[1];
3'b010: out2 = register[2];
3'b011: out2 = register[3];
3'b100: out2 = register[4];
3'b101: out2 = register[5];
3'b110: out2 = register[6];
3'b111: out2 = register[7];
default: out2 = 1'b0;
endcase
end
always@(*)
begin
case(op)
3'b000: res=out1+out2;
3'b000: res=out1-out2;
3'b000: res=~out2;
3'b000: res=out1&out2;
3'b000: res=out1|out2;
endcase
end
always @(posedge clk)
begin
register[seld]<=res;
end
endmodule
Test bench:
module tb_p3b();
wire [7:0] out1,out2,res;
reg [7:0] in;
reg [2:0] sela,selb,seld,op;
reg clk=1;
p3_b uut (out1,out2,res,sela,selb,op,seld,in,clk);
always
begin
#5 clk=~clk;
end
initial
begin
op=0;
in=1;
sela=0;
selb=0;
seld=1;
#9;
in=2;
sela=0;selb=0;
seld=2;
#9;
in=3;
sela=0;
selb=0;
seld=3;
#9;
in=4;
sela=0;
selb=0;
seld=4;
#9;
in=5;sela=0;
selb=0;
seld=5;
#9;
in=6;sela=0;
selb=0;seld=6;
#9;
in=0;sela=2;
selb=3;
#9;
in=0;sela=3;
selb=4;
end
endmodule
Simulation:
Part c:
Circuit:
State Diagram:
Circuit:
Code:
module P3_c(o1,o2,ans,sela,selb,reset,op,seld,in,clk);
output [7:0] ans,o1,o2;
reg [7:0] ans,o1,o2;
reg [7:0] res,out1,out2;
input [2:0] sela,selb,seld,op;
input reset;
integer i=0;
reg [1:0] state;
reg [1:0] next_state;
input [7:0] in;
input clk;
reg [7:0] register [0:7];
parameter FIRST=2'b00;
parameter SECOND=2'b01;
always @(posedge clk)
begin
if(reset)
state<=2'b00;
else
state<=next_state;
end
always @(*)
begin
case(state)
2'b00:
if(reset)
next_state=2'b00;
else
begin
case(sela)
3'b000: out1 = in;
3'b001: out1 = register[1];
3'b010: out1 = register[2];
3'b011: out1 = register[3];
3'b100: out1 = register[4];
3'b101: out1 = register[5];
3'b110: out1 = register[6];
3'b111: out1 = register[7];
default: out1 = 1'b0;
endcase
case(selb)
3'b000: out2 = in;
3'b001: out2 = register[1];
3'b010: out2 = register[2];
3'b011: out2 = register[3];
3'b100: out2 = register[4];
3'b101: out2 = register[5];
3'b110: out2 = register[6];
3'b111: out2 = register[7];
default: out2 = 1'b0;
endcase
o1=out1;
o2=out2;
next_state=2'b01;
end
2'b01:
if (reset)
next_state = 2'b00;
else
begin
case(op)
3'b000: res = out1+out2;
3'b001: res = out1-out2;
3'b010: res = ~out2;
3'b011: res = out1&out2;
3'b100: res = out1|out2;
endcase
ans=res;
next_state = 2'b10;
end
2'b10:
if (reset)
begin
for(i=1;i<8;i=i+1)
register[i]=0;
next_state = 2'b00;
end
else
begin
case (seld)
3'b001: register[1] = res;
3'b010: register[2] = res;
3'b011: register[3] = res;
3'b100: register[4] = res;
3'b101: register[5] = res;
3'b110: register[6] = res;
3'b111: register[7] = res;
endcase
next_state = 2'b00;
end
endcase
end
endmodule
Test bench:
module TB_P3();
reg clk,reset;
reg [2:0] seld, selb,sela;
reg [2:0] op;
reg [7:0] in;
wire [7:0] o1,o2,ans;
always #5 clk = ~clk;
P3_c uut(o1,o2,ans,sela,selb,reset,op,seld,in,clk);
initial begin
clk <=0;
reset <=1;
#6;
reset <=0;
seld <=1;
sela <=0;
selb <=0;
op <=0;
in <=1;
#10;
reset <=0;
seld <=1;
sela <=0;
selb <=0;
op<=0;
in <=1;
#10;
reset <=0;
seld <=1;
sela <=0;
selb <=0;
op <=0;
in <=1;
#10;
seld <=2;
sela <=1;
selb <=0;
op <=0;
in <=2;
#10;
seld <=2;
sela <=1;
selb <=0;
op <=0;
in <=2;
#10;
seld <=2;
sela <=1;
selb <=0;
op <=0;
in <=2;
#10;
seld <= 3;
sela <=1;
selb <= 2;
op <= 0;
in <=3;
#10;
seld <= 3;
sela <=1;
selb <= 2;
op <= 0;
in <=3;
#10;
seld <= 3;
sela <=1;
selb <= 2;
op <= 0;
in <=3;
#10;
seld <= 4;
sela <=1;
selb <= 3;
op <= 0;
in <=4;
#10;
seld <= 4;
sela <=1;
selb <= 3;
op <= 0;
in <=4;
#10;
seld <= 4;
sela <=1;
selb <= 3;
op <= 0;
in <=4;
#10;
end
endmodule
Simulation:

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