International Journal of Electronics, Electrical and Computational System

IJEECS
ISSN 2348-117X
Volume 5, Issue 12
December 2016

Designing of Look Ahead Carry Adder by using VHDL

Deepti Rajput ,
Assistant Professor, Department of Electronics & Communication,
Faculy of Engineering, Teerthanker Mahaveer University, Moradabad

ABSTRACT
Now we required fast addition it plays an important role in highly developed digital systems. Fast adders means that they
are able to calculate the carry propagation much faster without having to wait for it to ripple the adders. The CLA
technique is the mostly used for accelerating the carry propagation. The CLA is to be designed with combination of 4-bit
adders. The design is implemented, simulated and synthesized by using VHDL. According to the chip’s density, designers
are trying to give some facilities of computational and storage space on single chips. So, hardware design will be built
for VHSIC, which is more efficient and cost effective. In ALU, addition takes so much time if it uses the ripple-carry
adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that
use this principle are called CLA. The CLA is to be designed with combination of 4-bit adders.
KEY WORDS: VHDL, Designing, Simulation

1. INTRODUCTION
Arithmetic operations such as addition, subtraction, multiplication and division are mostly used and various
digital systems such as digital signal processor (DSP) architecture, microprocessor and microcontroller and
data process unit play an important role. Adders are the logic circuits designed to perform high speed
arithmetic operations and are important circuits in digital systems. In electronic devices like computers and
other kinds of processors, adders are used ALU and other parts of the processor, where they are used to
calculate addresses, table indices, and other kind of operations. The very basic arithmetic operation is the
addition of two binary digits, i.e. bits. A combinational circuit that adds two bits according the scheme is
called a half adder. A full adder that can add three bits, the third bit produced from a previous addition
operation i.e. carry coming from lower order bits. Addition is a fundamental arithmetic operation that is used
in many VLSI design systems like DSP architecture, microprocessor, microcontroller and data process unit.
This VLSI system requires fast addition which impacts the overall performance of digital system. These
addition operations are done by using adders.

2. METHODOLOGY
Strategy for designing fast adders is to reduce the time required to form carry signals. In this Paper first
approach is to compute the input carry needed by stage i directly from carry like signals obtained from all the
preceding stages i-1,i-2,……0, rather than waiting for normal carries to ripple slowly from stages to stages.
carry look-ahead adders use this principle . if n-bit carry look-ahead adder has n stages , each of which is
basically a full adder modified by replacing its carry output line ci by two auxiliary signals called generate(Gi)
and propagate (Pi) ,which are defined by the logic equation
(1); Gi = Xi AND Yi Pi = Xi XOR Yi (1)
These name generate from the fact that stage i generates a carry of 1(Ci=1) independent of the value of Ci-1 if
both Xi and Yi are 1; that is, if Xi .Yi=1.Stage i propagates Ci-1; that is makes Ci=1 in response to Ci-1=1 if
Xi or Yi is 1, in order words, if Xi + Yi=1. Now the usual equation for the sum & the carry are as follows:
Si = Pi XOR Ci-1 , Ci =Gi + PiCi-1 (2)
denoting the carry signal Ci to be sent to stage i+1,Similarly, Ci-1 can be expressed in terms of Gi-1, Pi-1 and
Ci-1, Ci-1 = Gi-1 + Pi-1Ci-2 (3)
On substituting Equation (3) into Equation (2),

44 Deepti Rajput
 International Journal of Electronics, Electrical and Computational System
IJEECS
ISSN 2348-117X
Volume 5, Issue 12
December 2016

Ci = Gi + PiGi-1+PiPi-1Ci-2 (4)
Continuing in this way, ci can be expressed as a sum-of-products function of the P and G outputs of all the
preceding stages. For example, the carries in a four-stage carry look-ahead adder are defined as follows:
C0 = G0 + P0.Cin
C1 = G1 + P1.G0 + P1.P0.Cin
C2 = G2 + P2.G1 + P2.P1.G0 +P2.P1.P0.Cin
C3 = G3 + P3.G2 + P3.P2.G1 + P3P2.P1.G0 + P3P2.P1.P0.Cin (5)
Carry look-ahead adder's structure can be divided into three parts: the propagate/generate generator, the sum
generator, carry generator. The architecture of 4-bit Carry Look-Ahead adder is shown in Fig. 1

Fig. 1: 4-bit Carry Look Ahead Adder

3. RESULT & DISCUSSION

3.1 EXPANSION OF ADDER
The Way of handling carry signals in the two main combinational adder designs considered namely ripple
carry propagation and carry look-ahead Fig. 1 can be extended to larger adders of the kind needed to execute
add instructions in a 64-bit computer. If the n 1-bit (full) adder’s stages are replaced in the n-bit ripple-carry
design with n k-bit adders, than nk-bit adder can be obtained. Sixteen 4-bit adders such as the 4-bit carry look-
ahead circuit of Fig. 1 can be connected in this way to form the 64-bit adder obtained. This design represents a
compromise between a 64-bit stage ripple-carry adder, which is cheap but slow, and a single-stage 64-bit
carry look-ahead adder, which is fast and expensive. The circuit of Fig.1 effectively combines sets of sixteen
xi & yi inputs into groups that are adder via carry look-ahead; the results computed in many groups are then
linked via ripple carries [4].The components are designed for 1-bit addition have been replaced with similar
but larger components intended for 4-bit addition. So 1-bit adders replaced with 4-bit adder , but now each
adder stage produces a propagate-generate signal pair PG instead of Cout and a carry look-ahead generator
converts the four sets of PG signals to the carry inputs required by the four stages. The “group” G and P
signals produced by each 4-bit stage are defined as:
G = xi.yi + xi-1.y i-1(x i + y i) + x i-2 .yi-2(xi + yi) (x i-1 + y i-1) + x i-3 .y i-3(xi + yi) (x i-1 + y i-1) (x i-2 +
y i-2) (6)
P = (xi +yi) (x i-1 + y i-1) (x i-2 +y i-2) (x i-3 + y i-3) (7)

45 Deepti Rajput
 International Journal of Electronics, Electrical and Computational System
IJEECS
ISSN 2348-117X
Volume 5, Issue 12
December 2016

It is not compulsory to show that the logic to generate the group carry signals Cout, C59, C55, C51, C47, C43,
C39, C35, C31, C27, C23, C19, C15, C11, C7 and C3 in Fig. 2 is exactly the same as that of the carry look-
ahead generator of Fig. 1.
3.2 DESIGNING OF 64 BIT ADDER
The main Objective is to minimize the number of gates & the speed of operation. The Device is required to
handle different data word sizes, including 4, 8, 16, 32 and 64. The lowest cost adders employ ripple-carry
propagation. Sixteen 4-bit CLAs are interconnected as ripple adder form as shown in the fig.2, here the carry
is propagated to the next stage 4-bit CLA. The internal carry propagation delay of 4-bit adder is reduced by
using the technique CLA. So that the overall speed of the 64-bit adder is increased.. So that the sum delays as
well as the carry delay is very much improved. For faster Full adders designs VHDL can be used to reduce
design time and speed.

Fig. 2: 64-Bit Composed of 4-Bit Adders Linked by Ripple Carry Propagation

3.3 VHDL CODE FOR 64 BIT CLA

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity carry_ahead is
Port
( a_in : in std_logic_vector (63 downto 0);
b_in : in std_logic_vector (63 downto 0);
c_in : in std_logic ;

46 Deepti Rajput
 International Journal of Electronics, Electrical and Computational System
IJEECS
ISSN 2348-117X
Volume 5, Issue 12
December 2016

sum : out std_logic_vector (63 downto 0);

c_out : out std_logic);
end carry_ahead;
architecture Behavioral of carry_ahead is
SIGNAL h_sum : std_logic_vector (63 downto 0);
SIGNAL c_in_internal : std_logic_vector(63 downto 0);
SIGNAL c_generate : std_logic_vector (63 downto 0);
SIGNAL c_propagate : std_logic_vector (63 downto 0);
begin
h_sum <= a_in XOR b_in;
c_generate <= a_in AND b_in;
c_propagate <= a_in XOR b_in;
PROCESS (c_generate,c_propagate,c_in_internal)
BEGIN
c_in_internal(1) <= c_generate(0) OR (c_propagate(0) AND c_in) ;
inst: FOR i IN 1 TO (63) LOOP
c_in_internal(i) <= c_generate (i-1) OR (c_propagate (i-1) AND c_in_internal (i-1));
end LOOP;
c_out <= c_generate (63) OR (c_propagate(63) AND c_in_internal(63));
end PROCESS;
sum(0) <= h_sum(0) XOR c_in ;
sum(63 downto 1) <= h_sum(63 downto 1) XOR c_in_internal(63 downto 1);
end Behavioral;

Fig. 3.1: Simulation Result after running of Coding

47 Deepti Rajput
 International Journal of Electronics, Electrical and Computational System
IJEECS
ISSN 2348-117X
Volume 5, Issue 12
December 2016

Fig. 3.2: Simulation Result after running of Coding

Fig. 3.3: RTL Schematic Diagram of 64 bit Carry Look Ahead Adder

48 Deepti Rajput
 International Journal of Electronics, Electrical and Computational System
IJEECS
ISSN 2348-117X
Volume 5, Issue 12
December 2016

4. ADVANTAGES AND DISADVANTAGES

1. Fast adders have the advantage to scale better with increasing word widths
2. CLA occupies less area as compare to RCA.
3. The CLA has the fastest growing area and power requirements with respect to the bit size.
4. The disadvantage of carry look- ahead is that the carry logic for any circuit larger than 4-bit is getting
quite complicated for more than 4-bits.
5. Carry look-ahead adders are usually implemented as 4-bit modules and are used in a hierarchical structure
to realize adders that have multiples of 4-bits.

5. CONCLUSION
The first stage of the adder block is getting input data, which is 4-bit wide. After each stages of the adder
block some extra bits are added because of the overflow. The final adder stage can give output data of 64-bit
wide. The general approach to design fast adders is to overcome the time form carry signals. This type of
adders are called carry look-ahead adder. The carry look-ahead is a fast adder but extremely large, especially
when the operands are big The faster path is paved by two signals, generate and propagate. The former creates
a carry regardless of the carry input, and the other passes a carry along.

6. REFERENCES
1. May Phyo Thwal, Khin Htay Kyi, and Kyaw Swar Soe, Implementation of Adder-Subtractor Design with
VerilogHDL, World Academy of Science, Engineering and Technology International Journal of Computer,
Electrical, Automation, Control and Information Engineering Vol:2, No:3, 2008
2. M. Morris Mano, Michael D. Ciletti, Digital Design, Pearson 4th ed., 2008.
3. K. Ramu, B.N. Srinivasa Rao A I E T., Visakhapatnam, A I E T., Visakhapatnam, Implementation of Area Efficient
16bit Adder in SPARTAN-3 FPGA, International Journal of Engineering Science and Innovative Technology
(IJESIT) Volume 2, Issue 2, March 2013.
4. Rajender Kumar, Sandeep Dahiya, SES, BPSMV, Khanpur Kalan, Gohana, Sonipat, Haryana, Performance Analysis
of Different Bit Carry Look Ahead Adder Using VHDL Environment, International Journal of Engineering Science
and Innovative Technology (IJESIT) Volume 2, Issue 4, July 2013.

49 Deepti Rajput