3D integrated circuits 2019-20

TECHNICAL SEMINAR REPORT

ON
“3D INTEGRATED CIRCUITS”
(Subject Code:
15ECS86)

Submitted to

VISVESVARAYA TECHNOLOGICAL UNIVERSITY

“Jnana sangama”, Belagavi-590018
In partial fulfillment of the
requirement for award of the degree
of BACHELOR OF ENGINEERING
In
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted By
ROHIT H
1MJ16EC093
Under the Guidance of
DR. ARUN ANANTHA NARAYAN
Assistant Professor,
Department of ECE, MVJ
College of Engineering,
Bangalore -67 carried out at

AN AUTONOMOUS
INSTITUTE
Permanently Affiliated to
VTU, Belagavi Approved
by AICTE, New Delhi
Recognized by UGC
under 2(f) & 12(B)
Accredited by NBA &
NAAC
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
MVJCE, Bengaluru,
Karnataka-560067

Department of Electronics and communication Engineering, MVJCE, Bangalore 1

 3D integrated circuits 2019-20

MVJ COLLEGE OF ENGINEERING

Near ITPB, Channasandra,
Bangalore, Karnataka 560067
(Affiliated to VTU, approved by AICTE and accredited by NBA and NAAC)

DEPARTMENT OF ELECTRONICS & COMMUNICATION

ENGINEERING
CERTIFICATE
This is to certify that the technical seminar work entitled “3D integrated circuits”, is a bonafide
work carried out by, ROHIT H (USN:1MJ16EC093), In partial fulfillment for the award of degree
of Bachelor of Engineering in ELECTRONICS AND COMMUNICATION ENGINEERING
of the VISVESVARAYA TECHNOLOGICAL UNIVERSITY, Belagavi, during the year 2019-
2020. It is certified that all corrections/suggestions indicated for Internal Assessment have been
incorporated in the Report deposited in the Departmental library. The Final Report has been
approved as it satisfies the academic requirements in respect of Research work prescribed for the
said Degree.

-------------------------------- ---------------------------------- ----------------------------------

Dr. I. Hameem Shanavas

Dr. Arun Anantha Narayan Associate professor & HOD Dr. P. Mahabaleshwarappa
Assistant Professor Department of ECE PRINCIPAL
Department of ECE, MVJ College of Engineering
Bangalore MVJ College of Engineering
MVJ College of Engineering Bangalore
Bangalore External Viva-voce

Name of the Examiners Signature with Date

Examiner 1.

Examiner 2.
Department of Electronics and communication Engineering, MVJCE, Bangalore 2
3D integrated circuits 2019-20

MVJ COLLEGE OF ENGINEERING

Near ITPB, Channasandra,
Bangalore, Karnataka 560067
(Affiliated to VTU, approved by AICTE and accredited by NBA and NAAC)

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
DECLARATION
I ROHIT H (USN:1MJ16EC093),Student of B.E.., Department of Electronics &
Communication Engineering of M.V.J College of Engineering, Bangalore hereby declare that the
technical seminar work entitled “3D integrated circuits”, embodies the seminar work which is
carried out. This work has been submitted for the partial fulfillment of the UG degree course of
VISVESVARAYA TECHNOLOGICAL UNIVERSITY, Belagavi.

I, also hereby declare that to the best of my knowledge and belief, the work reported here does
not form part of any other thesis or dissertation on the basis of which degree or award was
conferred on an earlier occasion on this by any student Declaration.

STUDENT NAME Signature with Date

Department of Electronics and communication Engineering, MVJCE, Bangalore 3

3D Integrated Circuits 2019-20

ACKNOWLEDGEMENT

The success and final outcome of this technical seminar required a lot of guidance
and assistance from many people and we are extremely privileged to have got this all
along the completion of our project. All that we have done is only due to such
supervision and assistance and we would not forget to thank them.

I heartily thank our internal project guide Dr. Arun Anantha Narayan, Asst.
Professor, ECE Dept. for his guidance, suggestions and encouragement till the
completion of the project work.

I am thankful to and fortunate enough to get constant encouragement, support and

guidance from Dr. Hameem Shanavas, HOD, ECE Dept., and Dr. P
Mahabaleshwarappa, Principal, MVJCE which helped us in successfully completing
our project work

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 4
3D Integrated Circuits 2019-20

ABSTRACT

The report entitled “3D Integrated Circuits” which focuses on the key potential applications
of 3D ICs that have the most impact in terms of performance, power and area are
highlighted, followed by a brief overview of the different technology approaches to
implement 3D ICs. Further, the key challenges to 3D integration are discussed here. The
unprecedented growth of the computer and the Information technology industry is
demanding Very Large Scale Integrated (VLSI) circuits with increasing functionality and
performance at minimum cost and power dissipation. VLSI circuits are being aggressively
scaled to meet this Demand, which in turn has some serious problems for the semiconductor
industry. Additionally heterogeneous integration of different technologies in one single
chip (SoC) is becoming increasingly desirable, for which planar (2-D) ICs may not be
suitable. 3-D ICs are an attractive chip architecture that can alleviate the interconnect
related problems such as delay and power dissipation and can also facilitate integration of
heterogeneous technologies in one chip (SoC). The multi-layer chip industry opens up a
whole new world of design. With the Introduction of 3-D ICs, the world of chips may never
look the same again.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 5
3D Integrated Circuits 2019-20

CONTENTS

Page No.
CERTIFICATE
ACKNOWLEDGEMENT
ABSTRACT
1. Introduction 9
2. Typical Architecture for 3D Integration
2.1 Silicon Interposer (2.5D)
2.2 Stacked memory
10-12
2.3 Memory on processor
2.4 Logic on Logic
2.5 Heterogeneous Integration
3. Fabrication Methods
3.1 Beam Recrystallization
3.2 Silicon Epitaxial Growth 13-15
3.3 Processed wafer bonding
3.4 Solid phase crystallization (SPC)
4. 3D IC Technologies
4.1 Back to Back bonded 3D ICs
4.1.1 Via-First
4.1.2 Via-Last 16-18
4.1.3 Via-Middle
4.2 Face-to-Face bonding with micro pillars
4.3 Monolithic 3D ICs
5. Benefits of 3D integrated circuits
5.1 Power
5.2 Noise
5.3 Logical span 19-22
5.4 Density
5.5 Performance
5.6 Functionality

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 6
3D Integrated Circuits 2019-20
6. Key Challenges for 3D Integration
6.1 Heat Removal
6.2 IC Testing and Yield 23-24
6.3 Reliability
6.4 Power Delivery
7. Applications 25
8. Present scenario of the 3D IC Industry 26-27
9. Future of the 3D IC Industry 28
10. Conclusion 29
11. Reference 30-31

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 7
3D Integrated Circuits 2019-20

LIST OF FIGURES

Figure No. Title Page No.

2.5D IC/SIP using a silicon interposer and through-silicon vias
2.1 10
(TSVs).
Stacked Memory. (a) High Bandwidth Memory (HBM) and (b)
2.2 11
Hybrid Memory Cube (HMC).
3.1 Beam Recrystallization 13
3.2 Silicon Epitaxial Growth 14
4.1 Back to Back bonded 3D ICs 16
4.2 Face-to-Face bonding with micro pillars. 18
Layout designs of the 2D and 3D inventers with fan-in equal to
5.4 20
1, showing large (30%) areal gain for the 3D case.
Relative performance for different numbers of stacked layers
vs. the pre-set total power in the process core, showing
5.5 21
performance increase as the square root of the number of layers
stacked.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 8
3D Integrated Circuits 2019-20

Chapter 1
INTRODUCTION

Riding high on the back of device scaling, the semiconductor industry has made
tremendous improvements in the performance, power, and cost of integrated circuits (ICs)
over the last five decades [1]. For the first few decades after the digital revolution in the
late 1960s, the semiconductor industry enjoyed a steady improvement in critical metrics
like performance, power, and area, in line with Moore’s law [2]. However, as the device
dimensions started shrinking and the demand for performance kept growing, traditional
scaling was not enough to keep up with Moore’s law [3]. Through numerous device and
interconnect innovations like the transition to on-chip copper interconnects, strained
silicon, High-k Metal Gate, FinFET, porous low-k dielectric [4] [5] [6] [7] [8], the
semiconductor industry has somehow found a way to boost performance. The effort to
improve chip performance is critical to maximizing the frequency of operation of
individual ICs, and reducing their power consumption. However, the performance of
individual ICs cannot be evaluated in isolation, but rather as of part of the system. For
example, as microprocessor operating frequencies keep increasing, the demand for data
from the main memory also increases. If the chip-to-chip links feeding data into the
processor do not keep up with the improving performance, then they start to limit the
overall system performance [9]. State of the art IO links are limited primarily by dielectric
and resistive losses in transmission lines [10]. 3D integration provides an elegant solution
to the off-chip interconnect problem by bringing the communicating ICs physically closer
to each other, while simultaneously reducing the area footprint, which is critically
important for handheld devices. Hence, 3D integration is considered to be a promising
technology to alleviate the off-chip interconnect problem [11].

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 9
3D Integrated Circuits 2019-20

Chapter 2
TYPICAL ARCHITECTURES FOR 3D
INTEGRATION

The most commonly studied architectures for 3D ICs are discussed here.

2.1 Silicon Interposer (2.5D)

Although technically not a true 3D architecture, silicon interposer, as shown in Fig. 2.1,
provides several advantages over conventional packages. First, very fine pitch wires,
similar to on-chip BEOL interconnects can be patterned on silicon interposers. Second, due
to the matched coefficient of thermal expansion between the chip and silicon interposer,
reliable fine pitch micro-bumps can be used as first level interconnect. As a result, silicon
interposers offer a significant bandwidth and energy improvement over conventional off-
chip interconnects [12] [13].

Fig. 2.1. 2.5D IC/SIP using a silicon interposer and through-silicon vias (TSVs).

2.2 Stacked Memory

Multiple DRAM die are stacked on top of each other, with one logic die at the bottom for
control. The memory stack significantly increases the capacity that can be fit in a given
area, whereas the logic die handles communication with other ICs on the interposer. The
two prominent memory architectures for stacked memory are High Bandwidth Memory
(HBM), as shown in Fig. 2.2(a), and Hybrid Memory Cube (HMC) from Micron, as shown
in Fig. 2.2(b) [14] [15].

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 10
3D Integrated Circuits 2019-20

(a) (b)

Fig. 2.2. Stacked Memory. (a) High Bandwidth Memory (HBM) and (b) Hybrid Memory
Cube (HMC).

2.3 Memory on Processor

The ability to stack high density DRAM on top of the processor is extremely valuable for
several applications. By minimizing the physical distance between the two communicating
ICs, the losses in the chip-to-chip link can be minimized. Additionally, since Through
Silicon Vias (TSVs) can be densely packed to provide a large bus width, the data rate for
operation can be reduced significantly compared to the conventional IO links that typically
operate at tens of GHz. This, in turn simplifies the IO circuits considerably and minimizes
the issues that creep up at higher frequencies.

2.4 Logic on Logic

The motivation for stacking logic on logic is to reduce the aggregate interconnect length in
a large logic circuit. For example, if a large 2D chip like a microprocessor is 2cm 2cm in
dimensions, the overall interconnect length can be reduced significantly if the
microprocessor is partitioned into 4 blocks of 1cm 1cm stacked on top of each other and
connected with TSVs. However, the caveat here is that the communication between the 4
partitions should be limited.

2.5 Heterogeneous Integration

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 11
3D Integrated Circuits 2019-20
This is the ultimate holy grail of researchers seeking to integrate multiple technologies
stacked together in a single package. The dream is to one day combine logic, memory, RF,
sensor ICs built separately in the optimal technology within a package. There are several
advantages to such a heterogeneous 3D IC including cost, form factor, performance, IO
count reduction, and lower power consumption.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 12
3D Integrated Circuits 2019-20

Chapter 3
FABRICATION METHODS

3.1 Beam Recrystallization

Beam Recrystallization as shown in the Fig. 3.1, is a very popular method of fabricating a
second active layer (Si) on top of an existing substrate (oxidized Si wafer) is to deposit
polysilicon and fabricate thin film transistors (TFT). To enhance the performance of such
transistors, an intense laser or electron beam is used to induce recrystallization of the
polysilicon film to reduce or even eliminate most of the grain boundaries.

Fig. 3.1 Beam Recrystallization

Advantages
1. MOS on transistors fabricated on polysilicon exhibit very low surface mobility values [of
the order of 10 cm/Vs].

2. MOS transistors fabricated on polysilicon have high threshold voltages (several

volts) due to the high density of surface states (several 10 cm ) present at the grain
boundaries.

Disadvantages
Department of Electronics and communication Engineering, MVJCE, Bangalore
Page 13
3D Integrated Circuits 2019-20
1. This technique, however, may not be very practical for 3-D devices because of the
high temperature involved during melting of the polysilicon.

2. Difficulty in controlling the grain size variations.

3.2 Silicon Epitaxial Growth

Silicon Epitaxial Growth as shown in the Fig. 3.2, is a technique for forming additional Si
layers is to etch a hole in a passivated wafer and epitaxially grow a single crystal Si seeded
from open window in the ILD. The Si crystal grows vertically and then laterally to cover
the ILD.

Fig. 3.2. Silicon Epitaxial Growth

Advantages
1. The quality of devices fabricated on these epitaxial layer can be as good as those
fabricated underneath on the seed wafer surface, since the grown layer is single
crystal with few defects.

Disadvantages
1. The high temperatures involved in this process cause significant degradation in the
quality of devices on lower layers.

3.3 Processed Wafer Bonding

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 14
3D Integrated Circuits 2019-20
An attractive alternative is to bond two fully processed wafers on which devices are
fabricated on the surface, including some interconnects, such that the wafers completely
overlap. Interchip vias are etched to electrically connect both wafers after metallization and
prior to the bonding process at 400 degree Celsius. For applications where each chip is
required to perform independent processing before communicating with its neighbor, this
technology can prove attractive.

Advantages
1. Devices on all active levels have similar electrical properties.

2. Since all chips can be fabricated separately and later bonded, there is independence of
processing temperature.

Disadvantages
1. The lack of precision restricts the interchip communication to global metal lines.

3.4 Solid Phase Crystallization (SPC)

In this technique, a layer of amorphous Si is crystallized on top of the lower active layer
devices. The amorphous film is randomly crystallized to form a polysilicon film. Device
performance can be enhanced by eliminating the grain boundaries in the polysilicon film.
For this purpose, local crystallization can be induced using low temperatures processes
(<600C) such as using patterned seeding of germanium. In this method, Ge seeds implanted
in narrow patterns made on amorphous Si can be used to include lateral crystallization.
This results in the formation of small islands, which are nearly single crystal. CMOS
transistors can then be fabricated within these islands to give SOI like performance.

Advantages
1. This technique offers flexibility of creating multiple active layers.
2. This is a low temperature technique.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 15
3D Integrated Circuits 2019-20

Chapter 4
3D IC TECHNOLOGIES

Although 3D integration is a promising new technology with a significant number of

potential applications, it is clear that 3D integration is not trivial to implement. There are
several technology options to choose from, some of which are highlighted in this section.

4.1 Back to Back bonded 3D ICs

Through silicon via is the most important component required to enable 3D integration.
TSVs are fabricated using the Bosch process, which is a two-step process including plasma
etch and deposition of passivation layer, repeated multiple times to etch deep via holes. The
barrier material is then deposited followed by the electroplating copper to form the TSVs.
In order to reduce the TSV height and hence minimize parasitics, the wafer needs to be
thinned down significantly. Further, since the TSV fabrication is typically limited to an
aspect ratio of ~20, the minimum TSV diameter is also determined by the TSV height.
Thus, the TSV parasitics effectively have a quadratic dependence on the TSV height. The
following three approaches to fabricating back-to-back bonded 3D ICs, as shown in the
Fig. 4.1, have been adopted by the industry:

Fig. 4.1. Back to Back bonded 3D ICs

4.1.1 Via-First
The TSVs are fabricated before the wafer is taken through any FEOL or BEOL process.
Since the TSVs are fabricated at the beginning, via holes can be etched and filled from the
front side, and wafer thinning can be done at the end to expose TSVs from the backside.
The advantage is that TSV processing will not inadvertantly damage any of the devices or
interconnects. However, the disadvantage of this approach is that the TSV has to be taken
through the high temperature processing steps for FEOL and BEOL processing. The
Department of Electronics and communication Engineering, MVJCE, Bangalore
Page 16
3D Integrated Circuits 2019-20
mismatch of Coefficient of Thermal Efficient (CTE) between copper and silicon results in
stress being introduced in the silicon substrate. As a result, transistor performance and
reliability are significantly compromised.

4.1.2 Via-Last
The TSVs are fabricated at the end, after all the FEOL and BEOL processing is completed.
Since the FEOL and BEOL processing are done prior to TSV etching, TSVs need to be
etched from the back side after wafer thinning. This process is very attractive from a CTE
standpoint, since the TSVs don’t have to endure high temperature processing. However,
the key challenges with this approach include designing robust and reliable TSV contacts
with lower level on-chip interconnect, and ensuring that the TSV etch stops at the right
depth without damaging or degrading the reliability of the lower BEOL layers/ILDs [16].

4.1.3 Via-Middle
This approach combines the best of both worlds - TSVs are processed after FEOL
processing, but before the BEOL processing. This prevents the TSVs suffering through the
high temperature FEOL processing, but improves the TSV contact and BEOL/ILD
reliability compared to the via-last process. This approach is popular with many companies
in the industry [17].

4.2 Face-to-Face Bonding with micro pillars.

This approach is very popular for 3D ICs with two ICs in the stack. The two ICs stacked
together in a 3D IC can communicate with each other through fine-pitch micro-pillars
connecting the pads of one chip to the other. The integrated 3D IC communicates with the
external world through TSVs through the bottom die. The advantage of Face-to-Face
Bonding with micro pillars, as shown in the Fig. 4.2, is that the parasitics for the chip to
chip link are minimized by using micro-pillars, but the technology is useful mainly for two-
stack 3D ICs.

Fig. 4.2. Face-to-Face bonding with micro pillars.

Department of Electronics and communication Engineering, MVJCE, Bangalore
Page 17
3D Integrated Circuits 2019-20

4.3 Monolithic 3D ICs

Monolithic 3D ICs are theoretically one of the most attractive options available because
they would allow for very short and fine-pitch vias, thus reducing the interconnect
parasitics considerably. Monolithic 3D ICs have the potential to make seamless
communication between the different layers of the 3D IC a reality. However, the high
temperature FEOL processing of the second Si layer is expected to melt the BEOL
processed for the first layer. Thus, the research in this area is headed towards low
temperature FEOL processing. Another approach to stack logic on logic is to manufacture
NMOS transistors on the bottom layer and PMOS on the top layer. However, the TSVs
connecting NMOS and PMOS to form logic gates need to have extremely fine pitches in
order to minimize parasitic loading on logic gates.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 18
3D Integrated Circuits 2019-20

Chapter 5
BENEFITS OF 3D INTEGRATED CIRCUITS

One of several promising solutions being explored is the 3D integration and packaging
technology (also known as vertical integration), in which multiple layers of active devices
are stacked with vertical interconnections between the layers to form 3D integrated circuits
(ICs). Later sections present a detailed description of this technology. Even in the absence
of continued device scaling, 3D ICs provide potential performance advances, since each
transistor in a 3D IC can access a greater number of nearest neighbors, and each circuit
functional block has higher bandwidth. Other benefits of 3D ICs include improved packing
density, noise immunity, improved total power due to reduced wire length/lower
capacitance, superior performance, and the ability to implement added functionality. These
features are described in more detail in the following sections.

5.1 Power
Initial analyses of investigated 3D wire-length reduction showed that 3D integration indeed
provides a smaller wire-length distribution, with the largest effect associated with the
longest paths. These shorter wires will decrease the average load capacitance and resistance
and decrease the number of repeaters needed for long wires. Since interconnect wires with
their supporting repeaters consume a significant portion of total active power, the reduced
average interconnect length in 3D IC, compared with that of 2D counterparts, will improve
the wire efficiency (~15%) and significantly reduce total active power by more than 10%.

5.2 Noise
The shorter interconnects and consequent reduction of load capacitance in 3D ICs will
reduce the noise due to simultaneous switching events. The shorter wires will also have
lower wire-to-wire capacitance, resulting in less noise coupling between signal lines. The
shorter global wires with reduced numbers of repeaters should also have less noise and less
jitter, providing better signal integrity.
Department of Electronics and communication Engineering, MVJCE, Bangalore
Page 19
3D Integrated Circuits 2019-20

5.3 Logical span

Because MOSFET fan-out is limited to a fixed amount of capacitive gain per cycle, the
increasing intrinsic gate load is significantly constrained by extrinsic load capacitance
(wires). Since 3D IC provides a lower wiring load, it makes it possible to drive a greater
number of logic gates (fan-out).

5.4 Density
In three dimensions, active devices can be stacked and the size of a chip footprint can be
reduced. This added dimension to the conventional two-dimensional device layout
improves the transistor packing density, since circuit components can be stacked on top of
each other, as in Fig. 5.4, where an n-FET is placed over a p-FET. When the total layout
area (the sum of the device area and the metal routing area) is compared for 2D and 3D
standard cells with different inverter designs, a 30% areal benefit for the 3D cells can be
achieved. The ability to stack circuit elements, thus shrinking the footprint and potentially
reducing the volume and/or weight of a chip, is of great interest for wireless, portable
electronics, and military applications. Higher-density and hence higher-speed SRAM
circuits can also be created. For example, the pull-up p-MOS devices could be stacked over
the n-MOS in a 3D approach to save device area. However, since metal routing occupies a
large portion of the total layout area, the total cell area reduction will depend strongly on
the chip architecture and the metal routing design. Successful stacked CMOS SRAM cell
technology has been reported, but its extendibility is limited by extremely tight alignment
tolerance requirements for interlayer contacts.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 20
3D Integrated Circuits 2019-20
Fig. 5.4. Layout designs of the 2D and 3D inventers with fan-in equal to 1, showing large
(30%) areal gain for the 3D case.

5.5 Performance
3D technology enables the memory arrays to be placed above or under logic circuitry,
resulting in an increased bandwidth and thus a significant performance gain in
communication between memory and microprocessor. In particular, as the amount of on-
chip memory increases (i.e., the majority of the chip will soon be occupied by memory),
the latency of the path from logic to memory becomes a limiting factor in the logic-memory
system. The ability to stack logic and memory has been demonstrated. In addition, one can
determine maximum system performance as a function of the number of device layers.
Maximum performance depends on power dissipation constraints. In the presence of power
constraints, there are global technology scaling optima that yield maximum computation
(for example, if devices are scaled too far, leakage consumes too much of the power).
Simple models of device and system dependencies have been developed, and optimizations
have been performed. These layering models ignore the impact of blockage due to signals
passing through a device layer. As depicted in Fig. 5.5, the results show significant potential
advantage for 3D integration, with performance increasing roughly as the square root of
the number of circuit layers that are stacked. For these data points, device characteristics
(such as Vdd, VT, tox, gate length, mean FET width, wire half-pitch, and repeater spacing)
have all been optimized for maximum performance, where performance is calculated as
Performance ¼ total number of logic switching events per second in a processor core.

Fig. 5.5. Relative performance for different numbers of stacked layers vs. the pre-set total
power in the process core, showing performance increase as the square root of the number
of layers stacked.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 21
3D Integrated Circuits 2019-20

5.6 Functionality
3D integration will allow the incorporation of new elements that are currently prohibited
by conventional planar technology; it will enable the implementation of related design
flexibility, including new system architectures. Its primary application is the combination
of dissimilar technologies (memory, logic with extension to rf, analog, optical, and
microelectromechanical systems) to create hybrid circuits.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 22
3D Integrated Circuits 2019-20

Chapter 6
KEY CHALLENGES FOR 3D INTEGRATION

Given all the potential benefits of 3D integration, it is essential to understand the key
challenges that are holding the technology back from completely disrupting the
semiconductor industry. The most critical challenges to the widespread adoption of 3D
integration are discussed here.

6.1 Heat Removal

The performance of modern electronic chips is primarily limited by their power
consumption, and the effectiveness of the cooling systems. 3D integration makes heat
removal harder because the hotspots on the die farther away from the heat sink are not
easily accessible. Liquid cooling through microfluidic channels is a promising new
technology that can alleviate the problem, but its robustness and reliability are yet to be
proven in the industry.

6.2 IC Testing and Yield

Another crucial challenge that impedes the widespread adoption of 3D ICs is the problem
of testing them. Although it 2017 IEEE MTT-S International Conference on Numerical
Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and
Terahertz Applications (NEMO) is desirable that only the Known Good Die (KGD) are
handpicked from wafer level testing and stacked with other KGD to form different layers
of a 3D IC, it is extremely expensive to assemble 3D ICs at the die level. On the other hand,
wafer level assembly is cheaper but leads to a significant yield loss because a single
malfunctioning die in the stack renders the entire 3D IC useless.

6.3 Reliability
Depending on the process used for TSV fabrication, the reliability of transistors or
interconnects on the chip can be severely impacted. If via-middle process is used, TSVs
Department of Electronics and communication Engineering, MVJCE, Bangalore
Page 23
3D Integrated Circuits 2019-20
have to go through high temperature BEOL processing, resulting in a stress profile that
could degrade transistor performance and reliability over time. On the other hand, if via-
last process is used, TSV etch can potentially damage the already fabricated BEOL wiring
and the ILD layers. In order to minimize the impact of TSVs on transistor/interconnect
performance and reliability, designers pay a heavy price with additional guardbands like
using larger Keep Out Zones (KOZ) for transistors and creating routing blockages for more
interconnect layers. It was shown in [,] that reliability of on-chip wires connecting I/Os to
TSVs is critical to the operation of these 3D ICs, and it could determine the upper bound
on the performance of 3D ICs.

6.4 Power Delivery

Power is delivered to die higher up in the stack through power/ground TSVs that need to
be distributed over the area of the die. Since the performance of each die in the 3D IC is a
strong function of the IR drop, a significant number of TSVs need to be dedicated to
power/ground TSVs. Unlike the die closest to the C4 bumps, the power TSVs on the other
die cannot be distributed all over the area of the chip, and are governed by industry
standards. As a result, improving the internal power grid within the upper layer die of 3D
ICs is essential to maintain performance.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 24
3D Integrated Circuits 2019-20

Chapter 7
APPLICATIONS

Portable electronic digital cameras, digital audio players, PDAs, smart cellular phones,
and handheld gaming devices are among the fastest growing technology market for both
business and consumers. To date, one of the largest constraints to growth has been
affordable storage, creating the marketing opportunity for ultra-low cost internal and
external memory. These applications share characters beyond rapid market growth.
Portable devices all require small form factors, battery efficiency, robustness, and
reliability. Both the devices and consumable media are extremely price sensitive with high
volumes coming only with the ability to hit low price points. Device designers often trade
application richness to meet tight cost targets. Existing mask ROM and NAND flash
nonvolatile technology force designers and product planners to make the difficult choice
between low cost or field programmability and flexibility. Consumers value the
convenience and ease of views of readily available low cost storage. The potential to
dramatically lower the cost of digital storage weapons many more markets than those listed
above. Manufacturers of memory driven devices can now reach price points previously
inaccessible and develop richer, easier to use products.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 25
3D Integrated Circuits 2019-20

Chapter 8
PRESENT SCENARIO OF THE 3-D IC INDUSTRY

Many companies are working on the 3-D chips, including groups at Massachusetts institute
of technology (MIT), international business machines (IBM). Rensselar Polytechnic and
SUNY Albany are also doing research on techniques for bonding conventional chips
together to form multiple layers .whichever approach ultimately wins ,the multilayer chip
building technology opens up a whole new world of design .

However ,the Santa Clara, California US based startup company matrix semiconductor
will bring the first multilayer chip to the market ,while matrix’s techniques will not likely
result in more computing power ,they will produce cheaper chips for certain applications,
like memory used in digital cameras , personal digital assistants ,cellular phones ,hand held
gaming devices ,etc. Matrix has adapted the technology developed for making flat –panel
liquid crystal displays to build chips with multilayer of circuitry.

The company’s first products will be memory chips called 3-Dmemory, for consumer
electronics like digital cameras and audio players. Current flash memory cards for such
devices are rewritable but expensive .however the newly produced chips will cost ten times
less, about as much as an audio tape or a roll of film, but will only record information once.
The cost is so largely because the stacked chips contain the same amount of circuitry as
flash cards but use a much smaller area of the extremely expensive silicon wafers that form
the basis for all silicon chips. The chips will also offer a permanent record of the images
and sounds users record. The amount of computing power the company can ultimately
build in to its chips could be limited .the company hopes to eventually build chips for cell
phones, or low performance microprocessors like those found in appliances; such chips
would be about one tenth as expensive as current ones.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 26
3D Integrated Circuits 2019-20
The patent technology opens up the ability to build ICs in three dimensions- “up” as well
as “out” in the horizontal directions as in the case now with conventional chip designs. The
result is a tenfold increase in the potential no of bits on a silicon die, according to the
company .moreover, the 3-D circuits can be produced with today’s standard semiconductor
materials, fab equipment’s and processors the 3-D memory will be used in memory devices
which will be marketed under well-known brand names for portable electronics devices,
including digital cameras digital audio players, games, PDAs and archival digital storage
.the 3-D memory can also be used for prerecorded content such as music, electronics books,
digital maps, games, and reference guides.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 27
3D Integrated Circuits 2019-20

Chapter 9
FUTURE OF THE 3-D IC INDUSTRY

Matrix is working with partners including Microsoft Corp, Thomas Multimedia, Eastman
Kodak and Sony Corp. three product categories are planned: bland memory cards: cards
sold preloaded with content, such as software or music ; and standard memory packages,
for using embedded applications such as PDAs and set-top boxes .
Thomson electronics, the European electronic giant, will begin to incorporate 3-D memory
chips from matrix semiconductor in portable storage cards, a strong endorsement for the
chip start –up.
Thomson multimedia will incorporate the 3-D memory in memory cards that can be used
to store digital photos or music. Although the cards plug into cameras Thomson is also
working on card readers that will allow consumers to view digital photos on a television.
The Thomson /matrix cards price makes the difference from completing flash cards from
Sony and Toshiba .the 64 MB Thomson card will cost about as much as camera film does
today. to further strengthen the relationship with film ,the cards will be sold under the name
Technicolor Digital Memory Card.
Similar flash memory cards from other companies cost around Rs.1900 or more-though
consumers can erase and rerecord data on them, unlike the matrix cards. As a result of
their price, consumers buy very few of them. Thomson, by contrast, expects to market its
write-once cards in retail outlet such as Wal-Mart.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 28
3D Integrated Circuits 2019-20

Chapter 10
CONCLUSION

The 3D memory will just the first of a new generation of dense, inexpensive chips that
promise to make digital recording media both cheap and convenient enough to replace the
photographic film and audio tape. We can understand that 3-D ICs are an attractive chip
architecture, that can alleviate the interconnect related problems such as delay and power
dissipation and can also facilitate integration of heterogeneous technologies in one chip.
The multilayer chip building technology opens up a whole new world of design like a city
skyline transformed by skyscrapers, the world of chips may never look at the same again.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 29
3D Integrated Circuits 2019-20

Chapter 11
REFERENCES

[1] R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous and A. R. LeBlanc, "Design

of ion-implanted MOSFET's with very small physical dimensions," IEEE Journal of Solid-
State Circuits, vol. 9, no. 5, pp. 256-268, 1974.
[2] G. Moore, "Cramming more components onto integrated circuits,” vol.38, April 1965.,"
Electronics, vol. 38, 1965.
[3] K. J. Kuhn, "Moore's Law Past 32nm: Future Challenges in Device Scaling," in
International Workshop on Computational Electronics, 2009.
[4] P. C. Andricacos, C. Uzoh, J. O. Dukovic, J. Horkans and H. Deligianni, "Damascene
copper electroplating for chip interconnections," IBM Journal of Research and
Development, vol. 42, no. 5, 1998.
[5] T. Ghani and e. al, "A 90nm high volume manufacturing logic technology featuring
novel 45nm gate length strained silicon CMOS transistors," in IEEE International Electron
Devices Meeting, 2003.
[6] K. Mistry and e. al, "A 45nm logic technology with high-k+ metal gate transistors,
strained silicon, 9 Cu interconnect layers, 193nm dry patterning,;100% Pb-free packaging,"
in IEEE International Electron Devices Meeting, 2007.
[7] D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson,
T.-J. King, J. Bokor and C. Hu, "FinFET-a self-aligned double-gate MOSFET scalable to
20 nm," IEEE Transactions on Electron Devices, vol. 47, no. 12, 2000.
[8] S. Natarajan and e. al, "A 14nm logic technology featuring 2 ndgeneration
FinFET, air-gapped interconnects, self-aligned double patterning;a 0.0588 um 2 SRAM
cell size," in IEEE Electron Device Meeting, 2014.
[9] B. M. Rogers, A. Krishna, G. B. Bell, K. Vu, X. Jiang and Y. Solihin, "Scaling the
bandwidth wall: challenges in and avenues for CMP scaling," in ACM SIGARCH Computer
Architecture News, 1998.
[10] H. Cho, P. Kapur and K. C. Saraswat, "Power comparison between highspeed
electrical;optical interconnects for interchip communication," Journal of Lightwave
Technology, vol. 22, no. 9, 2004.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 30
3D Integrated Circuits 2019-20
[11] J. U. Knickerbocker and e. al, "Three-dimensional silicon integration," IBM Journal
of Research and Development, vol. 52, no. 6, 2008.
[12] T. O. Dickson and e. al, "An 8x 10-Gb/s source-synchronous I/O system based on
high-density silicon carrier interconnects," IEEE Journal of Solid-State Circuits, vol. 47,
no. 4, 2012.
[13] R. Chaware, K. Nagarajan and S. Ramalingam, "Assembly and reliability challenges
in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer," in
Electronic Components and Technology Conference (ECTC), 2012.
[14] D. U. Lee and e. al, "25.2 A 1.2 V 8Gb 8-channel 128GB/s highbandwidth memory
(HBM) stacked DRAM with effective microbump I/O test methods using 29nm process
and TSV," in IEEE International Solid-State Circuits Conference, 2014.
[15] J. Jeddeloh and B. Keeth, "Hybrid memory cube new DRAM architecture increases
density;performance," in Symposium on VLSI Technology (VLSIT), 2012.
[16] M. Aoki, F. Furuta, K. Hozawa, Y. Hanaoka, H. Kikuchi, A. Yanagisawa, T.
Mitsuhashi and K. Takeda, "Fabricating 3D integrated CMOS devices by using wafer
stacking;via-last TSV technologies," in IEEE International Electron Devices Meeting,
2013.
[17] H. S. Kamineni, S. Kannan, R. Alapati, S. Thangaraju, D. Smith, D. Zhang and S. Gao,
"Challenges to via middle TSV integration at sub- 28nm nodes," in Interconnect
Technology Conference/Advanced Metallization Conference, 2014.

Department of Electronics and communication Engineering, MVJCE, Bangalore

Page 31