ECTE 212: Electronics

Lecture 1: Semiconductor Diodes & Applications

Dr. Le Chung Tran

Email: LCTRAN@UOW.EDU.AU
Room: 35.G32, Ext: 3846
Consultation:
Mondays 09.30–11.30 (via email)
Tuesdays 09.30–11.30 (face-to-face)
Students are advised to email for an appointment

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 About Me (1)
 1997: BE (1st Hons, Highest Distinction)
 2000: ME (1st Hons, Highest Distinction)
 2006: PhD (from UOW)
 1997-2002: Lecturer in Vietnam
 2002-2005: Part-time teaching academic at UOW
 2005-2006: Associate Research Fellow at UOW
 2006-2008: Post-doctor in Germany, Humboldt research
fellowship
 2015-2016: Humboldt research fellowship
 2009-date: Lecturer/Senior Lecturer at UOW
 22-year teaching experience

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 About Me (2)
 Awards: OCTAL 2019, WUS (twice), UPA,
University Tuition Fee Waiver, Humboldt fellowships
(twice), Vietnamese Government Scholarship

 Publications: 82 (1 book, 2 chapters, 31 journals, 48

conf papers).

 Expertise: PHY layer, e.g., OFDM, UWB, MIMO,

Space-time processing, signal processing for
wireless communications, WBANs, WPANs.

 Prof. activities: Lead Guest Editor, Editorial board

member, Track chair/session chair, TPC (Technical
Program Committee), journal & conf reviewer, PhD
thesis marker

 Web: http://www.uow.edu.au/~lctran/

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 How to contact me?
 Email (lctran@uow.edu.au) to book appointment

 Email etiquette: proper email title, including Subject code ECTE212

and Student ID

 Consultation time (also for other subjects):

Mondays 09.30am – 11.30am (via email),

Tuesdays 09.30am – 11.30am (face-to-face)

 Room: 35.G32

 Phone: 02 4221 3846

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 Timetable for Part A

Lecture Fri 8:30-10:30 (14.G01) Weeks: 1-6

Tutorials Fri 12:30-14:30 (24.102) Weeks: 1-6

Laboratory Neither Dr Peter Vial nor I does lab demonstration

Lab demonstrators and lab markers:

Mr Zeeshan, Mr Yani
Mr Zeeshan is in charge of marking lab reports.

Quiz 1 2nd half of the lecture time in Week 4

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 Textbook, References and Labs
[1] R. L. Boylestad and L. Nashelsky, Electronic Devices and Circuit Theory, 5th
Ed., Pearson International Edition, Upper Saddle River, New Jersey, USA,
2012 [Preferred for the 1st half]
[2] Sedra and Smith, Microelectronic Circuits, 6th Ed., Oxford University Press
[Preferred for the 2nd half].
• Students need to collect the (free) lab kit in Week 1 from Mr Brian 35.132A
(9pm-12.30pm and 1.30pm-3pm, working days). Bring your ID card.
• Make sure you visit the ECTE212 lab website
http://secte1.elec.uow.edu.au/electronicslab/ to do the prelab activities before
you come to every lab class.
• These activities will be marked (see subject outline), starting from Week 2
• Students will need to work in pairs in the lab classes.
• Most labs are at the maximum capacity, so ensure that you know the correct
lab you are scheduled for. Students should not attend other lab sessions which
are not your enrolled one.

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 Lab Regulations
• Must have a laboratory logbook to record pre-lab and post-lab work
– This is a hardcover, bound book with no loose sheets. A pile of papers is not
acceptable.

• Important:
– small vero board for Experiment 1
– big vero board for backup in case the small one is broken or if students want to
practise soldering further (e.g., in Experiment 5 - Lab Design)

• Reminders:
– do not take excessive wires from the lab rooms
– bread boards must NOT be removed from the lab rooms (other classes have to use)
– clean and tidy your bench, put the equipment back to where it is, make the bench
ready for the next class. A common practice is students complete experiments 5-10
mins before the time is up to clean the bench and tidy up equipment.
– if students want to buy a second-hand breadboard for their own possession, contact
Mr Brian Biehl (Store Room 35.132A).
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 Identify Labs

Lab website: http://secte1.elec.uow.edu.au/electronicslab/ 8

 Assessments
• TF is NOT applied in this subject.

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Assessments

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Assessments

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Assessments

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Assessments

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Assessments

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 Assessments

Important: students should expect to be marked at any time in the last 30 minutes, so be ready
for marking. Note that a catch up lab has been allocated for preparation of the design project. So
please prepare well in advance to shorten the time in building circuits on breadboards. 15
 Assessments
• Quiz 1 (weight 10%) is in the 2nd half of the lecture time in Week 4 (Aug
23)
• Exam papers and detailed questions will NOT be uploaded to Moodle
• Keys to the answer sheets will be uploaded to Moodle.
• Review of Quiz 1 will be discussed in Tutorial 4 (in class).
• If students want to review the Quiz 1 papers (with detailed questions)
again, just email me for an appointment.
• Quiz 1 will be marked by the marker assigned by the school (not me).
• Attendance: recorded in most of lectures, tutorials and practical.
• Used for determining the outcome of the Academic Consideration
application (refer to the UOW Student Academic Consideration
Guidelines).

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 Reasonable Adjustment & AC
• If you have a RA (Reasonable Adjustment) document, you must send me
as early as possible (as indicated in that document).

• If you have RA and you require a time extension and/or a separate exam
supervision for Quiz 1, you must contact me no later than Friday, Week 3
(Aug 16).

• For RA requirements regarding to Part B of the subject (e.g., Quiz 2),

you should contact Dr Peter Vial.

• University unifies the Academic Consideration (AC) requests from

students. If you need to submit an AC application, your supporting
documents must be verified by the student centre. Once verified, details
of your AC will be displayed for subject coordinators to process
(otherwise, no detail is displayed, thus impossible to process).

• Do not take advantage of medical certificates!

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 Calculator and Withdrawal

• Your calculator need to be approved. Otherwise, you cannot use it

during the final exam.
• Where to get it approved? See
http://www.uow.edu.au/student/exams/calculators/index.html
http://www.uow.edu.au/student/exams/permitted/index.html

• Last day to withdraw subjects without paying for them 31 Aug

• Last day to withdraw subject without academic penalty 29 Sept

subject deleted from record. Fail grade recorded if subject
withdrawn after this date
(see http://www.uow.edu.au/student/dates/index.html)

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 Plagiarism and Misconduct

Plagiarism and misconduct issues: use the electric circuit made in

previous years for Lab 5 (design project), copy other student’s lab
report, open materials in the in-class quiz, discussion in exam,
exchange the exam papers, copy website without proper citation, etc.

Plagiarism will not be tolerant

Penalty: mark deduction, school and/or faculty investigation, school

database, expelled from the course. See
http://www.uow.edu.au/about/policy/UOW058648.html

All students involved will be penalised.

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 Teaching Topics – Part A

Semiconductor, Diodes & Applications

Bipolar Junction Transistors (BJT) & BJT Bias

BJT Small AC Signal Analysis

Field Effect Transistors (FET)

FET Bias & FET Amplifiers

FET AC Analysis,
Power Amplifiers & Review of Part A

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 Week Lecture Tut Lab Quizzes Other
Activities
Lecture
W1 Tut 1
1

Lecture
W2 Tut 2
2
Lab 1
Lecture
W3 Tut 3
3

Lecture Quiz 1: 2nd hour of

W4 4 Tut 4 lecture time
Lab 2
Lecture
W5 Tut 5
5

Lecture Teacher Evaluation

W6 Tut 6 For Dr Le Chung Tran
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Lab 3
ECTE Lecture
W7 Tut 7
212 7

Lecture
W8 Tut 8
8
Lab 4
Lecture
W9 9 Tut 9

Lecture Catch-up Lab &

W 10 Tut 10
10 Preparation for
Design Project + Quiz 2: 2nd hour of
Lecture Tut 11 Lab Report
W 11 lecture time
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Lecture Tut 12 Report Due (Oct 21)

W 12
12 &
Marking the Design
W 13 Project (Lab 5)

The above scheduled tasks are anticipated. They might be changed due to some practical reasons. 21
Dr Peter Vial advised he will review Part B in Week 12 rather than in Week 13 as planned since it overlaps with ECTE250
conference and innovation fair.
 Top Down Approach – Example 1

Source: Internet 22
 Top Down Approach – Example 2

Source: Internet 23
 This Lecture

• P-N junction
• Semiconductor (or rectifier) diodes
• Applications of rectifier diodes
• Zener diodes

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 Semiconductor Materials

Materials commonly used in the development of semiconductor devices:

• Silicon (Si)
• Germanium (Ge)
• Gallium Arsenide (GaAs)

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 Intrinsic Semiconductor
Structure of the crystal network of Si Element Eg (eV) @ 300 K

Ge 0.67
Si Si Si
Si 1.1
valence GaAs 1.43
electron

Si Si Si
Fermi Level Model

Energy Free electron

E
Conduction band
Si Si Si
Ec
Gap band Eg

Ev
Valence band

• Valence electrons (e) are in covalent Electron constrained

bondings in the Si crystal in the crystal network
• No of free electrons = No of holes
Intrinsic semiconductors: 0< Eg < 5eV
Dielectric: Eg > 5eV 26
Metals: Eg does not exist
 Doping

The electrical characteristics of intrinsic Si and Ge are changed

significantly by adding materials in a process called doping.

Two types of doped semiconductor materials:

n-type
p-type

• n-type materials: No of holes << No of electrons

• p-type materials: No of holes >> No of electrons

• n: stands for negative

• p: stands for positive

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 N-type Semiconductor
Ec ∆E
ED
Eg

Si Si Si
Ev

• Eg = 1.1 eV for Si
• ∆E = (0.01 to 0.05) eV
Si P Si
• N-type semiconductor has
No. of free electrons >> No of holes
• Electrons are majority carriers
Si Si Si • Holes are minority carriers
• P, As, Sb (Group 15): are the donors
• When receiving energy ≥ 0.01 – 0.05 eV
electrons become free, and impurities
N-type semiconductor (P, As, Sb) become positive
Mix Si or Ge with some group-15 chemical elements ions (donor ions)

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 P-type Semiconductor
Ec

EA Eg
Ev
Si Si Si

Hole flow

• P-type semiconductor has

Si Al Si
No. of free electrons << No of holes
Electron flow
• Electrons are minority carriers
• Holes are majority carriers
Si Si Si
• In, Ga, Al, B (Group 13): are the
acceptors
• When receiving electrons from
adjacent bonds, impurities (In,
P-type semiconductor
Ga, Al, B) become negative ions
(acceptor ions)
Mix Si or Ge with some group-13 chemical elements

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 Majority and Minority Carriers
There are 2 types of free carriers (electrons and holes), thus 2
different currents might exist in semiconductor:

• Flow of majority carriers

majority carriers in
n-type materials are electrons.
p-type materials are holes.

• Flow of minority carriers

minority carriers in + : holes
n-type materials are holes. – : electrons
p-type materials are electrons. : donor ions
: acceptor ions

For short, denote electrons e, and holes p

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 P-N Junctions

One end of a Si or Ge crystal can be doped as a p-type

material and the other end as an n-type material.

The result is a p-n junction.

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 P-N Junctions - No Bias
Due to the different density of majority carriers,
e in n-type diffuse to p-type, while p in p-type
diffuse to n-type

The migration results in a region – called

depletion region - which
- is lack of free carriers (e and p)
- has (almost) only positive ions (of donors P, As,
Sb) and negative ions (of acceptors Ga, B, Al, In). Current created by flows of majority carriers

Current created by flows of minority carriers

This internal electric field
- prevents the further migration of majority carriers, but
- boosts the migration of minority carriers in the opposite direction (e migrate from p-type to
n-type and p migrate in the opposite direction).

Internal electric field is constant when the migration flows of minority and majority
carriers are equal
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 P-N Junctions - Reverse Bias

P connected to –VD
N connected to +VD
Internal & external electric fields
have same directions, thus
broadening the depletion region &
causing the inequality:

Flow of minority carriers > Flow of majority carriers

A reverse current thus flows from N to P (inside PN junction).

It is quickly saturated, even when the reverse voltage increases. This
current is called reverse saturation current, Is.
It is very small, in the range of nA or µA, because the number of minority
carriers is limited.
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 P-N Junctions - Forward Bias
P connected to + VD
N connected to – VD
External electric field >< internal one
Depletion region becomes narrower, thus
Flow of majority carriers > Flow of minority carriers
which results in a forward current ID flowing
from P to N (in the range of mA).

The greater the forward voltage is, the narrower the depletion region is,
and thus the larger the current is

I D  IS (eVD /nVT  1) (Shockley equation)

Is is the reverse saturation current,
VT is thermal voltage (VT = kT/q), n is the coefficient depending on the material (n =1 except
when clearly stated).
Boltzmann’s constant: k = 1.38. 10-23 J/K. Charge of an electron q=1.6. 10-19 Coulombs.
T temperature in Kelvin degree (oK). Note: oK = oC +273.
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 Theoretical and Actual V-A Characteristics
V-A characteristics:

I D  IS (e VD /nVT  1)

Forward bias (VD > 0): if VD >> VT

I D  IS (eVD /nVT  1)  ISeVD /nVT

Reverse bias (VD < 0): if |VD| >> VT

ID  IS (eVD/nVT  1)  IS

No bias (VD = 0): ID  0

p-n junction conducts in one
direction and does not conduct in
the other (rectifying effect)

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 Zener Region
• Zener region is in the reverse-bias
region. Named after Clarence Melvin
Zener
• At some point the reverse bias
voltage is so large that the reverse
current suddenly increases
dramatically. This voltage, Vz, is
called zener (breakdown) voltage
• Vz is the voltage that causes a P-N
junction to enter the Zener region
P-type N - type
• maximum reverse voltage that won’t
take a P-N junction into the Zener
region is called the peak inverse
voltage (PIV) or peak reverse
voltage.
- +
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Free e collide with atoms at high speed, creating more free e and p
Semiconductor Diodes

• diode is a 2-terminal device: 1 p-n

junction & two electrodes: anode
connected to P, cathode connected
to N.
• Work based on the rectifying effect
of the p-n junction, i.e. conduction in
only one direction
• Arrow points in the direction of the
current flowing through the diode
when it is forward biased.

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 Ideal Diode Characteristics
V-A characteristic of ideal diode

ID (mA)

VD (V)

Conducting (forward bias): Non-conducting (reverse bias):

• diode acts like a short circuit • diode acts like an open circuit
• voltage across diode is 0 V • current is 0 A
• forward resistance is RD = VD / ID = 0 • reverse resistance is RD = VD / ID = ∞
• current is limited by the circuit • all external voltage is across diode

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 Realistic Diodes

Realistic diode has internal resistance

A diode has three operating conditions:
No Bias

• VD = 0 V, ID = 0 A

Reverse Bias

• There exits a reverse current which

quickly saturates, denoted Is

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 Diode Operating Conditions
Forward Bias

• There exists the forward current ID flowing

through P-N junction from P to N
• Shockley formula

ID  IS (eVD/nVT 1)

• where VT = kT/q = 25 mV at 20oC, and

VT = 26 mV at 25oC and 27oC

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 Forward Bias Voltage
Diode changes from no-bias to
forward-bias when e and p are given
sufficient energy to cross the p-n
junction.
This energy comes from the external
voltage applied across the diode
The min voltage to make diode
forward biased is denoted as VF

• Ge diode VF  0.3 V
• Si diode VF  0.7 V
• GaAs diode VF  1.2 V

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 DC and AC Resistances

A semiconductor diode reacts differently to DC and AC currents.

We are interested in two types of resistance:

• DC (static) resistance
• AC (dynamic) resistance

Reminder: DC: direct current, AC: Alternating current

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 DC (Static) Resistance
When a DC voltage VD is applied,
diode has a specific DC current ID
DC (or static) resistance RD is defined
as Q

VD
RD 
ID
The point (ID, VD) is called quiescent
point or Q-point or DC operating point

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 AC (Dynamic) Resistance
Together with the DC applied voltage, if we apply an AC voltage (e.g. sine
wave) to diode, the actual operating point moves around the DC operating
point Q. AC resistance is defined as:

dVD VD Differentiate the Shockley equation

rD  
I D
 
dI D
I D  IS e VD /nVT  1
we have

dVD nVT n. 26 (mV)

rD    ()
dI D ID I D (mA)

AC resistance at a certain point can be estimated

mathematically if the DC current at that point is known

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 Load-Line Analysis
• Most basic application is the series diode VD
ID
configuration + −

• Load line plots all possible combinations

of diode current (ID) and voltage (VD) for a
given circuit (i.e. given load).
• Load line equation: VD = E - IDR
• Two intersection points
VD = 0, ID = E/R &
VD = E, ID = 0
• Intersection between the load line &
characteristic curve is the Q-point, which
identifies ID and VD for a particular diode in
a given circuit.
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 Series Diode Configurations
Forward Bias VD ID
+ −
Constants
• Silicon Diode: VD ≈ 0.7 V
• Germanium Diode: VD ≈ 0.3 V

Analysis (for silicon)

• VD ≈ 0.7 V (or VD = E if E < 0.7 V)
• VR = E – VD
• ID = IR = VR / R

ID can be more accurately calculated from the Shockley formula if the

VD and IS are known
ID  IS (eVD/nVT 1)  ISeVD/nVT
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 Series Diode Configurations

Reverse Bias

Diodes ideally behave as open circuits VD

+ −

Analysis
• VD = E
• VR = 0 V
• ID = 0 A

If we replace the DC voltage E in a series diode configuration by an

AC voltage, we have a half-wave rectifier

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 Half-Wave Rectification

• diode only
conducts when
forward biased

• only half of the

AC cycle passes
through the
diode to the
output.

The DC output voltage is 0.318Vm, where Vm = the peak AC voltage.

T
1 2 Vm
VDC = න Vm sin ωt dt = = 0.318Vm
T 0 π

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 Full-Wave Rectification

The rectification process can be

improved by using a full-wave rectifier
circuit.

Full-wave rectification produces a

greater DC output:

1 T 2Vm
VDC = න Vm sin ωt dt = = 0.636Vm
T 0 π

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 Full-Wave Rectification
Bridge Rectifier

• 4 diodes in a bridge
configuration

• Output DC voltage:

1 T
VDC = න Vm sin ωt dt
T 0
2Vm
= = 0.636Vm
π

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 Zener Diode

• Zener diode operates in reverse

bias at the Zener voltage (VZ).
• Note that VZ is, with the direction
shown in the figure, positive to
guarantee that Zener diode is
reverse biased.
• They are used to regulate
(stabilise) the voltage, normally in
the range between 1.8 V and 200
V, and power from 1/4 W to 50 W

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 Voltage Regulation Concept
R ID

VD
E RL

• Load line equation:

VD  E  I D R
• ∆E >> ∆VD
• Thus VD = -VZ ≈ constant

VZ is usually a positive value, e.g. VZ = 6V, VZ = 5.1V etc.

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 Zener Diode Analysis
IR
Zener is a diode operated in reverse
bias at the Zener voltage (Vz) 1K IRL
• When Vi  VZ
10V
– The Zener is on 16V
3K
– Voltage across the Zener is VZ
VZ 10V
I RL    3.33mA
R L 3K
Vi  VZ 6V
IR    6mA
R 1K
I Z  I R  I RL  6  3.33  2.67mA

– Zener power: PZ = VZIZ=10x2.67 = 26.7mW

• When Vi < VZ
– The Zener is off
– The Zener acts as an open circuit

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 Summary

• P-N junction
– No bias
– Reverse bias
– Forward bias
• Semiconductor diodes
– Construction and operation
– Equivalent circuit
– Diode resistors
• Applications
• Zener diodes

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