Translation Lookaside Buffer

- Only the lower 12-bits of the linear address match the lower 12-
bits of the physical location in RAM or ROM where data is
located. The upper 20-bits of linear address must go into two
levels of translation to get the actual address of the beginning
page where data is held. This is the reason for having (TLB).
- Translation Look Aside Buffer (TLB):holds the list of the most recently
(commonly) used physical addresses of the page frames when the CPU
wants to access a piece of information (Data or Code) by providing linear
address , it first compares the 20-bit upper address with TLB to see if the
table entry for the required page inside the CPU.
- There are two possibilities:
1. If match then 20-bit physical address combined with the lower 12-bit linear
address then the result will be 32-bits physical address to put on 32 address
pins to fetch data or code.
2. If does not match, the CPU must fetch into TLB the page table entry from
memory.
- Since the TLB in the 80386 keeps the list of addresses for the 32 most
recently used pages, it allows the CPU to have access to 128k bytes
(32*4 = 128) of code and data at any time without going through the
time –consuming process of converting the linear address to a physical
address (two-stage table translation).
- One way to enhance the processor is to increase the number of pages
held by the TLB. This is what the Pentium has done.