Basic operation DMA

The device requests the CPU to hold its data, address and control bus, so the device is free to transfer
data directly to/from the memory. The DMA data transfer is initiated only after receiving HLDA signal
from the CPU.

How DMA operations are performed?

Following is the sequence of operations performed by DMA:

 Initially, when any I/O device has to transfer data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert the
HLDA.
 Then the microprocessor tri-states all the data bus, address bus and control bus. The CPU leaves
the control over bus and acknowledge the Hold request through HLDA signal.
 Now the CPU is in Hold state and the DMA controller has to manage the operations over buses
between the CPU, memory and I/O devices
Direct memory access diagram

Below we have a block diagram of DMA controller.

Whenever a processor is requested to read or write a block of data, i.e. transfer a block of data, it
instructs the DMA controller by sending the following information:

 Read or write command, sending through read or write control lines.

 Starting address for the data block in memory to read from or write to, communicated in data
lines and stored in the address register. It also called the start address register.
 Number of words to be read or written, communicated on the data lines and stored in the data
count or the word count register.
 Address of the I/O device involved, communicated on data lines.

DMA Controller modes for data transfer.

The DMA transfer the data in three modes which include the following:

 Burst transfer: DMA handover the buses to CPU only after completion of whole data transfer.
Meanwhile, if the CPU requires the bus it has to stay ideal and wait for data transfer.
 Cycle stealing: DMA gives control of buses to CPU after transfer of every bytes. It continuously
issues a request for bus control. Makes the transfer of one byte and returns the bus.
 Transparent: DMA transfer data only when CPU is executing the instruction which does not
require the use of buses.