DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

Subject with code COMPUTER ARCHITECTURE AND

ORGANIZATION- CSE18R174
Course/Department B.Tech

TUTORIAL -1

1. An instruction ADD R1, A is stored at memory location 4004H. R1 is a processor

register and A is a memory location with address 400CH. Each instruction is 32-
bit long. What will be the values of PC, IR and MAR during execution of the
instruction?
a. 4004H; ADD R1, A; 400CH
b. 4008H; ADD; 400CH
c. 4008H; ADD R1, A; 400CH
d. None of the above
2. The task of the Program Counter (PC) is to

a. Point to the next instruction to be executed.

b. Count the total number of instructions in a program.
c. Point to the current instruction that is being executed.
d. None of the above.

3. A computer has 2GB (Gigabytes) of byte addressable memory. The number of

address lines will be 31.

4. Consider a 1 MB (Mega byte) byte addressable memory system, with word

size of 32 bits. The number of bits in MAR and MDR will be:
a. 23,32
b. 20, 8
c. 23, 32
d. 20, 32

5. A hexadecimal number A45DF7BC is stored from memory address 3007H in

little endian format. The byte stored in memory locations 3007H, 3008H,
3009H, and 300AH will be:
 a. BC, F7, 5D, A4
b. A4, 5D, F7, BC
c. BC, F7, A4, 5D
d. F7, BC, A4, 5D

6. Which of the following instructions are valid in stack architectures?

a. ADD
b. PUSH X
c. ADD X
d. POP

7. The minimum number of instructions required to execute the statement A =

(B+C)/ D using accumulator-based architecture is 4 , where A, B, C and D are
memory locations.

8. The minimum number of instructions required to execute the statement A =

(B+C)/D using load store architecture is 6, where A, B, C and D are memory
locations.

9. Which instruction is typically not part of an Instruction Set Architecture?

a) mul
b) sub
c) or
d) add1 4

10. What is an example of CISC instruction set?

a) ARM
b) IBM PowerPC
c) Intel x86
d) HP PA-RISC

11. Is sbn instruction a Turing complete instruction? True or False

12. Which of the following is an Universal operation?

a) AND
b) OR
c) NOR
d) XOR

13. What is the value of 1 1 1 1 01 01 (8 bit binary in 1 ’s complement form) in

decimal?
a) 1 0
b) -1 1 7
c) 245
d) -1 0
14. What is the value of (243)5 in decimal?
a) 73
b) 1 1
c) 55
d) 97

15. What is the value of (4090)1 0 in hexa-decimal?

(FEA)1 6
(FFA)1 6
(EFA)1 6
(EEA)1 6

16. What is in 2’s complement binary representation of -4?

1 1 00
01 00
1 01 0
01 01

17. What is the binary encoding for "ld r0, [sp]"

a) 01 1 1 0 1 0000 1 1 1 0 000000000000000000
b) 00000 1 01 00 01 00 01 000000000000001 1
c) 00001 1 1 1 1 0 1 1 1 0 0000000000000001 00
d) 01 000 0 01 00 0000 0000000000000001 01

18. Assembly languages are specific to:

a) Compiler
b) Operating System
c) Hardware
d) Instruction set Architecture

19. Assemblers are:

a) programs that convert high level language to low level language
b) programs that convert low level language to machine language
c) programs that convert high level language to machine language
d) all of the above

20. Program counter contains the address of

a) current instruction
b) next instruction
c) previous instruction
d) It stores data not the address
21. How many instructions are present in simple RISC ISA
a) 1 9
b) 20
c) 21
d) 22

22. "mov" instruction is used to:

a) transfer contents of one register to another
b) transfer content of immediate to register
c) both a and b
d) none

23. How many Arithmetic instructions are present in simple RISC ISA
a) 5
b) 6
c) 1 0
d) 8

24. Load and store instructions are used to perform:

a) memory operation
b) register operation
c) both
d) none

25. Return instruction is used for:

a) puts return address register (ra) value in pc
b) puts ra + 4 value in pc
c) puts pc + 4 value in ra
d) none of the above

26. ret instruction is:

a) 0 address instruction
b) 1 address instruction
c) 2 address instruction
d) 3 address instruction

27. What is the return PC after a function call?

a) pc
b) pc+1
c) pc+2
d) pc+4
28. The arguments to a function can only be passed using registers. True or False
a) True
b) False

29. Which is the return address register?

a) r0
b) r1 5
c) r1 3
d) r1 4

30. What is the value of r1 after mvn r1 , #3 is executed?

a) 0x00000003
b) 0xFFFFFFC
c) 0xFFFFFFE
d) 0xFFFFFFD

31. Which instruction is equivalent to r1 = 8*r2

a) mul r1 , r2, #8
b) lsl r1 , r2, #3
c) Both a and b
d) None

32. Flags can be set only by the cmp instruction. True or False?
a) True
b) False

TUTORIAL -II

1. A stack can solve

a) space problem
b) overwrite problem
c) management of activation blocks
d) all the above

2. What is the actual address to jump in a b offset instruction?

a) PC + offset
b) PC - offset
c) PC + 4*offset
d) PC – 4*offset
3. What is the binary encoding of “add r0, r1 , 1 ” in SimpleRISC ISA?
a) 00000 1 0001 0000 000000000000000001
b) 00000 0 0000 0001 000000000000000001
c) 00000 1 0000 0001 000000000000000001
d) 00000 0 0001 0000 000000000000000001

4. Instruction to compute 2’s complement of a number stored in r0 is

a) rsb r1 , r0, #0
b) mvn r1 , r0
c) sub r1 , r0, #0
d) bic r1 , r2, r2

5. Which instruction is used to make a function call in ARM?

6. What is the encoding of 0x0B A0 00 00 in 1 2-bit ARM rot+payload immediate

format? 0x6BA

7. Branch target in bl offset instruction in ARM is: PC + 8 + 4*offset

8. What is the preferred method to return from a function call in ARM?

9. What does stmfd instruction do in ARM? spill a set of registers

10. We can run the 1 6 bit ISAs on a modern 64 bit x86 processor. True or False?

11. x86 can even Support 8 bit Registers. True or False?

12. How many floating point registers are there in x86 ISA?

13. How many segment registers are there in x86 ISA?

14. Which memory addressing mode is supported by x86?

( base + offset, base +scale*index, base + scale*index + offset)

15. Is an x86 processor aware of the presence of the stack?

16. The stack pointer is stored in the register:

17. The compare instruction in x86 processor sets the flags.

18. eax and edx in imul instruction (1 operand form) contain

19. The call instruction saves the return address on –

20. The rep prefix repeats the instruction n times. The value of n is present in -
register

21. Integer and Floating point registers are connected through:

22. An NMOS transistor is made up of:

a) two p-type wells in an n-type substrate.
b) two n-type wells in a p-type substrate.
c) None of the above

23. A PMOS transistor is made up of:

a) two p-type wells in an n-type substrate.
b) two n-type wells in a p-type substrate.
c) None of the above

24. A NOR gate consists of:

a) 2 transistors
b) 3 transistors
c) 4 transistors
d) 5 transistors

25. Multiplexer:
a) n inputs, 1 output
b) 1 input, n outputs
c) n inputs, 1 output based on the select bits
d) n inputs, log(n) outputs

TUTORIAL -III

1. Encoder:
a) n bits input, log(n) bits output
b) n inputs, log(n) output
c) n inputs, log(n) bits output
d) None of the above

2. In an SR latch, if S=0 and R=0, then Q is

a) 0
b) 1
c) Maintain old value
 d) Not defined

3. In a master slave J-K flip flop:

a) master gives the final output
b) slave gives the final output
c) none of the above

4. Implementation of a sram cell compared to a dram cell requires:

a more number of transistors
b less number of transistors
c same number of transistors

5. In an array of SRAM cells:

a) Only one row can be enabled at a time
b) Only one column can be enabled at a time
c) all the cells in a column can be enabled at a time
d) none of the above

6. CAM cell:
a) Enable cells by their address
b) Enable cells by their content

7. How long does the n-bit Ripple Carry Adder take? th is time for half adder and tf
is time for full
adder.
a) n*tf
b) n*th
c) th + (n-1 )tf
d) tf + (n-1 )th

8. What is the time-complexity of a n-bit Ripple Carry Adder?

a) O(1 )
b) O(n2)
c) O(n)
d) O(log n)

9. What is the time-complexity of a n-bit Carry Select Adder?

a) O(1 )
b) O(√n)
c) O(n)
d) O(log n)
10. What is the time-complexity of a n-bit Carry Look Ahead Adder?
a) O(1 )
b) O(√n)
c) O(n)
d) O(log n)

11. What is the time-complexity of a n-bit Booth Multiplier?

a) O(n)
b) O(n*n)
c) O(n*√n)
d) O(n*log(n))

12. What is the time-complexity of a n-bit Tree-based Multiplier?

a) O(n)
b) O(n*√n)
c) O(n*log(n))
d) O(log(n)*log(n))

13. What is the time-complexity of a n-bit Carry Select Adder if k is set to 1 ?

a) O(1 )
b) O(√n)
c) O(n)
d) O(log n)

14. What is the time-complexity of a n-bit Wallace-Tree Multiplier?

a) O(√n)
b) O(n)
c) O(log(n))
d) O(log(n)*log(n))

15. What action should be taken when current value is 0 and previous value was 1 in
case of
Booth’s multiplication?
a) Subtract multiplicand from U
b) add multiplicand to U
c) None of the above

16. Can we use Booth’s multiplier for multiplication of negative numbers?

a) Yes
b) No
17. How many iterations are used by Restoring algorithm to divide two 32 bit
numbers?

18. Time complexity of each iteration in Restoring algorithm is:

19. Assume that U contains remainder and D contains Divisor. If (U-D)>=0,then

20. How many rounding modes are available in IEEE 754 standard?

21. What is the condition for incrementing the significand in Round to Nearest
mode?

22. Time complexity of Goldschmidt algorithm is:

23. Number of steps and complexity of each step in Newton Raphson method is:

24. Normalization operation in multiplication of floating point numbers can be done

by using:

25. The value of isBranchTaken in case of call, ret and b instruction is

a) 0
b) 1

26. The isImmediate signal choses a value between

a) op1 and op2
b) immx and op1
c) immx and op2

27. The write port Address in RW Unit can be

a) pc
b) ra(1 5)
c) rd(inst[23:26])
d) both b and c

28. The write port Data in RW Unit can be

a) aluResult
b) ldResult
c) pc+4
d) all the above
29. Which is not an input to the Control Unit?
a) opcode
b) inst[23:26]
c) I bit

30. The isWb signal is not set for which instruction?

a) mul
b) ld
c) b
d) call

31. The isAdd signal is set for which instruction?

a) add
b) ld
c) st
d) all the above

32. The following Microinstructions is an implementation of which SimpleRISC

instruction?
mbeq flags.GT, 1 , .branch
mb .begin
.branch:
mmov pc, branchTarget
mb .begin
a) beq
b) bgt
c) b
d) call

33. The following Microinstructions is an implementation of which SimpleRISC

instruction?
mmov regData, pc
mmovi regSrc, 1 5, <write>
mmov pc, branchTarget
mb .begin
a) beq
b) bgt
c) b
d) call