MICROPROCESSOR EXIT EXAM REVIEWER

1. Based from order, when the instruction PUSHA is applied, which of the following
register is "PUSHED" last?
A. CX
B. AX
C. SI
D. DI

2. Pushes all registers to the stack

Ans. PUSHA

Note:
PUSH – push data onto stack
PUSHW - push word onto stack
PUSHD - push double word onto stack
PUSHA - push all registers to stack (60)
*Processors pushed the registers in the order: AX, CX, DX, BX, SP, BP, SI and DI.
The SP word pushed is the value before the first register is pushed.
PUSHF - push flags onto stack (9C)

3. The lower byte of the flag register contains 83h. Which flag registers are cleared as
a result of executing LAHF instruction?
A. PF (PARITY, ZERO, AUXILLIARY ARE CLEARED : MICRO BOOK
PAGE 87)
B. SF
C. none of the choices
D. CF
4. The lower byte of the flag register contains 83h. Which flag registers are set as a
result of executing LAHF instruction?
A. PF
B. ZF
C. AF
D. SF (SIGN, AND CARRY FLAGS ARE SET: MICRO BOOK PAGE 87)

5. The lower byte of the flag register contains 83h. What is the result of an LAHF
instruction?
A. AH = 83h
B. AX = 83h
C. AL = 83h
D. all the flags are set to 83h

6. Machine code for LAHF

Ans. 9F
Note: 9E for SAHF
7. The higher byte of the flag register contains 83h. Which flag registers are cleared as
a result of executing LAHF instruction?
Ans. AF

8. Prevent changing the location POPA which register is not loaded with data
Ans. SP or ESP
Note: POPA Pop All Registers; Intel 80x86; move memory pointed to by stack pointer
to all 16-bit general purpose registers (except for SP); does not affect flags

9. What segment is used for store destination string?

A. ES
B. Any
C. DS
D. CS

10. Instruction that sets carry flag to 1

Ans. STC Note:
PROGRAM CONTROL
INSTRUCTIONS 14. It is an instruction used to preserve
CLC - Sets carry flag to 0 (clear carry the contents of the outer loop counter
flag) A. LOOP
CMC - Complement carry flag B. PUSH
STD - Sets direction flag to 1 (set C. PUSH and POP
direction flag) (MICROPROCESSOR PAGE 126)
CLD - Sets direction flag to 0 (clear D. POP
direction flag)
STI - Set interrupt enable flag 15. It is considered as a system signal
CLI - Clear interrupt enable flag used in troubleshooting techniques for
8088 hardware architecture.
11. What does the command IN AL, A. DEN
DX mean? B. INTR
Ans. IN AL, DX: Input byte from C. HLDA (MICROPROCESSOR
I/O port in DX into AL PAGE 305)
D. ALE
12. Which of the ff is a bit
manipulation instruction? Note:
A. SHL DL; 2 System signals – CLK, RESET,
B. Any (MICROPROCESSOR READY, HOLD, HLDA, and MN/MX
BOOK PAGE 32) Signals involved with memory and I/O
C. ROL AX,1 access – ALE, RD, WR, DEN, DT/R,
D. NOT AL IO/M
Signals involved with interrupts - NMI,
Note: Check LECTURE NOTE 7- INTR, INTA
8_MICRO_COMANLISES
(Instruction Set and Programming) 16. It is the standard bus connector
Bit manipulation instructions - NOT, agreed upon by the PC business
AND, OR, XOR, TEST, BT, BTC, BTR, comprising of 62 pins found in early
BTS, SHL/SAL, SHR, SAR, ROL, ROR, PC motherboards that allow expansion
RCL, RCR with the 8088 microprocessor.
A. SATA connector
13. Which of the following is a logical B. ISA connector (MICRO
instruction? PROCESSOR BOOK PAGE 304)
A. TEST (MICROPROCESSOR C. RS232C connector
BOOK PAGE 113) D. SCSI connector
B. ADC
C. SHL 17. The following is true for r/m except
D. CMP for
A. r/m are used for addressing modes
B. r/m refers to registers enclosed in
Note: brackets
Logical Instructions – NOT, AND, OR, C. when mod = 11, r/m indicates a
XOR, TEST, BSF/BSR, register field
BT/BTC/BTS/BTR, SETcc, SETNZ D. r/m specifies the addressing mode
18. Which is false for r/m
A. r/m refers to registers enclosed in
brackets
B. r/m are used for addressing modes
C. r/m specifies the addressing mode
D. when mod = 11, r/m indicates a
register field

19. ARM stands for

A. Advance RISC Machines

B. Advance Response Machines
22. How many additional control reg
C. Advance RISC Model
are activated based from Pentium’s
D. Advance Reprogrammable Model
protected mode
Ans. 5
Note:
RISC – reduced instruction set
PROPOSITION QUESTIONS
computer
23. Which is a valid conclusion?
CISC – complex instruction set
Choices:
computer
(a) All humming birds are richly
colored
20. Signal that has I/O clk
(b) No large birds live on honey
Ans. CLK
(c) Birds that do not live on honey are
dull in color
21. The 8088's I/O addressing space
(d) Hummingbirds are small
contains how many possible
24. Consider the symbolic logic taken
input/output ports?
from Lewis Caroll illustrating how
A. 1048576
quantifiers are used in statements.
B. 4096
Which of the following is/are
C. 1024
premises?
D.65536 (MICROPROCESSOR
I. All lions are fierce
BOOK PAGE 296)
II. Some lions dont drink coffee
III. Some fierce creatures do not drink
coffee
Ans. I and II

25. There exists X not P(x)

there is an x for which P(x) is false
P(x) is true for every x
there is an x for which P(x) is true
every x, P(x) is false
26.

BIG-O NOTATION QUESTIONS

27. An algorithm that uses Hamiltonian

cycle to solve uses a Big-O notation of
Ans. Logarithmic complexity

28. An algorithm that uses Eulerian

Path/Bubble Sort to solve uses a Big-O
notation of
Ans. Linear complexity
29. An algorithm that uses Selection to
solve uses a Big-O notation of
Ans. Quadratic
Note:
SSI – less than 100 components (about
10 gates)
MSI – less than 500 components or
have more than 10 but less than 100
gates
LSI – between 500 and 300000 or have
more than 100 gates
VLSI – more than 300000 components
per chip

31. What is the highest privilege (RPL)

in protected mode?
Ans. 00
30. 10 – 1000 gates in a single package:
Ans. MSI
Note:
00 – highest
11 – lowest
32. Addressing mode executes its
instructions within CPU without the
necessity of reference memory for
operands?
Ans. Register Mode
33. Which technique does the Pentium
Pro employs where the processor looks
ahead into the instruction stream
pipeline can be kept busy?
Ans. Speculative execution
34. If 8088 has frequency of 4MHz, the
time of one T state? [200 ns; 80 ns, 250
ns; 300 ns]
Ans. 250 ns
35. This input is used to force the
Pentium to limit addressable memory
to 1 Mb to emulate the memory space
of the 8086.
Ans. A20M
36. 13.mm = __ is automatically used
for direct addressing
Ans. 00
37. A processor running in this mode
can exploit only the lowest 20 bits of
its address bus and is therefore limited
to the meager 1MB memory space
Ans. Real mode
38. This method of storing 16-bit
numbers in memory, wherein the lower
byte is already read/write to the lower
memory address
Ans. Little Endian
39. Intel introduced cache memory for
this microprocessor when it was
launched. The Western Design Center,
Inc (WDC) introduced this
microprocessor in 1982 and was used
as the CPU in the Apple IIe and IIc
personal computers
Ans. CMOS 8502
Note:
The Western Design Center, Inc.
(WDC) introduced the CMOS 65C02
in 1982 and licensed the design to
several firms. It became the core of the
Apple IIc and IIe personal computers,
medical implantable grade pacemakers
and defibrilators, automotive, industrial
and consumer devices. WDC pioneered
the licensing of microprocessor
technology which was later followed
by ARM and other microprocessor
Intellectual Property (IP) providers in
the 1990’s.
40. The ____ part specifies the
addressing mode for the selected
instruction
A. MOD
B. Addr-low
C. REG
D. R/M
41. Product term wherein which all
variables appear once rather
complement or uncomplemented
Ans. Minterm
42. Digital integrated circuits are
classified not only by their complexity
or logical operation, but also by the
specific circuit technology to which
they belong.
The circuit technology is referred to as
____.
Ans. Digital logic family
43. This is the time needed by a gate in
processing its input signals before the
output signal can be generated
Ans. Propagation delay time
44. Intel’s server and workstation
powerhouse.
Choices: [Celeron, Xeon]
Ans. Xeon (Intel Microprocessor by
James Antonakos)
45. Questions about RAM
A. STATIC RAM – fast, easy
interface, small size (16 bytes per chip)
B. DYNAMIC RAM – high density
(256K per chip), requires numerous
refreshing cycles to retain data.
Note: Both STATIC and DYNAMIC
lose info when turned off
C. NVRAM (Non-Volatile Random-
Access Memory) – retains memory
even power is turned off
ROM – Read-Only Memory, non-
volatile memory
46. Internal high-speed memory
(*not sure if it is the exact question)
Ans. CACHE
Note:
BIT MANIPULATION – SHL, SAL,
SHR, SHLD/SHRS, ROL, ROR,
RCL/RCR
LOGICAL INSTRUCTIONS - NOT,
AND, OR, XOR, TEST
PROGRAM TRANSFER
INSTRUCTION – JMP, RET, INT,
BOUND, PROC, ENDP, CALL, IRET
PROCESSOR CONTROL
INSTRUCTIONS – CLC/STC, CMC,
CLD/STD, CLI/STI, HLT, NOP, LOCK
49. First commercial 8-bit processor
Ans. Intel 8008 (1972)
50. Developed a single general-purpose
chip that could be programmed to carry
out a calculator’s function.
Ans. Ted Hoff
51. Which is used as the medium of
communication between the processor
and the outside world.
Ans. I/O Port

Note: 52. Who made calculator into

- Advance microprocessor load more computer?
than one instruction into this special Ans. Charles Babbage
buffer to space time
- While microprocessor is decoding 53. … fast retrieval?
other instruction, other memory can be Choices: [Static RAM, Dynamic RAM,
read from instruction cache. ROM, NVRAM]
Ans. STATIC RAM
47. Which of the following cannot be
found in microprocessor/ 54. Understand the code
microcontroller/ CPU Choices: [Interpreter, Compiler,
Choices: [Memory, ALU, Register] Assembler, Debugger]
Ans. Memory Ans. Compiler

48. Which of the following is BIT 55. Type of RAM that changes during
MANIPULATION? regular interval
Choices: [SHL, OR, AND] Choices: [Static RAM, Dynamic RAM,
Ans. SHL (pero sa ibang ref. lahat ROM, NVRAM]
yan bit manipulation, check lecture Ans. Dynamic RAM
note 7 manlises)
56. INT AX, DX
Ans. Read from DX, write to AX
57. Where will you know if it is in 16
bit or 32 bit?
Choices: [AV, D, G, RPL]
Ans. D (read COE121 LECTURE
NOTE 5_MICRO_COMANLISES)
58. Memory of 8 bit?
Choices: [16kB, 8kB, 64kB]
Ans. 64kB
59. Translation lookaside buffer
- a memory cache that is used to reduce
the time taken to access a user memory
location. It is a part of the chip’s
memory-management unit (MMU).
The TLB stores the recent translations
of virtual memory to physical memory
and can be called an address-translation
cache (Ref. Wikipedia)
60. Master slave D-flip flop is similar
to a synchronous edge triggered flip
flop, therefore it should have the ff
behavior except?
Ans. a change in output is activated
by a clock pulse.
61. Race condition in R-S Latch
Ans. R=1 S=1
62. If an ASCII of A is used with odd
parity, the results is
Ans. 1100 0001 (C 1)
63. If an ASCII of A is used with even
parity the results is
Ans. 0100 0001 (4 1)
64. A parity bit is used in error
detecting codes, if an ASCII of T is
used with odd parity the result is
Ans. 0101 0100 (5 4)
65. Decimal parallel adder that adds 5
decimal digits requires how many BCD
adder stages?
A. 5
B. 6
C. 3
D. 4
Note:
parallel adder: n decimal digits need
n BCD adder stages
multiplier: n-1 sa isang OT, yung
sinulat ni gelo ndigits(ndigits-1)
66. 74LS83 is an example 4-bit parallel
adder. To expand this device to an 8-bit
adder, you must
A. use four adders with no
interconnections
B. use two adders and connect the
sum outputs of one to the bit inputs
of the other
C. use eight adders with no
interconnections.
D. Two adders with the carry output
of one connected to the input of the
other
67. 2 bit by 2 bit multiplier is simply
implemented using which of the
following combinational circuit?
A. 2 Half Adders and 4 AND gates
B. 2 Full Adders and an OR gate
C. 2 Full Adders and 4 AND gates
D. One 4 bit binary adder, 2 AND gates 72. Exclusive-OR (XOR) logic gates
and 1 OR gate can be constructed from what other
Note: logic gates?
Ans. AND gates, OR gates, and NOT
gates

73. Given a synchronous sequential

2X2 = 4 AND circuit what is the next state with
2-1 = 1 ADDER = ½ ADDER + ½ input = 1, if the current state is 001?
ADDER Ans. 010

68. If the function v(w+x+y)z would be

implemented using NOR gates?
Ans. Six NOR gates will be used

69. How many 4-binary adders are

needed to create a single digit binary
adder?
Ans. 4
Note:
n binary adders = single digit binary
adder

74. Refer to the behavior of

70. 4-bit magnitude comparator
combinational circuit A < B what logic
gate?
Ans. 4-input OR gate
71. 4-bit magnitude comparator
combinational circuit A = B what logic
gate?
Ans. 4-input AND gate
synchronous sequential circuit below.
Assume that the states are identified as
the combination ABC. What is the
complement of the next state for an
input of 1, if the current state is 001?
A. 010
B. 011
C. 101 78. A 4-input (D0 - D3) priority
D. 110 encoder circuit contain 3 output
functions (x, y) pertaining to binary
75. Given a synchronous sequential values. What is the function for the
circuit what is the next state with least significant bit y?
input = 0, if the current state is 010? A. D2 + D3
Ans. 100 B. D1 + D2 + D3
C. D3 + D1D2’
76. A 3 x 8 decoder contains output D. D2 + D1’D3
from D0 to D7. Which output is
activated high if the input expression
x'yz'?
A. D1
B. D2
C. D4
D. D5

79. 2 to 4 line decoder, made of NAND

gates which input would produce an
output of 1011 from D0 to D3
A. 1XX
77. A 4-input (D0 - D3) priority B.
encoder circuit contain 3 output
functions (x, y) pertaining to binary
values. What is the function for the
least significant bit x?
A. D2 + D3
B. D1 + D2 + D3
C. D3 + D1D2’
D. D2 + D1’D3

001
C. 011
D. 010
80. Under precedence of logical D. (p->(p v q))’
operators which is performed last?
Ans. Biconditional 84. How many basic theorems and
postulates are used to prove the
81. Which of the ff logical operator is expression x + xy = x
performed first? A. 6
Ans. AND (wala daw sa choices yung B. 4
NOT) C. 5
D. 3
Note:
precedence of logical operators -
NOT(Negation), AND(Conjunction),
OR(Disjunction), Note:
IMPLICATION, 3 laws namely; LAW OF UNION,
BICONDITIONAL(Equivalence) DISTRIBUTIVE, and INTERSECTION

85. Which of the ff relation from Set A

82. The expression below is regarded {integer numbers} is considered as
as (p ^ q) -> (p v q) equivalence relation?
Ans. TAUTOLOGY A. R = {(a,b) | a > b or a = b }
B. R = {(a,b) | a b (mod m) with m >
p q p^q pvq (p ^ q) -> (p v q)
1}
C. R = {(a,b) | a + b = 3}
0 0 0 0 1 D. R = {(a,b) | a < b}
0 1 0 1 1
Note:
1 0 0 1 1 Ref:
1 1 1 1 1 https://www.cs.odu.edu/~cs381/cs381c
ontent/relation/eq_relation/eq_relation.
html
83. Which of the propositional
expression is contradiction?
Definition(equivalence relation): A
A. (p ^ q)’ -> p
binary relation R on a set A is an
B. (p -> q)’ -> q’
equivalence relation if and only if
C. (p -> q)’ -> p
(1) R is reflexive
(2) R is symmetric, and 89. p v p = p
(3) R is transitive. Ans. Idempotent Law

Example 1: The equality relation (=) on

a set of numbers such as {1, 2, 3} is an
equivalence relation.
Note:
p ^ p = p : Idempotent Law
Example 2: The congruent modulo m p ^ 1 = p or p v 0 = p : Identity Law
relation on the set of integers i.e. {<a, p ^ (pvq) = p or p v (p^q) = p :
b>| a b (mod m)}, where m is a Absorption Law
positive integer greater than 1, is an
equivalence relation.

86. Set A = {integer numbers}, which

is antisymmetric
A. R = {(a,b) | a > b}
B. R = {(a,b) | a + b = 3}
C. R = {(a,b) | a - b = -4}
D. R = {(a,b) | a = b or a = -b}

Note:
Definition(antisymmetric relation): A
relation R on a set A is called
antisymmetric if and only if for any a,
and b in A, whenever <a, b> R , and
<b, a> R , a = b must hold.
Equivalently, R is antisymmetric if and
only if whenever <a, b> R , and a b ,
<b, a> R . Thus in an antisymmetric
relation no pair of elements are related
to each other.
90. Determine which of the given
Example 7: The relation < (or >) on
any set of numbers is antisymmetric. So
is the equality relation on any set of
numbers.

87. Which of the following relations

from Set A = [1,2,3,4] to Set A is
considered transitive?
Ans. {(1,1),(1,2),(2,1)}
relations on the set of all integers is an
88. A U A’ = U antisymmetric relation where (x, y) is
Ans. Complement Law an element of R.
A. x is not equal to y
B. x is greater than or equal to y2
C. x is a multiple of y
D. xy is greater than or equal to 1

91. Determine which of the given 95. Registers AX, BX and CX contain
relations on the set of all integers is an the following values respectively:
equivalence relation where (x, y) is an 1234h, 5678h and 9ABCh.
element of R. What is the result of the instruction
A. x is a multiple of y SHRD BX, CX, 8
B. x greater than or equal to y2 A. 9A78h
C. x = y2 B. 9A56h
D. x and y are both negative or both C. 2345h
nonnegative D. BC56h (MICROPROCESSOR
BOOK PAGE 118)
92. Machine code: 0FAC CB08

93.

96. SETNZ AL
If the zero flag indicates an NZ
condition (zero flag is clear), register
AL is set to 01H.
94. SHLD AX, BX, 4 Otherwise, AL is set to 00H.
AX= 1234H BX= 5678H
Ans. 2345H Machine Code: 0FA4 97. What is the result of NEG AX if
AX contains FFECh?
Ans. 0014h Machine Code: F7D8h

98. Result of executing RCR AX, CL if

D804 CL contains 2 and AX contains
ABCDh
Ans. AAF3 Machine Code: D3D8 B. 1001
C. 1100
D. 1000
Solution:

99. Result of executing RCL DL, 1; +7 -> 0 0111

cleared flags; DL contains 93h -7 -> 1 1000
Ans. 26h Machine Code: D0D2 + 1
1 1001
100. Machine code ROL BYTE
PTR[SI], 1
Ans. final value = 82H → D004 (1101
0000 0000 0100)

101. ROR AX, 1

Ans. 4FA5H Machine Code: D1C8

102. Machine code XOR AX, CX

Ans. 31C8 or 0011 0001 1100 1000

BASE N OPERATIONS 106. The 2’s complement representing

the value -12 is
103. 10110 - 01101 using 1’s A. 1110
complement B. 10100
Ans. 1001 C. 10011
1’s complement of subtrahend: D. 10101
01101 -> 10010
11 Sign magnitude +12: 0 1100
10110 11
+ 10010 1 0011
1 01000 (overflow, add 1 to result) + 1
+ 1 1 0100 (-12)
01001
If no carry, 1’s complement the ans. 107. 1st Complement subtraction
and place a negative sign to the result
104. Perform the binary division
1111 0011 ÷ 1001 to obtain the
quotient.
A. 10101
B. 10111
C. 11011
D. 11101

105. Using 2’s complement, what is the

binary equivalent of -7?
A. 1111
 Matrix: abc
108. The binary value 0111 represent a a101
decimal value of 1 in this decimal code b001
Ans. 8 4 -2 -1 c111
A. Simple directed graph with 3
Note: vertices
For other coding, we replace the 8 4 2 B. Pseudograph with 3 vertices
1 with other values. C. Directed multigraph with 3 vertices
We know that 0111 in decimal is 7 D. Simple multigraph with 3 vertices
because of the common 8 4 2 1 coding.

8(0) + 4(1) + 2(1) + 1(1) = 7

In this case, we replace it by 8 4 -2 -1.

8(0) + 4(1) - 2(1) - 1(1) = 1

109. The 2-4-2-1 code of 7 is:
Ans. 1101
Note:
We can see that 2 + 4 + 1 will make 7
so we multiply them by 1. The 2 in the
most significant bit has more priority
than the other.
2(1) + 4(1) + 2(0) + 1(1) = 7
112. The adjacency matrix of the graph
is seen below, determine how many
edges are in the graph.
Ans. 10
Note: count all the non-zeros to get the
no. of edges

Therefore 7 is 1101 in 2-4-2-1 code. 113. Give the adjacency matrix of the
graph G {a,b,c,d}, How many number
GRAPH / MATRIX QUESTIONS of paths from a to d has a length
exactly equal to 4?
110. Determine in-degree in vertex b? 0 1 1 0
Ans. 5
1 0 0 1
Matrix: abcd 1 0 0 1
a0230
b1221 0 1 1 0
c2110 Ans. 8
d1002

in-degree: add vertically, 5

out-degree: add horizontally, 6

111. Which of the ff correctly describes

the graph
 Ans. f-1 degree

114. The graph is represented by the 118. How many pass will it take in
adjacency matrix below. Determine the order to sort the single digit array 3 5 4
out-degree in vertex d 1 2 using selection sort?
A. 5
B. 4
C. 6
D. 10
Ans. 3 Note: For Bubble Sort
115.
V = {a,b,c,d,e},
E = {(a,b),(a,c),(b,c),(c,d),(c,e),(d,e)} is
classified as?
A. Hamiltonian but not Eulerian
B. neither H or E
C. H and E
D. E but not H (Eulerian cycle but
not Hamiltonian)

116. Given the undirected graph V =

{a,b,c,d,e} with
E = {(a,b).(a,d),(b,c),(c,d),(d,e)} is
classified as?
Ans. Eulerian Path

Note:
Eulerian circuit - visits every edge
exactly once and starts and ends on the
same vertex
Hamiltonian path - visit every vertex
only once
119. Given the following points below,
what is the longest/shortest route?
117. Which of the ff vertex is called a
pendant? Gr to SW 113 mi Gr to Kal 56 mi
Gr to Det 147 mi Gr to Tol 167 mi Ans. eulerian cycle
Kal to SW 137 mi Kal to Det 135 mi
Kal to Tol 133 mi Tol to Det 58 mi
Tol to SW 142 mi Det to SW 98 mi

A. Det- Tol- Kal- GR-Sw – Det -

SHORTEST
B. Det – Tol-Gr-Kal-Sw-Det
C. Det-GR-Sw-Tol-Kal-Det -
LONGEST
D. Det-Sw-Tol-GR-Kal-Det

121. What kind of graph? EULERIAN

PATH - 2 ODD VERTICES

120. What kind of graph?

122.
Ans. 8 x 8 127. 5.What is the canonical form of
the simplified function
K-MAP QUESTIONS F = C ‘D + ABC ‘+ ABD ‘+ A ‘B ‘D
A. M (0,1,2,3,5,9,11,12,14)
123. F = xy + x’z express as product of B. M (1,3,4,5,6,7,9,10,12,14,15)
maxterms C. M (0,2,4,6,7,8,10,11,15)
Ans. M(0,2,4,5) D. M (1,3,5,9,12,13,14)

124. 128. Determine the canonical form of

The complement of F = [x(y’z’ + yz)] the simplified Boolean expression
F = x‘y‘z + xy
A. m (0,5,7)
B. m (2,4,7)
C. m (2,3,7)
D. m (1,6,7)

129. Determine the canonical form of

the simplified Boolean expression
125. Simplify the Boolean function to a
F=x‘y‘z‘ + xz
minimum number of literals
A. m (0,5,7)
A B C T1
B. m (2,4,7)
0 0 0 1
C. m (2,3,7)
0 0 1 1
D. m (1,6,7)
0 1 0 1
0 1 1 0
130. Determine the canonical form of
1 0 0 0
the simplified Boolean expression
1 0 1 0
F2 = xy‘z‘ + x‘y
1 1 0 0
A. m (0,5,7)
1 1 1 0
B. m (2,4,7)
C. m (2,3,4)
A'(B' + C')
D. m (1,6,7)
A + BC
A'B + C
131. Simplify the Boolean function.
ABC + A'B'C'
A B C T
126. Simplify F(v, w, x, y, z) = Σm (0, 0 0 0 1
1, 2, 4, 5, 8, 9, 10, 12, 16, 17, 18, 20,
21, 24, 26, 29) using Karnaugh map. 0 0 1 1
A. v’w’y’ + v’x’z’ + vxz + v’y’z’ +
0 1 0 1
v’x’y’ + vxy’z
B. w’y’ + x’z’ + v’y’z’ + v’x’y’ + 0 1 1 0
vxy’z
1 0 0 0
C. none of the choices
D. vw’y’+ v’x’z’ + vxz + v’y’z’ + 1 0 1 0
v’x’y’ + v’xy’z
1 1 0 0
 1 1 1 0

Ans. T=A’B’C’+A’B’C+A’BC’

132. Express the function below as a

standard form product of maxterms.
F = xy + x'z
A. (x + y + z)(x + y' + z)(x' + y + z')
B. (x + y + z)(x + y' + z)(x' + y + z)
C. (x' + y)(x + z)(y + z)
D. (x + y + z)(x + y' + z)(x' + y + z)(x'
+ y + z'

133. Express the following function as

a sum of minterms: (xy + z)(y + xz)
A. x’yz + xy’z + xyz’ + xyz
B. x’y’z + xy’z + xyz
C. x’yz + x’y’z + xyz’+ xyz
D. x’y’z + xyz’ + x’y’z’

135. Simplify the Boolean function to a

minimum number of literals.
A B C T2
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
134. Reduce the Boolean expression 1 1 1 1
W’X(Z’ + Y’Z) + X(W + W’YZ) to 1 A + BC
literal ABC + A'B'C'
A. X A'(B' + C')
B. W AB + C
C. Z
D. Y Solution:

A\BC 00 01 11 10
0 0 0 1 0
1 1 1 1 1

136. Simplify the Boolean function

F(A,B,C,D) =
m(0,2,3,5,7,8,10,11,13,15)
B'C + CD + BD c. CF=1; AF=0; ZF=0; SF=0;
B'D' + BD + B'C PF=1
B'D' + BD + A'C'D d. CF=1; AF=1; ZF=1; SF=1;
A'B'D' + AB'D' + CD PF=1
e. None of the choices
137. A decoder with an enable input f. CF=1; AF=0; ZF=0; SF=1;
can function as PF=1
Ans. Demultiplexer

138. If the removal of any literal from

an implicant P results in a product term
that is not an implicant of the function 144. It is the most significant of the 32-
then P is a/an _______ bit designs done by Motorola,
Ans. Prime implicant introduced in 1979 and was
widely known, had 32-bit registers in
its programming model but used 16-bit
139. Which flag is set when the result internal data paths.
of an unsigned arithmetic operation is A. MC68000
too large to fit into the destination? B. MC68030
Ans. Carry Flag C. MC68010
D. MC68020
140. What circuit technology is
preferable in systems requiring low 145. Motorola introduced this
power consumption? microprocessor in 1978, an ambitious
Ans. CMOS and thought-through 8-bit design
source compatible with their previous
141. This specifies the number of loads design and was implemented using
that output of a gate can drive without purely hardwired logic.
compromising its performance? A. MC6800
Ans. Fan-out B. MC6815
C. MC6808
142. D. MC6809

143. 2.Simulate the given instructions

(below) and determine which among
the choices is correct.
Initially CF=0; AF=0; ZF=0; SF=0;
PF=0.
MOV AL, D6
MOV BL, E5
ADD AL, BL
a. CF=1; AF=1; ZF=0; SF=1;
PF=0
b. CF=1; AF=1; ZF=0; SF=0; 146. Pentium
PF=1 Choices: [parallel…,three floating…, U
and V pipelines…,ten floating..,]
Ans. U and V pipelines yata
146. a state where the data requested
for processing by a component or
application is not found in the cache
memory.
Ans. Cache miss
147. Pentium
Choices:[pipeline, shutdown, halt, may
isa pa]
Ans.
148. (AB+C) (B+C’D) to minterm
Ans.
Choices:[General purpose registers,
control unit, ALU, memory]
Ans. memory(?), ‘di ko sure kung
may none sa choices
Note:
Study parts of a Microprocessor,
Microcontroller, CPU
152. BCD 431 packed
Ans. 0100 0011 0001
Note:
Study BCD packed and unpacked
153. How many 4 digit binary adder to
create a 4 bit binary multiplier (not sure
pero basta parang ganyan)
Choices:[1,4,3,2]
Ans.

154.
When is it false?
149. what is a RISC design? Ans. every x, P(x) is true
Choices:
[PowerRISC, PowerPC, PowerLaptop, 155. ENIAC
none] Ans. Large Brain (Great Brain ‘di ko
Ans. PowerPC sure kung meron sa choices, Large
brain lang naaalala ko)
150.
MOV AL, AE 156. Which is not a program transfer
MOV BL, 9A instruction?
SUB AL,BL Choices:[ADD, CMPS, SHL]
Flags: SF=0 CF=0 ZF=0 IF=0 Ans. ADD (aralin nalang lahat ng
Ans. program transfer para masagutan
‘to)
151. MOV CX, 7, what machine code?
Ans.

152. Not included in microprocessor?