Too

Many Macros too easy to deal

Lakshmi Chaya Kandula, Vijesh Devan, Gaurav Ganeriwal, Sreedeep Sundaran

Broadcom
Synopsys,
Bangalore, India

www.broadcom.com
www.synopsys.com

ABSTRACT
Modern SoC designs have several complexities and one of the major challenges we see in our
designs is the number of macros we deal with. Optimal macro placement is critical in achieving
good quality of results. Manually placing such macros can be very iterative and it requires large
engineering efforts to get to design closure.
There are multiple issues that we need to deal with while placing the macros. Achieving optimal
channel size of the macros, connectivity of macros with modules to meet timing goals, dealing
with high percentage of macros which makes looking at multiple cost functions such as timing,
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congestion etc challenging, amount of iterations(runtime-cycles) to get to a good QoR with

manual efforts. In our designs we see blocks with several hundreds of macros and we get to deal
with each of the above issue. This paper talks about how IC Compiler II automatic macro
placement helped meet our design goals on blocks which were macro intensive.

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Table of Contents
1. Introduction .......................................................................................................................................................................... 4
2. Design details ........................................................................................................................................................................ 4
3. Flow ........................................................................................................................................................................................... 4
4. Results ...................................................................................................................................................................................... 9
5. Conclusions ......................................................................................................................................................................... 13
6. References ........................................................................................................................................................................... 13

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1. Introduction
Today’s complex SoCs have several design challenges and one of them is to arrive at an optimal macro
placement. Manually placing the several hundreds of macros can be very iterative and error prone
and it can lead to an increase in the turn-around time. There are multiple cost functions that the
designers needs to keep in mind while placing the macros like channel spacing for the macros,
connectivity of the macro with other logic modules etc. in order to achieve good QoR. At lower
technology nodes there are added restrictions on the macro placement which adds to the complexity
of doing manual macro placement. In this paper we discuss on how we leveraged the IC Compiler II’s
automatic macro placement capability to achieve good QoR and reduce the turn- around time on
macro intensive blocks.

2. Design details
Design1:
Instance Count: ~1.5M
Technology: 16FF
Frequency: 700Mhz
Number of hard macros: 370
Number of scenarios: 4 (2 setup and 2 hold)
Number of clocks: 4

Major challenges:
• Macro intensive design
• Channel congestion
• Large turn-around time
• Timing closure

3. Flow
Macro placement flow diagram:

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Defining macro placement

options and constraints

Macro Placement

Analyzing QoR

NO
QoR ok?

Yes

place_opt flow

Analyzing QoR

NO
QoR ok?

Yes


CTS and Routing

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Macro Placement flow commands ICCII:

#### Macro Placement Constraints ####

set_macro_constraints -allowed_orientations R0 [get_cells -hierarchical -filter "is_hard_macro==true"]
set_app_options -name plan.macro.macro_place_only -value true
#### DFA Placement####
set_app_options -list {plan.place.trace_mode dfa}

#### Macro Placement ####

create_placement -floorplan

#### Fix the macro placement####

set_placement_status fix [get_cells -hierarchical -filter "is_hard_macro==true"]

#### Auto blockage creation on channels ####

set_app_options -name place.floorplan.sliver_size -value 60um
derive_placement_blockages
set_attribute [get_placement_blockages auto*] blockage_type soft

#### Standard cell placement ####

create_placement –timing_driven –congestion –congestion_effort high

#### Generate Congestion Map ####

route_global –congestion_map_only true

#### Placement Flow ####

place_opt

#### Incremental Macro Placement####

create_placement –floorplan -incremental

We started with the vanilla macro placement flow as a reference and then evaluated three different
macro placement flows using IC Compiler II for achieving the best QoR.
• Flow1: Vanilla macro placement flow.
• Flow2: DFA based macro placement.
• Flow3: DFA based macro placement + incremental macro placement post place_opt.
• Flow4: Manual macro placement.

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Flow1 Flow2 Flow3

IC Compiler II IC Compiler II IC Compiler II

DFA based macro DFA based macro

Vanilla macro
placement placement
placement

place_opt place_opt
place_opt

QoR Analysis QoR Analysis QoR Analysis

Incremental
Macro Placement

3.1.1: Macro Placement controls

ICC II has several options to further control and refine the macro placement based on specific design
requirements. Some of them are highlighted below:

(i) To control macro placement constraints

set_macro_constraints –allowed_orientation –preferred_location

(ii) To control the amount of array packing

plan.macro.auto_macro_array_size none|low|medium|high

(iii) Control on array width and height
plan.macro.auto_macro_array_max_width
plan.macro.auto_macro_array_max_height



(iv) Control on orientation of macros inside an array
plan.macro.auto_macro_array_minimize_channels
pins_in|pins_out|none

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(v) Grouping of macros to be placed together logically/physically.

create_bounds

(vi) Macro keepout margins
create_keepout_margin

(vii) Incremental Macro Placement. Tries to preserve existing placement, tool will move
existing macros to expand congested channels to improve congestion.
create_placement –floorplan –incremental –congestion

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4. Results
Flow1: Vanilla Macro placement results:

Fig1: Vanilla macro placement congestion map

Flow2 : DFA Macro placement

Fig2: DFA Macro placement congestion map

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Flow3 : DFA with incremental macro placement.

Flow 3.1 Unfixed all the lower L shapes macros with high congestion, added a larger keepout
margin on them and performed macro placement incrementally.

Fig3: Incremental macro placement1 congestion map

Flow 3.2 Flow 3.1 plus restricted channels to buffer only blockages with 50% blocked.

Fig4: Incremental macro placement2 congestion map

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Flow4 : Manual macro placement

Fig5: 1st iteration manual macro placement

Fig6: 2nd iteration manual macro placement

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Fig7: Final iteration macro placement

18
16
14
12 Manual Macro Placement
10
8 Automatic Macro
6 Placement
4
2
0
Experiment1 Experiment2 Experiment3
Fig8: Run time comparison (hours) manual vs automatic macro placement

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5. Conclusions
- On macro intensive designs, manual macro placement is iterative and can significantly
increases the overall turn-around time.
- At lower technology nodes additional constraints need to be followed, this makes manual
macro placement tedious.
- IC Compiler II’s automatic macro placement algorithm helps at arriving at an optimal macro
placement quickly which can significantly improve the design closure time.
- Several iterations can be tried to further refine the macro placement as the runtime is really
fast. This also ensures that we can further improve on the overall design QoR

6. References
[1] IC Compiler II Update Training Slides
[2] IC Compiler II User Guide.

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Too Many Macros Too Easy to Deal