Power management is a significant factor in the design of present technology electronics.

In almost all
applications that use battery as a voltage supply, they require methods that lengthen or increase the
overall battery life. In today’s applications there are increasing number of electronic components used
for portable applications in a microchip and designers consider having a power management block such
as a low dropout regulator. An LDO can be used for any application that utilizes a constant supply
voltage. A high performing LDO should be able to produce a stable output voltage, should have a fast
transient response, and high power efficiency, smaller silicon area is a must for System-on-Chip
applications.

In terms of transient response, a capacitorless LDO suffers from large overshoot and undershoot voltage
whenever the load varies from no load to full load. When the system is inactive, it requires all units in
the system to shut down including the LDO. The LDO should be able to start-up fast enough, while
maintaining low overshoot and undershoot voltage. Excessive overshoot results in system latch-up, thus
making the transient response a vital part of the LDO’s performance.

In a conventional LDO, a large output capacitor is usually required in order for the system to have a good
transient response. Since this capacitor is large, it is usually incorporated as an off-chip capacitor which
requires it to have an external pin for the off chip capacitor. For the removal of the off-chip capacitor
and reduce the size of the overall system, a capacitor-less LDO can be implemented. In order to
compensate for the removal of the off-chip capacitor techniques that improve transient response are
required. Moreover, downscaling the large the power supply voltage in advanced CMOS technologies
has considerably challenged the LDO regulators.

There are many ways of improving the transient response of LDOs such as improving the loop stability of
the system and having a high slew rate error amplifier.The technique discussed in this paper for
improving the transient response is through increasing the slew rate at the gate of the pass transistor of
the LDO. In order to achieve this, a high slew rate error amplifier is applied to the LDO. This
improvement reduces the voltage spikes in the system as discussed in various studies. The error
amplifier used in this study is a recycling folded cascade error amplifier which has a high slew rate while
maintaining good characteristics of an error amplifier.
2. high slew rate error amplifier.

a conventional folded cascade is shown in figure. A conventional folded cascade also has a high slew
rate which can be used for this study. In this study, the researchers chose an improvement of the folded
cascade which has a much higher slew rate than the folded cascade. The recycling folded cascade is
shown in figure .

In a folded cascode. The transistors that conduct the most current have the largest transconductance is
M3 and M4. However their role is just to act as a folding node for the small signal current generated by
transistor M1 and M2. The input transistors M1 and M2 are halved to carry equal currents. The same is
done for M3 and M4 but their current mirror aspect ratio has a value of equal to K. Transistors M5 and
M6 have a similar aspect ratio as M11 and M12 to ensure that the drain potentials of the current mirror
are the same to achieve proper matching.

The slew rate factor is increased by a factor of K thus improving the charging and discharging of the pass
transistor which results in the reduction of overshoot and undershoot voltage significantly. The slew rate
of the traditional folded cascode error amplifier is expressed as: while the slew rate of the recycling
folded cascode amplifier is denoted as: Ib is represents the bias current that flows into the load
capacitor CL which is the equivalent capacitance at the gate of the pass transistor.
Simulation results

The Proposed LDO is simulated in TSMC 65nm CMOS technology using synopsys custom tool.

A. Load regulation the Load Regulation is described by the following equation,