Amplifiers Frequency Response Examples

ECE 5/415 − Analog IC Design

We will use the following MOSFET parameters for hand-calculations and the 1 µm CMOS models
for corresponding simulations.

Table 1: Long-channel MOSFET parameters.

Parameter NMOS PMOS

Scale factor (Lmin ) 1 µm
VDD 5V
VT HN and |VT HP | 0.8 0.9
µA µA
KPn and KPp 120 V2
40 V2
Bias Current, ID 20µA 20µA
gmn and gmp 150 µA
V
150 µA
V
Vov ∼ 2I
= D gm
250mV 250mV
W/L 10/2 30/2
VGS and VSG 1.05V 1.15V
ron and rop 5M Ω 4M Ω
0 ox fF
Cox = tox
1.75 µm2
Coxn and Coxp 35 f F 105 f F
Cgsn and Csgp 23.3 f F 70 f F
Cgdn and Cdgp 2 fF 6 fF
fT n and fT p 900 M Hz 300 M Hz

Pole-splitting Equations
The pole-splitting equations were derived for a second-order amplifier in class using the circuit model
shown in Fig.

Figure 1: Second-order amplifier model used for analyzing pole-splitting.

1 1
fp1 = 2πR1 [C1 +(1+gm2 R2 )Cc ]+R2 (C2 +Cc ) ≈ 2πgm2 R2 R1 Cc

R1 (1+gm2 R2 )Cc +R1 C1 +R2 (Cc +C2 ) gm2 Cc gm2

fp2 ≈ 2πR1 R2 [C1 Cc +C1 C2 +Cc C2 ] ≈ 2π(C1 Cc +C1 C2 +Cc C2 ) ∝ 2πC2

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 Amplifiers Frequency Response Examples

1
fz = 1


2πCc gm2 −Rz

gm1
fun = Av fp1 = 2πCc

Example 1: Common Source Amplifier

Determine the gain, magnitude, and phase shift of the amplifier shown in Figure 2 below.
For high-frequency small-signal analysis, the Cbig − Rbig network exhibits a high-pass frequency

Figure 2

response which allows the input signal at frequencies ωin  Rbig1Cbig to be applied to the amplifier.
At DC, or frequencies  Rbig1Cbig , the capacitor ’DC blocks’ the AC input so that the VGS for
the NMOS M1 is set by the current source. This is an example of ’AC-coupling’ of the input to
the amplifier circuit. Similarly, the output can also be ’DC-blocked’ by placing a large capacitor in
series with the output node (not shown here).
The estimated low-frequency gain of the circuit is Av = −gm1 ·ro1 ||ro2 = −150 µA
V ·(5M Ω||4M Ω)=333,
which in dB scale is 20log10 (333) = 50.45dB.
Since there are two ’high-impedance’ nodes in this circuit, which interact through the Miller capac-
itance (Cgd1 ), we expect two low-frequency poles. We say ’low-frequency poles’, as eventually all
MOSFETs will lead to corresponding poles at higher frequencies due to parasitic capacitances and
the resulting fT limitation.
As per the model in Fig. 1, we have R1 = 100Ω, R2 = ro1 ||ro2 = 2.22M Ω.
C1 = Cgs1 = 23.3f F , CC = Cgd1 = 2f F , and C2 = Cdg2 = 6f F .
gm1 = 1
Rs = 1
100k = 100 µA
V (Norton equivalent of the Thevenin input source).
gm2 = 150 µA
V .

We will use pole splitting equations to determine the poles and zeros:
1
fp1 ≈ 2πgm2 R2 R1 Cc = 2.39M Hz
fp2 ≈ 2π(C1 Ccg+C
m2 Cc
1 C2 +Cc C2 )
= 240M Hz
gm2
fz = 2πCc = 11.94GHz
Compare these calculations with the simulation results in Fig. 3. Here, the phase margin is roughly
35ř.

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 Amplifiers Frequency Response Examples

Figure 3: (left) schematic for simulation, (right) simulated frequency response.

Example 2: Common Source Amplifier with Miller Compen-

sation
Determine the frequency response of the amplifier shown in Figure 4 below.

Figure 4

This circuit is same as the previous example, except for the additional Miller cap of 1pF .

Again, the low-frequency gain of the circuit is 50.45dB. The second-order amplifier model is modified
so that we have C2 = CC + Cdg2 ' 1pF .
Again, using the pole splitting-equations, we get:
1
fp1 ≈ 2πgm2 R2 R1 Cc = 4.78kHz
fp2 ≈ 2π(C1 Ccg+C
m2 Cc
1 C2 +Cc C2 )
= 811M Hz
gm2
fz = 2πCc = 23.82M Hz
and
gm1
fun = 2πCc = 1.59M Hz
Compare these calculations with the simulation results in Fig. 5. Here, the phase margin is improved
and is roughly 85ř (actually overdamped) and the unity-gain (aka gain-crossover) frequency is fun =

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 Amplifiers Frequency Response Examples

1.59M Hz. We can see that after Miller compensation, the frequency response looks similar to that
of a first-order sytem near fun .

Figure 5: (left) schematic for simulation, (right) simulated frequency response.

Example 3: Two-Stage Amplifier

Determine the frequency response of the amplifier shown in Figure 6 below.

Since there are two ’high-impedance’ nodes in this two-stage amplifier, we expect two low-frequency

Figure 6

poles. Note that the input cap of M1 (i.e. Cgs1 ) will not contribute a pole as the source impedance
is zero. As per the model in Fig. 1, we have R1 = ro1 ||ro2 = 2.22M Ω, and R2 = ro3 ||ro4 = 2.22M Ω.
C1 = Cgd1 + Cdg2 + Cgs3 = 2f F + 6f F + 23.3f F = 31.3f F . Note that these are approximated
values, you can get more accurate values from Spectre for a well characterized process.
CC = 1pF + Cgd1 ≈ 1pF , and
C2 = CL + Cdg4 = 100f F + 6f F = 106f F .
gm1 = gm2 = 150 µA
V .

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 Amplifiers Frequency Response Examples

The estimated low-frequency gain of the circuit is Av = gm1 R1 gm2 R2 = (150 µA 2

V · (5M Ω||4M Ω)) ,
which is 2 × 20log10 (333) = 100.9dB.

Using pole splitting equations, we determine the poles and zeros:

1
fp1 ≈ 2πgm2 R2 R1 Cc = 215kHz
fp2 ≈ 2π(C1 Ccg+C
m2 Cc
1 C2 +Cc C2 )
= 170M Hz
gm2
fz = 2πCc = 23.8M Hz
and
gm1
fun = 2πC c
= 23.82M Hz
Compare these calculations with the simulation results in Fig. 5. Here, the phase margin is roughly
0ř due to the RHP zero closer to the fun . This can be improved by eliminating the RHP zero by
using a zero-nulling resistor (not shown here).

Figure 7: (left) schematic for simulation, (right) simulated frequency response.

Example 4: Cascode Amplifier

Determine the frequency response of the amplifier shown in Figure 8 below.
2
The low-frequency gain of the circuit is Av = gm1 · gmp rop 2
||gmn ron = 150 µA
V · (3.75GΩ||2.4GΩ),

which is 20log10 (219000) = 106.8dB.

Here, we have three high-impedance nodes, and Cgd1 will experience Miller-effect due to inverting
gain from node A to X. M2 is a common-gate device and will provide capacitive isolation between
nodes A-X and Y (i.e. no Miller cap between X and Y). We can use either Miller approximation or
pole-splitting equations to find the poles at nodes A and X.

Let’s first observe the gain from node A to X, Av,AX . Using the Av = −Gm Rout lemma discussed
in class (and in the textbook), we have Gm = gm1
and Rout = ro1 ||RM 2s , where RM 2s is the impedance looking up the source of M2 .
Recall that we derive RM 2s in the class (for common-gate amplifier) as:
RD 1
RM 2s = (gm2 +g mb2 )ro2
+ gm2 +gmb2
.
2
Here, we have RD ' gm3 ro3 ro4 = gmp rop . Ignoring body-effect, we get

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 Amplifiers Frequency Response Examples

Figure 8

2
gmp rop 1 1
RM 2s = gmn ron + gmn ≈ rop , as we have gmn = gmp and rop ≈ ron (not gm2 looking into the
source of M2 as a common misconception would suggest!) .
This eventually results in Rout = rop ||ron , resulting in Av,AX = −gm1 · rop ||ron = 333. This
gain is large and thus can lead to erroneous results if Miller approximation was used (only moderate
Miller Killer effect here, unlike in the class notes).

Using pole splitting equations, we determine the poles and zeros at nodes A and X (Note that we
used Miller approximation in the class notes):
RA = 100k, RX = rop ||ron = 2.22M Ω, CA = Cgs1 ≈ 23.3f F , CX = Cgd1 + Cgs2 ≈ 25.3f F ,
Cc = Cgd1 = 2f F
1 µA
gmA = RA , and gmX = gm1 = 150 V
fp1 ≈ 2πgmX R1X RA Cc = 2.4M Hz
gmX Cc
fp2 ≈ 2π(CA Cc +C A CX +Cc CX )
= 70M Hz
gmX
fz = 2πCC = 11.93GHz

Further, due to capacitive isolation, the pole at Y can be directly determined from the output
time-constant (RY CY ):
2 2
RY = gmp rop ||gmn ron = 3.75GΩ||2.4GΩ = 1.46GΩ,
CY = CL + Cgd2 + Cdg3 = 100f F + 3f F + 6f F = 109f F .
1
fp3 ≈ 2πRY CY = 1kHz
Compare these calculations with the simulation results in Fig. 3. Here, the location of fp3 , the
dominant or low-frequency pole, was accurately estimated. However, the locations of fp1 and fp2 are
slightly off as these two poles are closely interacting with each other and thus test our pole-splitting
approximations.
Note that a very large (100GΩ) resistor is used for biasing in Fig. 9 , otherwise the simulated gain
in Fig. 9 will be off from the estimated value. This is a precaution to be used when dealing with
very high-impedance nodes in the circuits (Rout = 1.46GΩ) and even 1GΩ in parallel can reduce

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 Amplifiers Frequency Response Examples

the expected gain. In practice, however, we use a diffamp for the first stage for ’easy biasing’ using
a tail current source, or inductor-based biasing networks for bandpass amplifiers at RF/microwave
frequencies.

Figure 9: (left) schematic for simulation, (right) simulated frequency response.

References
[1] R. J. Baker, CMOS Circuit Design, Layout and Simulation – R. J. Baker, 3rd Edition, Wiley-
IEEE, 2010.[2]