A B C D E

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1 1

QHRAE
2
Superior 10AS/10ASG 2

LA-7213P REV 1.0 Schematic

3
AMD Llano FS1 Processor / Hudson M2/M3 3

Whistler Pro
2011-04-30 Rev 1.0

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 1 of 51
A B C D E
 A B C D E

EC SMBus HDMI-CEC
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PWM Fan
page 30 PCI-Express X4 5GHz AMD APU page 5
HDMI Conn.
VGA HDMI
FS1 Processor
page 30
Memory BUS(DDRIII)
1 200pin DDRIII-SO-DIMM X2 1
PCI-Express X16 5GHz Llano uPGA-722 Dual Channel page 10,11
35mm*35mm
BANK 0, 1, 2, 3
1.5V DDRIII 1066/1333 MT/s
page 5,6,7,8

DP0, DP1 DP1

LVDS Translator (X2) (X4) PCIe X1 X1 USB/B Right Left USB
UMI X4 1.1V 5GT/s
AMD GPU ANX3110 2.5GT/s USB port 0,1 USB port 2
page 31 page 31
AMD Whistler PRO, 128bit with 1GB/2GB DDR3 page 27
PCIe X1
AMD Whistler LP, 128bit with 1GB/2GB DDR3 1.1V 5GT/s USB 3.0 Int. Camera
(Design Ready) USB port 10 USB port 5
USB page 35 page 28
FCBGA-962 VGA eDP LVDS Conn.
29mm*29mm 5V 480MHz
page 12,13,14,15,16,17,18,19,20,21 page 28

PCIeMini Card
2
USB WLAN 2

5V 480MHz
VGA CRT CRT
USB port 8 PCIeMini Card
page 29 page 32
APU PCIe port 1
JET APU PCIe port 2
AMD FCH page 32 page 32

RTL8105E 10/100M Hudson M2/M3

RJ45 SATA port 0 SATA HDD
page 34
RTL8111E 1G 5V 6GHz(600MB/s) SATA port 0
APU PCIe port 0 page 31
page 33 SATA port 2 2nd HDD
5V 6GHz(600MB/s) SATA port 2
FCBGA-656 SATA port 1 SATA ODD page 31
24.5mm*24.5mm
5V 6GHz(600MB/s) SATA port 1
page 31
Cardreader PCIe X1
JMB389C 1.1V 5GT/s
USB 3.0 port0 USB 3.0
FCH PCIe port2 page 22,23,24,25,26 5GHz USB3.0 port0
page 34 page 35
3
PCIe X1 USB3.0 3
SPI Bus 1.1V 5GT/s UPD720200AF1-DAP-A
3.3V 33 MHz FCH PCIe port1
page 36
LPC Bus HD Audio 3.3V 24MHz
3.3V 33 MHz
TP& Light Pipe/B
LS-6061P page 39 HDA Codec
ALC269
Cap Sensor SPI ROM Debug Port ENE KB930 page 36
page 38 page 37
& Light Sensor/B (2MB)
page 24
RTC CKT. LS-6062P page 39
page 22
Touch Pad Int.KBD EC ROM CIR G-Sensor Int. SPK Conn JPIO
page 37
LED/B page 40 page 38 page 39 page 38 MIC Conn (HP &page
MIC)
DC/DC Interface CKT. LS-6063P page 39
(128KB)
page 38
page 36 36

page 40 EC SMBus
Audio & USB/B
4 4

Power Circuit DC/DC LS-6064P page 31

page 41,42,43,44,45,46
47,48,49
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

Power On/Off CKT. Power/B_FPC THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
page 39 DA300006JM0 page 39 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8 B

Date: Monday, July 04, 2011 Sheet 2 of 51

A B C D E
 5 4 3 2 1

B+
Ipeak=5A, Imax=3.5A, Iocp min=7.9A
DESIGN CURRENT 0.1A
DESIGN CURRENT 0.1A

DESIGN CURRENT 5A
+3VL
+5VL

+5VALW
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SUSP

N-CHANNEL DESIGN CURRENT 4A +5VS

SI4800
KB_LED
DESIGN CURRENT 400mA +5VS_LED
P-CHANNEL
D AO-3413 D

+5VS
DESIGN CURRENT 300mA +3VS_HDP
LDO
G9191
ODD_PWR
TPS51125A DESIGN CURRENT 1.6A
P-CHANNEL
+5VS_ODD
AO-3413

Ipeak=5A, Imax=3.5A, Iocp min=7.7A DESIGN CURRENT 5A +3VALW

WOL_EN#

P-CHANNEL DESIGN CURRENT 330mA +3V_LAN

AO-3413

SYSON
DESIGN CURRENT 0.2A +3V
P-CHANNEL
AO-3413
GPU_PWREN
DESIGN CURRENT 1.65A +1.8VSG
SY8033BDBC
SUSP

N-CHANNEL DESIGN CURRENT 4A +3VS

SI4800 LCD_ENVDD

C C
P-CHANNEL DESIGN CURRENT 1.5A +LCD_VDD
AO-3413

PXS_PWREN
DESIGN CURRENT 0.3A +3VSG
P-CHANNEL
AO-3413
+3VS

LDO DESIGN CURRENT 1A +2.5VS

APL5508-25DC
POK

Ipeak=5.3A, Imax=3.71A, Iocp min=6.81A DESIGN CURRENT 5.3A +1.1VALW

G5603RU1U
SUSP

N-CHANNEL DESIGN CURRENT 4A +1.1VS

FDS6676AS
VR_ON

Ipeak=50A, Imax=35A, Iocp min=65.21A DESIGN CURRENT 50A +CPU_CORE

ISL6267HRZ-T DESIGN CURRENT 27.5A
B
Ipeak=27.5A, Imax=19.25A, Iocp min=34.92A +CPU_CORE_NB B

VR_ON

Ipeak=6.5A, Imax=4.55A, Iocp min=8.55A DESIGN CURRENT 6.5A +1.2VS

G5603RU1U

SYSON DIS Ipeak=20A, Imax=14A, Iocp min=24.13A

UMA Ipeak=8.5A, Imax=5.95A, Iocp min=10.44A DESIGN CURRENT 20A +1.5V
G5603RU1U SUSP

N-CHANNEL DESIGN CURRENT 2A +1.5VS

FDS6676AS
+3V

LDO DESIGN CURRENT 1A +1.05V

APL5930KAI-TRG

SUSP

DESIGN CURRENT 1.5A +0.75VS

G2992F1U

VGA_PWRGD

N-CHANNEL DESIGN CURRENT 11A +1.5VSG

FDS6676AS
A A
GPU_PWREN

LDO DESIGN CURRENT 3A +1.0VSG

APL5930KAI
VGACORE_EN
Ipeak=32.6A, Imax=20.3A, Iocp min=36.19A DESIGN CURRENT 32.6A +VGA_CORE
RT8237CZQW
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 3 of 51
5 4 3 2 1
 A B C D E

Voltage Rails ( O MEANS ON X MEANS OFF )

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+5VS BTO Option Table
+RTCVCC B+ +5VL +5VALW +1.5V
+3VS
+3VL +3VALW +3V Function HDMI SKU
+2.5VS
+1.1VALW +1.05V
power +1.5VS description HDMI SKU
1 plane +VSB 1
+1.2VS UMA
explain PowerXpress Discrete COMMON CEC UMA PowerXpress Discrete
+1.1VS
+0.75VS BTO IHDMI@ DHDMI@ HDMI@ CEC@ UMA@ UMA@+VGA@+PXS@ VGA@+DIS@
+CPU_CORE
+CPU_CORE_NB
Function LAN CIR KB Light
+VGA_CORE
State
+3VSG description LAN CIR KB Light
+1.8VSG
explain 10/100M GIGA CIR KB Light
+1.5VSG
+1.0VSG BTO 8105E@ 8111E@ CIR@ KBL@

S0 Function G-SENSOR Cam & Mic Panel

O O O O O O
description G-SENSOR Cam & Mic Panel (DIS@)
S1
O O O O O O
explain G-SENSOR Cam & Mic 3D LVDS eDP Non-3D & EDP
2 2
S3
O O O O O X BTO GSENSOR@ CAM@ 3D@+NOEDP@ EDP@ NO3D@+NOEDP@

S5 S4/AC
O O O O X X
Function GPIO for PowerXpress Chipset
S5 S4/ Battery only
O O O X X X description PowerXpress (PXS@) FCH GPU

S5 S4/AC & Battery explain PowerXpress Enable Crossfire Enable Hudson-M3 Whistler Pro
don't exist
O X X X X X
BTO PXSEN@ CROSSEN@ HUDM3R1@ HUDM3R3@ WHPROR1@ WHPROR3@

Function PowerXpress Renesas USB3.0 FCH EC

description PowerXpress (PXS@) Renesas USB3.0 FCH EC

FCH SM Bus Address (SCL0/SDA0)
explain BACO mode Non-BACO Renesas USB3.0 Hudson-M2 Hudson-M3 KB-930 KB-9012
Power Device HEX Address BACO@ NOBACO@ RENE@ M2@ M3@ KB930@ KB9012@
BTO
3 3
+3VS DDR SO-DIMM 0 A0 H 1010 0000 b
+3VS DDR SO-DIMM 1 A4 H 1010 0100 b
+3VS WLAN
+3VS 3G

SIGNAL
STATE SLP_S3# SLP_S5#
EC SM Bus1 Address EC SM Bus2 Address
Full ON HIGH HIGH
Power Device HEX Address Power Device HEX Address S1(Power On Suspend) HIGH HIGH
+3VL Smart Battery 16 H 0001 0110 b +3VS CPU Thermal Sensor 98 H 1001 1001 b
S3 (Suspend to RAM) LOW HIGH
+3VL HDMI-CEC 34 H 0011 0100 b +3VS GPU Thermal Sensor 41 H 0100 0001 b
+3VS G-Sensor 40 H 0100 0000 b S4 (Suspend to Disk) LOW HIGH
+3VS Light Sensor 52 H 0101 0010 b
S5 (Soft OFF) LOW LOW
4
Power Device HEX Address C0 H
4
+3VS 3D - Bootloader 1100 0000 b G3 LOW LOW
+3VL Cap. Sensor Virtual I2C +3VS 3D - Slave C0 H 1100 0000 b

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 4 of 51
A B C D E
 A B C D E

12 PCIE_GTX_C_FRX_P[0..15]

12 PCIE_GTX_C_FRX_N[0..15]
PCIE_FTX_C_GRX_P[0..15] 12

PCIE_FTX_C_GRX_N[0..15] 12
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JAPUA @

PCI EXPRESS
PCIE_GTX_C_FRX_P0 AA8 AA2 PCIE_FTX_GRX_P0 C1 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P0
P_GFX_RXP0 P_GFX_TXP0
PCIE_GTX_C_FRX_N0 AA9 AA3 PCIE_FTX_GRX_N0 C2 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N0
P_GFX_RXN0 P_GFX_TXN0
PCIE_GTX_C_FRX_P1 Y7 Y2 PCIE_FTX_GRX_P1 C3 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P1
P_GFX_RXP1 P_GFX_TXP1
1 PCIE_GTX_C_FRX_N1 PCIE_FTX_GRX_N1 C4 PCIE_FTX_C_GRX_N1 1
Y8 P_GFX_RXN1 P_GFX_TXN1 Y1 1 2 VGA@ 0.1U_0402_16V7K

PCIE_GTX_C_FRX_P2 W5 Y4 PCIE_FTX_GRX_P2 C9 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P2

P_GFX_RXP2 P_GFX_TXP2
PCIE_GTX_C_FRX_N2 W6 Y5 PCIE_FTX_GRX_N2 C22 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N2
P_GFX_RXN2 P_GFX_TXN2
PCIE_GTX_C_FRX_P3 W8 W2 PCIE_FTX_GRX_P3 C23 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P3
P_GFX_RXP3 P_GFX_TXP3
PCIE_GTX_C_FRX_N3 W9 W3 PCIE_FTX_GRX_N3 C24 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N3
P_GFX_RXN3 P_GFX_TXN3
PCIE_GTX_C_FRX_P4 V7 V2 PCIE_FTX_GRX_P4 C25 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P4
For PowerXpress
P_GFX_RXP4 P_GFX_TXP4
PCIE_GTX_C_FRX_N4 PCIE_FTX_GRX_N4 C26 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N4
V8 P_GFX_RXN4 P_GFX_TXN4 V1 1 Place R1 ~ R8 close to C33 ~ C40
PCIE_GTX_C_FRX_P5 U5 V4 PCIE_FTX_GRX_P5 C27 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P5
P_GFX_RXP5 P_GFX_TXP5 PCIE_FTX_GRX_P8 R1 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX2+ 30
PCIE_GTX_C_FRX_N5 U6 V5 PCIE_FTX_GRX_N5 C28 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N5
P_GFX_RXN5 P_GFX_TXN5 PCIE_FTX_GRX_N8 R2 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX2- 30
PCIE_GTX_C_FRX_P6 U8 U2 PCIE_FTX_GRX_P6 C29 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P6
P_GFX_RXP6 P_GFX_TXP6 PCIE_FTX_GRX_P9 R3 1 IHDMI@ 2 0_0402_5%

GRAPHICS
UMA_HDMI_TX1+ 30
PCIE_GTX_C_FRX_N6 U9 U3 PCIE_FTX_GRX_N6 C30 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N6
P_GFX_RXN6 P_GFX_TXN6 PCIE_FTX_GRX_N9 R4 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX1- 30
PCIE_GTX_C_FRX_P7 T7 T2 PCIE_FTX_GRX_P7 C31 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P7
P_GFX_RXP7 P_GFX_TXP7 PCIE_FTX_GRX_P10 R5 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX0+ 30
PCIE_GTX_C_FRX_N7 T8 T1 PCIE_FTX_GRX_N7 C32 1 2 VGA@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N7
P_GFX_RXN7 P_GFX_TXN7 PCIE_FTX_GRX_N10 R6 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TX0- 30
PCIE_GTX_C_FRX_P8 R5 T4 PCIE_FTX_GRX_P8 C33 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P8
P_GFX_RXP8 P_GFX_TXP8 PCIE_FTX_GRX_P11 R7 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TXC+ 30
PCIE_GTX_C_FRX_N8 R6 T5 PCIE_FTX_GRX_N8 C34 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N8
P_GFX_RXN8 P_GFX_TXN8 PCIE_FTX_GRX_N11 R8 1 IHDMI@ 2 0_0402_5% UMA_HDMI_TXC- 30
PCIE_GTX_C_FRX_P9 R8 R2 PCIE_FTX_GRX_P9 C35 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P9
P_GFX_RXP9 P_GFX_TXP9
2 PCIE_GTX_C_FRX_N9 PCIE_FTX_GRX_N9 C36 PCIE_FTX_C_GRX_N9 2
R9 P_GFX_RXN9 P_GFX_TXN9 R3 1 2 DIS@ 0.1U_0402_16V7K

PCIE_GTX_C_FRX_P10 P7 P2 PCIE_FTX_GRX_P10 C37 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P10

P_GFX_RXP10 P_GFX_TXP10
PCIE_GTX_C_FRX_N10 P8 P1 PCIE_FTX_GRX_N10 C38 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N10
P_GFX_RXN10 P_GFX_TXN10
PCIE_GTX_C_FRX_P11 N5 P4 PCIE_FTX_GRX_P11 C39 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P11
P_GFX_RXP11 P_GFX_TXP11
PCIE_GTX_C_FRX_N11 N6 P5 PCIE_FTX_GRX_N11 C40 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N11
P_GFX_RXN11 P_GFX_TXN11
PCIE_GTX_C_FRX_P12 N8 N2 PCIE_FTX_GRX_P12 C41 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P12
P_GFX_RXP12 P_GFX_TXP12
PCIE_GTX_C_FRX_N12 N9 N3 PCIE_FTX_GRX_N12 C42 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N12
P_GFX_RXN12 P_GFX_TXN12
PCIE_GTX_C_FRX_P13 M7 M2 PCIE_FTX_GRX_P13 C43 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P13
P_GFX_RXP13 P_GFX_TXP13
PCIE_GTX_C_FRX_N13 M8 M1 PCIE_FTX_GRX_N13 C44 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N13
P_GFX_RXN13 P_GFX_TXN13
PCIE_GTX_C_FRX_P14 L5 M4 PCIE_FTX_GRX_P14 C45 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P14
P_GFX_RXP14 P_GFX_TXP14
PCIE_GTX_C_FRX_N14 L6 M5 PCIE_FTX_GRX_N14 C46 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N14
P_GFX_RXN14 P_GFX_TXN14
PCIE_GTX_C_FRX_P15 L8 L2 PCIE_FTX_GRX_P15 C47 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_P15
P_GFX_RXP15 P_GFX_TXP15
PCIE_GTX_C_FRX_N15 L9 L3 PCIE_FTX_GRX_N15 C48 1 2 DIS@ 0.1U_0402_16V7K PCIE_FTX_C_GRX_N15
P_GFX_RXN15 P_GFX_TXN15

PCIE_FRX_C_LANTX_P0 AC5 AD4 PCIE_FTX_LANRX_P0 C49 1 2 0.1U_0402_16V7K

33 PCIE_FRX_C_LANTX_P0 P_GPP_RXP0 P_GPP_TXP0 PCIE_FTX_C_LANRX_P0 33
PCIE_FRX_C_LANTX_N0 AC6 PCIE_FTX_LANRX_N0 C50
LAN
33 PCIE_FRX_C_LANTX_N0 P_GPP_RXN0 P_GPP_TXN0 AD5 1 2 0.1U_0402_16V7K PCIE_FTX_C_LANRX_N0 33
3 PCIE_FRX_WLANTX_P1 PCIE_FTX_WLANRX_P1 C51 3
32 PCIE_FRX_WLANTX_P1 AC8 P_GPP_RXP1 P_GPP_TXP1 AC2 1 2 0.1U_0402_16V7K PCIE_FTX_C_WLANRX_P1 32
PCIE_FRX_WLANTX_N1 PCIE_FTX_WLANRX_N1 C52
WLAN
2 0.1U_0402_16V7K
GPP

32 PCIE_FRX_WLANTX_N1 AC9 P_GPP_RXN1 P_GPP_TXN1 AC3 1 PCIE_FTX_C_WLANRX_N1 32

32 PCIE_FRX_JETTX_P2
PCIE_FRX_JETTX_P2 AB7 P_GPP_RXP2 P_GPP_TXP2 AB2 PCIE_FTX_JETRX_P2 C53 1 2 0.1U_0402_16V7K PCIE_FTX_C_JETRX_P2 32
JET
FAN Control Circuit
PCIE_FRX_JETTX_N2 AB8 AB1 PCIE_FTX_JETRX_N2 C54 1 2 0.1U_0402_16V7K
32 PCIE_FRX_JETTX_N2 P_GPP_RXN2 P_GPP_TXN2 PCIE_FTX_C_JETRX_N2 32
AA5 AB4 +3VS
P_GPP_RXP3 P_GPP_TXP3
AA6 P_GPP_RXN3 P_GPP_TXN3 AB5

1
R18
10K_0402_5% JFAN
UMI_MTX_C_FRX_P0 AF8 AF1 UMI_FTX_MRX_P0 C55 1 2 0.1U_0402_16V7K 1
22 UMI_MTX_C_FRX_P0 P_UMI_RXP0 P_UMI_TXP0 UMI_FTX_C_MRX_P0 22 1
FANPWM 2
37 FANPWM

2
UMI_MTX_C_FRX_N0 UMI_FTX_MRX_N0 C56 2
22 UMI_MTX_C_FRX_N0 AF7 P_UMI_RXN0 P_UMI_TXN0 AF2 1 2 0.1U_0402_16V7K UMI_FTX_C_MRX_N0 22 37 FAN_SPEED1 3 3
+FAN1
UMI-LINK

1 4 4
UMI_MTX_C_FRX_P1 AE6 AF5 UMI_FTX_MRX_P1 C57 1 2 0.1U_0402_16V7K C13
22 UMI_MTX_C_FRX_P1 P_UMI_RXP1 P_UMI_TXP1 UMI_FTX_C_MRX_P1 22
0.01U_0402_25V7K ACES_85204-0400N
UMI_MTX_C_FRX_N1 AE5 AF4 UMI_FTX_MRX_N1 C58 1 2 0.1U_0402_16V7K +5VS @ @
22 UMI_MTX_C_FRX_N1 P_UMI_RXN1 P_UMI_TXN1 UMI_FTX_C_MRX_N1 22 2
UMI_MTX_C_FRX_P2 AE9 AE3 UMI_FTX_MRX_P2 C59 1 2 0.1U_0402_16V7K
22 UMI_MTX_C_FRX_P2 P_UMI_RXP2 P_UMI_TXP2 UMI_FTX_C_MRX_P2 22
40 mils
UMI_MTX_C_FRX_N2 AE8 AE2 UMI_FTX_MRX_N2 C60 1 2 0.1U_0402_16V7K 1A
22 UMI_MTX_C_FRX_N2 P_UMI_RXN2 P_UMI_TXN2 UMI_FTX_C_MRX_N2 22 +5VS
1 2 +FAN1 Close to Connector
UMI_MTX_C_FRX_P3 AD8 AD1 UMI_FTX_MRX_P3 C61 1 2 0.1U_0402_16V7K 2 R15 0_0603_5% D7
22 UMI_MTX_C_FRX_P3 P_UMI_RXP3 P_UMI_TXP3 UMI_FTX_C_MRX_P3 22
1 1 2 2

10U_0805_10V6K

1000P_0402_50V7K
UMI_MTX_C_FRX_N3 AD7 AD2 UMI_FTX_MRX_N3 C62 1 2 0.1U_0402_16V7K C10
22 UMI_MTX_C_FRX_N3 P_UMI_RXN3 P_UMI_TXN3 UMI_FTX_C_MRX_N3 22

1
10U_0805_10V6K 1SS355TE-17_SOD323-2 2 1
1 @ D8 C12 C11
+1.2VS 1 2 P_ZVDDP K5 K4 P_ZVSS 1 2
4 R9 196_0402_1% P_ZVDDP P_ZVSS R10 196_0402_1% BAS16_SOT23-3 4
1 2

2
AMD_TOPEDO_FS-1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 5 of 51
A B C D E
 A B C D E

www.qdzbwx.com
10 DDR_A_DQS[0..7] 11 DDR_B_DQS[0..7]

10 DDR_A_DQS#[0..7] 11 DDR_B_DQS#[0..7]

1 1

JAPUB @ JAPUC @

10 DDR_A_MA[0..15] MEMORY CHANNEL A DDR_A_D[0..63] 10 11 DDR_B_MA[0..15] MEMORY CHANNEL B DDR_B_D[0..63] 11

DDR_A_MA0 U20 E13 DDR_A_D0 DDR_B_MA0 T27 A14 DDR_B_D0
DDR_A_MA1 MA_ADD0 MA_DATA0 DDR_A_D1 DDR_B_MA1 MB_ADD0 MB_DATA0 DDR_B_D1
R20 MA_ADD1 MA_DATA1 J13 P24 MB_ADD1 MB_DATA1 B14
DDR_A_MA2 R21 H15 DDR_A_D2 DDR_B_MA2 P25 D16 DDR_B_D2
DDR_A_MA3 MA_ADD2 MA_DATA2 DDR_A_D3 DDR_B_MA3 MB_ADD2 MB_DATA2 DDR_B_D3
P22 MA_ADD3 MA_DATA3 J15 N27 MB_ADD3 MB_DATA3 E16
DDR_A_MA4 P21 H13 DDR_A_D4 DDR_B_MA4 N26 B13 DDR_B_D4
DDR_A_MA5 MA_ADD4 MA_DATA4 DDR_A_D5 DDR_B_MA5 MB_ADD4 MB_DATA4 DDR_B_D5
N24 MA_ADD5 MA_DATA5 F13 M28 MB_ADD5 MB_DATA5 C13
DDR_A_MA6 N23 F15 DDR_A_D6 DDR_B_MA6 M27 B16 DDR_B_D6
DDR_A_MA7 MA_ADD6 MA_DATA6 DDR_A_D7 DDR_B_MA7 MB_ADD6 MB_DATA6 DDR_B_D7
N20 MA_ADD7 MA_DATA7 E15 M24 MB_ADD7 MB_DATA7 A16
DDR_A_MA8 N21 DDR_B_MA8 M25
DDR_A_MA9 MA_ADD8 DDR_A_D8 DDR_B_MA9 MB_ADD8 DDR_B_D8
M21 MA_ADD9 MA_DATA8 H17 L26 MB_ADD9 MB_DATA8 C17
DDR_A_MA10 U23 F17 DDR_A_D9 DDR_B_MA10 U26 B18 DDR_B_D9
DDR_A_MA11 MA_ADD10 MA_DATA9 DDR_A_D10 DDR_B_MA11 MB_ADD10 MB_DATA9 DDR_B_D10
M22 MA_ADD11 MA_DATA10 E19 L27 MB_ADD11 MB_DATA10 B20
DDR_A_MA12 L24 J19 DDR_A_D11 DDR_B_MA12 K27 A20 DDR_B_D11
DDR_A_MA13 MA_ADD12 MA_DATA11 DDR_A_D12 DDR_B_MA13 MB_ADD12 MB_DATA11 DDR_B_D12
AA25 MA_ADD13 MA_DATA12 G16 W26 MB_ADD13 MB_DATA12 E17
DDR_A_MA14 L21 H16 DDR_A_D13 DDR_B_MA14 K25 B17 DDR_B_D13
DDR_A_MA15 MA_ADD14 MA_DATA13 DDR_A_D14 DDR_B_MA15 MB_ADD14 MB_DATA13 DDR_B_D14
L20 MA_ADD15 MA_DATA14 H19 K24 MB_ADD15 MB_DATA14 B19
F19 DDR_A_D15 C19 DDR_B_D15
DDR_A_BS0 MA_DATA15 DDR_B_BS0 MB_DATA15
10 DDR_A_BS0 U24 MA_BANK0 11 DDR_B_BS0 U27 MB_BANK0
DDR_A_BS1 U21 H20 DDR_A_D16 DDR_B_BS1 T28 C21 DDR_B_D16
10 DDR_A_BS1 MA_BANK1 MA_DATA16 11 DDR_B_BS1 MB_BANK1 MB_DATA16
DDR_A_BS2 L23 F21 DDR_A_D17 DDR_B_BS2 K28 B22 DDR_B_D17
10 DDR_A_BS2 MA_BANK2 MA_DATA17 11 DDR_B_BS2 MB_BANK2 MB_DATA17
J23 DDR_A_D18 C23 DDR_B_D18
10 DDR_A_DM[0..7] MA_DATA18 11 DDR_B_DM[0..7] MB_DATA18
DDR_A_DM0 E14 H23 DDR_A_D19 DDR_B_DM0 D14 A24 DDR_B_D19
DDR_A_DM1 MA_DM0 MA_DATA19 DDR_A_D20 DDR_B_DM1 MB_DM0 MB_DATA19 DDR_B_D20
J17 MA_DM1 MA_DATA20 G20 A18 MB_DM1 MB_DATA20 D20
DDR_A_DM2 E21 E20 DDR_A_D21 DDR_B_DM2 A22 B21 DDR_B_D21
DDR_A_DM3 MA_DM2 MA_DATA21 DDR_A_D22 DDR_B_DM3 MB_DM2 MB_DATA21 DDR_B_D22
F25 MA_DM3 MA_DATA22 G22 C25 MB_DM3 MB_DATA22 E23
DDR_A_DM4 AD27 H22 DDR_A_D23 DDR_B_DM4 AF25 B23 DDR_B_D23
DDR_A_DM5 MA_DM4 MA_DATA23 DDR_B_DM5 MB_DM4 MB_DATA23
AC23 MA_DM5 AG22 MB_DM5
2 DDR_A_DM6 DDR_A_D24 DDR_B_DM6 DDR_B_D24 2
AD19 MA_DM6 MA_DATA24 G24 AH18 MB_DM6 MB_DATA24 E24
DDR_A_DM7 AC15 E25 DDR_A_D25 DDR_B_DM7 AD14 B25 DDR_B_D25
MA_DM7 MA_DATA25 DDR_A_D26 MB_DM7 MB_DATA25 DDR_B_D26
MA_DATA26 G27 MB_DATA26 B27
DDR_A_DQS0 G14 G26 DDR_A_D27 DDR_B_DQS0 C15 D28 DDR_B_D27
DDR_A_DQS#0 MA_DQS_H0 MA_DATA27 DDR_A_D28 DDR_B_DQS#0 MB_DQS_H0 MB_DATA27 DDR_B_D28
H14 MA_DQS_L0 MA_DATA28 F23 B15 MB_DQS_L0 MB_DATA28 B24
DDR_A_DQS1 G18 H24 DDR_A_D29 DDR_B_DQS1 E18 D24 DDR_B_D29
DDR_A_DQS#1 MA_DQS_H1 MA_DATA29 DDR_A_D30 DDR_B_DQS#1 MB_DQS_H1 MB_DATA29 DDR_B_D30
H18 MA_DQS_L1 MA_DATA30 E28 D18 MB_DQS_L1 MB_DATA30 D26
DDR_A_DQS2 J21 F27 DDR_A_D31 DDR_B_DQS2 E22 C27 DDR_B_D31
DDR_A_DQS#2 MA_DQS_H2 MA_DATA31 DDR_B_DQS#2 MB_DQS_H2 MB_DATA31
H21 MA_DQS_L2 D22 MB_DQS_L2
DDR_A_DQS3 E27 AB28 DDR_A_D32 DDR_B_DQS3 B26 AG26 DDR_B_D32
DDR_A_DQS#3 MA_DQS_H3 MA_DATA32 DDR_A_D33 DDR_B_DQS#3 MB_DQS_H3 MB_DATA32 DDR_B_D33
E26 MA_DQS_L3 MA_DATA33 AC27 A26 MB_DQS_L3 MB_DATA33 AH26
DDR_A_DQS4 AE26 AD25 DDR_A_D34 DDR_B_DQS4 AG24 AF23 DDR_B_D34
DDR_A_DQS#4 MA_DQS_H4 MA_DATA34 DDR_A_D35 DDR_B_DQS#4 MB_DQS_H4 MB_DATA34 DDR_B_D35
AD26 MA_DQS_L4 MA_DATA35 AA24 AG25 MB_DQS_L4 MB_DATA35 AG23
DDR_A_DQS5 AB22 AE28 DDR_A_D36 DDR_B_DQS5 AG21 AG27 DDR_B_D36
DDR_A_DQS#5 MA_DQS_H5 MA_DATA36 DDR_A_D37 DDR_B_DQS#5 MB_DQS_H5 MB_DATA36 DDR_B_D37
AA22 MA_DQS_L5 MA_DATA37 AD28 AF21 MB_DQS_L5 MB_DATA37 AF27
DDR_A_DQS6 AB18 AB26 DDR_A_D38 DDR_B_DQS6 AG17 AH24 DDR_B_D38
DDR_A_DQS#6 MA_DQS_H6 MA_DATA38 DDR_A_D39 DDR_B_DQS#6 MB_DQS_H6 MB_DATA38 DDR_B_D39
AA18 MA_DQS_L6 MA_DATA39 AC25 AG18 MB_DQS_L6 MB_DATA39 AE24
DDR_A_DQS7 AA14 DDR_B_DQS7 AH14
DDR_A_DQS#7 MA_DQS_H7 DDR_A_D40 DDR_B_DQS#7 MB_DQS_H7 DDR_B_D40
AA15 MA_DQS_L7 MA_DATA40 Y23 AG14 MB_DQS_L7 MB_DATA40 AE22
AA23 DDR_A_D41 AH22 DDR_B_D41
DDR_A_CLK0 MA_DATA41 DDR_A_D42 DDR_B_CLK0 MB_DATA41 DDR_B_D42
10 DDR_A_CLK0 T21 MA_CLK_H0 MA_DATA42 Y21 11 DDR_B_CLK0 R26 MB_CLK_H0 MB_DATA42 AE20
DDR_A_CLK0# T22 AA20 DDR_A_D43 DDR_B_CLK0# R27 AH20 DDR_B_D43
10 DDR_A_CLK0# MA_CLK_L0 MA_DATA43 11 DDR_B_CLK0# MB_CLK_L0 MB_DATA43
DDR_A_CLK1 R23 AB24 DDR_A_D44 DDR_B_CLK1 P27 AD23 DDR_B_D44
10 DDR_A_CLK1 MA_CLK_H1 MA_DATA44 11 DDR_B_CLK1 MB_CLK_H1 MB_DATA44
DDR_A_CLK1# R24 AD24 DDR_A_D45 DDR_B_CLK1# P28 AD22 DDR_B_D45
10 DDR_A_CLK1# MA_CLK_L1 MA_DATA45 11 DDR_B_CLK1# MB_CLK_L1 MB_DATA45
AA21 DDR_A_D46 AD21 DDR_B_D46
DDR_A_CKE0 MA_DATA46 DDR_A_D47 DDR_B_CKE0 MB_DATA46 DDR_B_D47
10 DDR_A_CKE0 H28 MA_CKE0 MA_DATA47 AC21 11 DDR_B_CKE0 J26 MB_CKE0 MB_DATA47 AD20
DDR_A_CKE1 H27 DDR_B_CKE1 J27
10 DDR_A_CKE1 MA_CKE1 11 DDR_B_CKE1 MB_CKE1
AA19 DDR_A_D48 AF19 DDR_B_D48
DDR_A_ODT0 MA_DATA48 DDR_A_D49 DDR_B_ODT0 MB_DATA48 DDR_B_D49
10 DDR_A_ODT0 Y25 MA_ODT0 MA_DATA49 AC19 11 DDR_B_ODT0 W27 MB_ODT0 MB_DATA49 AE18
DDR_A_ODT1 AA27 AC17 DDR_A_D50 DDR_B_ODT1 Y28 AE16 DDR_B_D50
10 DDR_A_ODT1 MA_ODT1 MA_DATA50 11 DDR_B_ODT1 MB_ODT1 MB_DATA50
AA17 DDR_A_D51 AH16 DDR_B_D51
DDR_A_SCS0# MA_DATA51 DDR_A_D52 DDR_B_SCS0# MB_DATA51 DDR_B_D52
10 DDR_A_SCS0# V22 MA_CS_L0 MA_DATA52 AB20 11 DDR_B_SCS0# V25 MB_CS_L0 MB_DATA52 AG20
3 DDR_A_SCS1# DDR_A_D53 DDR_B_SCS1# DDR_B_D53 3
10 DDR_A_SCS1# AA26 MA_CS_L1 MA_DATA53 Y19 11 DDR_B_SCS1# Y27 MB_CS_L1 MB_DATA53 AG19
AD18 DDR_A_D54 AF17 DDR_B_D54
DDR_A_RAS# MA_DATA54 DDR_A_D55 DDR_B_RAS# MB_DATA54 DDR_B_D55
10 DDR_A_RAS# V21 MA_RAS_L MA_DATA55 AD17 11 DDR_B_RAS# V24 MB_RAS_L MB_DATA55 AD16
DDR_A_CAS# W24 DDR_B_CAS# V27
10 DDR_A_CAS# MA_CAS_L 11 DDR_B_CAS# MB_CAS_L
DDR_A_WE# W23 AA16 DDR_A_D56 DDR_B_WE# V28 AG15 DDR_B_D56
10 DDR_A_WE# MA_WE_L MA_DATA56 11 DDR_B_WE# MB_WE_L MB_DATA56
Y15 DDR_A_D57 AD15 DDR_B_D57
MEM_MA_RST# MA_DATA57 DDR_A_D58 MEM_MB_RST# MB_DATA57 DDR_B_D58
10 MEM_MA_RST# H25 MA_RESET_L MA_DATA58 AA13 11 MEM_MB_RST# J25 MB_RESET_L MB_DATA58 AG13
MEM_MA_EVENT# T24 AC13 DDR_A_D59 MEM_MB_EVENT# T25 AD13 DDR_B_D59
10 MEM_MA_EVENT# MA_EVENT_L MA_DATA59 11 MEM_MB_EVENT# MB_EVENT_L MB_DATA59
Y17 DDR_A_D60 AG16 DDR_B_D60
MA_DATA60 DDR_A_D61 MB_DATA60 DDR_B_D61
+MEM_VREF
15mil MA_DATA61 AB16
DDR_A_D62 MB_DATA61 AF15
DDR_B_D62
W20 M_VREF MA_DATA62 AB14 MB_DATA62 AE14
Y13 DDR_A_D63 AF13 DDR_B_D63
MA_DATA63 MB_DATA63

+1.5V 1 2 M_ZVDDIO W21 M_ZVDDIO

R33 39.2_0402_1%
AMD_TOPEDO_FS-1

AMD_TOPEDO_FS-1

EVENT# pull high 0.75V Reference Voltage +1.5V

2

+1.5V
4 R31 4
1K_0402_1%

R11
15mil
1 2 1K_0402_5% MEM_MA_EVENT#
1

+MEM_VREF
R12 1 2 1K_0402_5% MEM_MB_EVENT#
2

1 2
R32 C63 C64
1K_0402_1% Security Classification Compal Secret Data Compal Electronics, Inc.
1000P_0402_50V7K 0.1U_0402_16V7K 2011/01/06 2012/01/06 Title
2 1 Issued Date Deciphered Date
SCHEMATIC, MB A7213
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 6 of 51
A B C D E
 A B C D E

To LVDS Translator
27

27
DP0_TXP0_C

DP0_TXN0_C
C69

C70
Close to APU

1
2 0.1U_0402_16V7K
UMA@
2 0.1U_0402_16V7K
UMA@
DP0_TXP0

DP0_TXN0
F2

F1
JAPUD

DP0_TXP0

DP0_TXN0
DP0_AUXP

DP0_AUXN
@

D4

D5
DP0_AUXP

DP0_AUXN
C79

C80
Close to APU

1
2 0.1U_0402_16V7K
UMA@
2 0.1U_0402_16V7K
UMA@
DP0_AUXP_C 27

DP0_AUXN_C 27
www.qdzbwx.com
To LVDS Translator
DP0_AUXP

DP0_AUXN

DP1_AUXP
R34

R35

R36
2 UMA@ 1 1.8K_0402_5%

2 UMA@ 1 1.8K_0402_5%

2 UMA@ 1 1.8K_0402_5%

C189 1 2 0.1U_0402_16V7K DP0_TXP1 E3 E5 DP1_AUXP C81 1 2 0.1U_0402_16V7K DP1_AUXN R37 2 UMA@ 1 1.8K_0402_5%
27 DP0_TXP1_C DP0_TXP1 DP1_AUXP ML_VGA_AUXP 24
UMA@ UMA@ To FCH

DISPLAY PORT 0
C223 1 2 0.1U_0402_16V7K DP0_TXN1 E2 E6 DP1_AUXN C82 1 2 0.1U_0402_16V7K
27 DP0_TXN1_C DP0_TXN1 DP1_AUXN ML_VGA_AUXN 24
UMA@ UMA@

D2 DP0_TXP2 DP2_AUXP J5

DISPLAY PORT MISC.

D1 J6 +1.2VS
DP0_TXN2 DP2_AUXN
1 1
TEST25_L R156 1 2 510_0402_1%
C2 DP0_TXP3 DP3_AUXP H4 AUX 2~5 are for GFX interface use,
TEST25_H R160 1 2 510_0402_1%
C3 H5
they could be selected to DDC or
DP0_TXN3 DP3_AUXN
Close to APU AUX logic
+1.5V
G5 UMA_HDMI_CLK VDDIO level
DP4_AUXP UMA_HDMI_CLK 30
C71 1 2 0.1U_0402_16V7K DP1_TXP0 K2 TEST35 R155 1 2 300_0402_5%
24 ML_VGA_TXP0
UMA@ DP1_TXP0
G6 UMA_HDMI_DATA Need level shifter
DP4_AUXN UMA_HDMI_DATA 30
C72 1 2 0.1U_0402_16V7K DP1_TXN0 K1 R128 1 2 300_0402_5%
24 ML_VGA_TXN0 DP1_TXN0
UMA@ DP2_HPD 2 1 @
F4 R105 100K_0402_5%
C73 DP1_TXP1 DP5_AUXP DP3_HPD +1.5V
24 ML_VGA_TXP1 1 2 0.1U_0402_16V7K J3 DP1_TXP1 2 1
UMA@ R70 100K_0402_5%

DISPLAY PORT 1
DP5_AUXN F5
C74 1 2 0.1U_0402_16V7K DP1_TXN1 J2 DP5_HPD 2 1 M_TEST R191 1 @ 2 39.2_0402_1%
24 ML_VGA_TXN1 DP1_TXN1
UMA@ R102 100K_0402_5%
To FCH D7 DP0_HPD LVDS R192 1 2 39.2_0402_1%
DP0_HPD DP0_HPD 9
C75 1 2 0.1U_0402_16V7K DP1_TXP2 H2
24 ML_VGA_TXP2 DP1_TXP2
UMA@ E7 DP1_HPD CRT
DP1_HPD DP1_HPD 9 +3VALW
C76 1 2 0.1U_0402_16V7K DP1_TXN2 H1
24 ML_VGA_TXN2 DP1_TXN2
UMA@ J7 DP2_HPD Avoid leakage issue
DP2_HPD FS1R1 R196 1 2 10K_0402_5%
C77 1 2 0.1U_0402_16V7K DP1_TXP3 G2 H7 DP3_HPD
24 ML_VGA_TXP3 DP1_TXP3 DP3_HPD +1.5V
UMA@
C78 1 2 0.1U_0402_16V7K DP1_TXN3 G3 G7 DP4_HPD HDMI
24 ML_VGA_TXN3 DP1_TXN3 DP4_HPD DP4_HPD 9 +1.5VS
UMA@
F7 DP5_HPD DMA_ACTIVE# R109 1 2 1K_0402_5%
DP5_HPD
APU_CLKP AH7 DMA_ACTIVE# R49 1 @ 2 1K_0402_5%
22 APU_CLKP CLKIN_H
100MHz (SS) C6 DP_ENBKL
DP_BLON DP_ENBKL 9
APU_CLKN AH6 UMA_HDMI_CLK R55 1 IHDMI@ 2 1K_0402_5%
22 APU_CLKN CLKIN_L
C5 DP_ENVDD
DP_DIGON DP_ENVDD 9

CLK
UMA_HDMI_DATA R57 1 IHDMI@ 2 1K_0402_5%
2 APU_DISP_CLKP DP_INT_PWM 2
22 APU_DISP_CLKP AH4 DISP_CLKIN_H DP_VARY_BL C7 DP_INT_PWM 9
100MHz (NSS) APU_DISP_CLKN
22 APU_DISP_CLKN AH3 DISP_CLKIN_L
D8 DP_AUX_ZVSS R61 1 2 150_0402_1%
DP_AUX_ZVSS

R216 1 2 0_0402_5% APU_SVC_R B8 +1.5V +3VS

49 APU_SVC SVC
TEST6 AA10
R217 1 2 0_0402_5% APU_SVD_R A8
49 APU_SVD SVD

SER.
TEST9 G10

1
2

1
APU_SIC AH11 H10 R44
9,23 APU_SIC SIC TEST10
SB-TSI R43 10K_0402_5% R45
APU_SID AG11 H12 R129 1 2 1K_0402_5% 1K_0402_5% 10K_0402_5%
9,23 APU_SID SID TEST12 R46

2
D9 T6 1 2

2
TEST14 10K_0402_5%

2
APU_RST# APU_RST#

B
2 1 22 APU_RST# AF10 RESET_L TEST15 E9 T7
C258 1000P_0402_50V7K Q41
APU_PWRGD APU_PROCHOT#

E
22 APU_PWRGD AE10 PWROK TEST16 G9 T8 22 APU_PROCHOT# 1 3 H_PROCHOT# 37,42,49
APU_PWRGD

C
2 1
C83 1000P_0402_50V7K H9 T9 MMBT3904_NL_SOT23-3
APU_PROCHOT# TEST17
AD10 PROCHOT_L APU_TEST18 R130 1 2 1K_0402_5%
CTRL

TEST18 H11
APU_THERMTRIP# AG12 +1.5V
THERMTRIP_L APU_TEST19 R131 1
TEST19 G11 2 1K_0402_5%
+1.5VS APU_ALERT# AH12
24 APU_ALERT# ALERT_L
Close to R38 and R39 F12 APU_TEST20 R136 1 2 1K_0402_5%
TEST20

1
@ E11 APU_TEST21 R137 1 2 1K_0402_5% R52 R51
TEST21 1K_0402_5% 10K_0402_5%
TEST

1 2 T3 C12 TDI
C199 0.1U_0402_16V7K D11 APU_TEST22 R142 1 2 1K_0402_5%
TEST22
T10 A12 Thermal Shutdown Temperature:

2 2
R38 @ APU_SVC_R TDO
3 1 2 1K_0402_5% TEST23 F10 125 degree 3

B
T17 A11 TCK
R39 1 @ 2 1K_0402_5% APU_SVD_R G12 APU_TEST24 R152 1 2 1K_0402_5% Q5
TEST24

E
T18 D12 APU_THERMTRIP# 3 1
JTAG

TMS H_THERMTRIP# 23

C
R47 1 2 300_0402_5% APU_RST# AH10 TEST25_H
TEST25_H MMBT3904_NL_SOT23-3
T19 B12 TRST_L
R48 1 2 300_0402_5% APU_PWRGD AH9 TEST25_L
TEST25_L
T20 B11 DBRDY
TEST28_H K7
T21 C11 DBREQ_L
TEST28_L K8

Reserve test point for debug use AA12 T11

HDT Debug conn
TEST30_H +1.5V
E8 RSVD_1
AB12 T12 JHDT @
TEST30_L APU_TCK
RSVD

K21 RSVD_2 1 1 2 2
K22 M_TEST
TEST31 APU_TMS
AC11 RSVD_3 3 3 4 4
TEST32_H AB11 T13
R58 1 2 0_0402_5% 5 6 APU_TDI
49 APU_VDDNB_RUN_FB_L 5 6
TEST32_L AA11 T14
R212 1 2 0_0402_5% VSS_SENSE B9 7 8 T22
49 APU_VDD_RUN_FB_L VSS_SENSE 7 8
D10 TEST35
TEST35 APU_TRST#
T1 C8 VDDP_SENSE 9 9 10 10 T23
R214 1 2 0_0402_5% VDDNB_SENSE A9 FS1R1 will be low 1 2 11 12 T24
49 APU_VDDNB_SENSE VDDNB_SENSE 11 12
FS1R1 R122 10K_0402_5%
SENSE

FS1R1 Y11
T4 B10 for non-FS1 APU 1 2 13 14 T28
VDDIO_SENSE DMA_ACTIVE# R123 10K_0402_5% 13 14
DMAACTIVE_L AB10 DMA_ACTIVE# 22
R215 1 2 0_0402_5% VDD_SENSE C9 1 2 15 16 APU_DBREQ#
49 APU_VDD_SENSE VDD_SENSE 15 16
R124 10K_0402_5%
T5 A10 VDDR_SENSE AE12 T15 Llano do not support 17 18 T29
TEST4 THERMDA 17 18
4 AD12
internal thermal die 19 20 4
T16 T50
TEST5 THERMDC 19 20
+1.5V
Close to JHDT AMD_TOPEDO_FS-1
+1.5V SAMTE_ASP-136446-07-B
R95 1 2 1K_0402_5% APU_TDI
R40 1 2 1K_0402_5% APU_SIC
R97 1 2 1K_0402_5% APU_TCK
R41 1 2 1K_0402_5% APU_SID
R100 1 2 1K_0402_5% APU_TMS Security Classification Compal Secret Data Compal Electronics, Inc.
R42 1 2 1K_0402_5% APU_ALERT# 2011/01/06 2012/01/06 Title
R116 1
Issued Date Deciphered Date
2 1K_0402_5% APU_TRST#
R107 1 2 1K_0402_5% APU_SVC_R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
R117 1 2 300_0402_5% APU_DBREQ# Avoid leakage issue Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
R108 1 2 1K_0402_5% APU_SVD_R Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 7 of 51
A B C D E
 A B C D E

CPU BOTTOM SIDE DECOUPLING

www.qdzbwx.com JAPUF @
+CPU_CORE

C132 C133 C135 C134 C137 C136 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 A7 T11
VSS VSS
A13 VSS VSS T19

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.01U_0402_16V7K

0.01U_0402_16V7K

0.01U_0402_16V7K

180P_0402_50V8J

180P_0402_50V8J

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y

330U_D2_2V_Y
1 1 1 1 A15 VSS VSS U4
JAPUE @ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A17 U7
+CPU_CORE +CPU_CORE C131 + + + + VSS VSS
A19 VSS VSS U10
A21 VSS VSS U18
C1 VDD VDD T6 A23 VSS VSS V9
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 D3
D6
VDD 50A VDD T10
T18
A25
B7
VSS VSS V11
V19
1
VDD VDD VSS VSS
E1 VDD VDD U1 C4 VSS VSS W4
F3 VDD VDD U11 C10 VSS VSS W7
F6 VDD VDD U19 C14 VSS VSS W10
F8 VDD VDD V3 C16 VSS VSS W12
G1 V6 +CPU_CORE_NB C18 W14
VDD VDD @ VSS VSS
H3 VDD VDD V10 C20 VSS VSS W16
H6 V18 C150 C151 C152 C153 C154 C155 C158 C159 C160 C201 C163 C22 W18
VDD VDD VSS VSS
H8 VDD VDD W1 C24 VSS VSS Y9

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

390U_2.5V_M_R10

390U_2.5V_M_R10

330U_D2_2V_Y
J1 VDD VDD W11 1 1 1 C26 VSS VSS Y22
K3 VDD VDD W13 1 1 1 1 1 1 1 1 1 C28 VSS VSS AA4
K6 W15 C149 + + + D13 AA7
VDD VDD VSS VSS
L1 VDD VDD W17 D15 VSS VSS AB9
L11 VDD VDD W19 D17 VSS VSS AB13
2 2 2 2 2 2 2 2 2 2 2 2
L19 VDD VDD Y3 D19 VSS VSS AB15
M3 VDD VDD Y6 D21 VSS VSS AB17
M6 VDD VDD Y10 D23 VSS VSS AB19
M10 VDD VDD Y12 D25 VSS VSS AB21
M18 VDD VDD Y14 D27 VSS VSS AB23
N1 VDD VDD Y16 E4 VSS VSS AB25
N11 Y18 +1.5V E10 AB27
VDD VDD VSS VSS
N19 VDD VDD Y20 E12 VSS VSS AC4
P3 AA1 C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 F9 AC7
VDD VDD VSS VSS
P6 VDD VDD AB3 F11 VSS VSS AC10

22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J
P10 VDD VDD AB6 1 F14 VSS VSS AC12
P18 VDD VDD AC1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 F16 VSS VSS AC14
R1 AD3 C88 + C106 F18 AC16
VDD VDD VSS VSS
R11 VDD VDD AD6 F20 VSS VSS AC18
R19 AE1 390U_2.5V_M_R10 F22 AC20
VDD VDD 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VSS VSS
T3 VDD F24 VSS VSS AC22
F26 VSS VSS AC24
F28 VSS VSS AC26
+CPU_CORE_NB J9 VDDNB VDDNB K11 +CPU_CORE_NB G4 VSS VSS AC28
2 2
J10
J11
VDDNB 22.5A VDDNB K12
K13
G8
G13
VSS VSS AD9
AD11
VDDNB VDDNB VSS VSS
J12 VDDNB VDDNB K14 G15 VSS VSS AE4
J14 VDDNB VDDNB K16 G17 VSS VSS AE7
J16 VDDNB VDDNB K17 G19 VSS VSS AE13
K9 VDDNB VDDNB K18 G21 VSS VSS AE15
K10 L18 +1.5V G23 AE17
VDDNB VDDNB VSS VSS
G25 VSS VSS AE19
C103 C104 C105 J4 AE21
VSS VSS
+1.5V G28 VDDIO VDDIO R22 +1.5V J8 VSS VSS AE23

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

180P_0402_50V8J

180P_0402_50V8J
H26 VDDIO 4A VDDIO R25 If the VSS plane is cut to J18 VSS VSS AE25
J28 VDDIO VDDIO R28 1 1 1 1 J20 VSS VSS AE27
K20 T20 C102 create a VDDIO plane, J22 AF3
VDDIO VDDIO VSS VSS
K23 VDDIO VDDIO T23 place across the VDDIO J24 VSS VSS AF6
K26 T26 K19 AF9
L22
VDDIO VDDIO
U22
2 2 2 2 and VSS plane split L4
VSS VSS
AF12
VDDIO VDDIO VSS VSS
L25 VDDIO VDDIO U25 L7 VSS VSS AF14
L28 VDDIO VDDIO U28 L10 VSS VSS AF16
M20 VDDIO VDDIO V20 M9 VSS VSS AF18
M23 VDDIO VDDIO V23 M11 VSS VSS AF20
M26 VDDIO VDDIO V26 M19 VSS VSS AF22
N22 VDDIO VDDIO W22 N4 VSS VSS AF24
N25 VDDIO VDDIO W25 N7 VSS VSS AF26
N28 VDDIO VDDIO W28 N10 VSS VSS AF28
P20 VDDIO VDDIO Y24 VDDP Decoupling N18 VSS VSS AG10
P23 VDDIO VDDIO Y26 P9 VSS VSS AH5
P26 VDDIO VDDIO AA28 P11 VSS VSS AH8
+1.2VS P19 AH13
VSS VSS
R4 VSS VSS AH15
C124 C125 C126 C127 C128 C129
+1.2VS AG2
AG3
VDDP_A_1 3.5AVDDP_B_1 A3
A4
R7
R10
VSS VSS AH17
AH19
VDDP_A_2 VDDP_B_2 VSS VSS
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

180P_0402_50V8J

180P_0402_50V8J

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K
AG4 VDDP_A_3 VDDP_B_3 B3 1 R18 VSS VSS AH21
AG5 VDDP_A_4 VDDP_B_4 B4 1 1 1 1 1 1 1 T9 VSS VSS AH23
3 C123 + C130 AH25 3
VSS
+1.2VS AG6 A5 390U_2.5V_M_R10
VDDR VDDR 2 2 2 2 2 2 2 2
AG7
AG8
VDDR 3A VDDR A6
B5 AMD_TOPEDO_FS-1
VDDR VDDR
AG9 VDDR VDDR B6
+2.5VS
L1
FBM_L11_201209_300LMA30T_0805 AE11
C170 +2.5VS_VDDA VDDA
1 2 AF11 VDDA 0.75A VDDR Decoupling
4.7U_0603_6.3V6K

0.22U_0402_6.3V6K

3300P_0402_50V7K

1
100U_B2_4VM_R35M

1 1 C164 1 C120 C121 C122 C115 C116 C117 C118 +1.2VS

1

C196 + C165 C198 AMD_TOPEDO_FS-1

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

1000P_0402_50V7K

@ 180P_0402_50V8J
@ 1 1 1 1 1 1 1 1
2

2 2 2 2 C119

2 2 2 2 2 2 2 2

CRB Decoupling Capacitor (include PWM side)：

C111 C112 C113 C107 C108 C109 C110
VDD: VDDNB: VDDIO: VDDP/R_PWM: VDDP: VDDR: VDDA:
0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

0.22U_0402_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

1 1 1 1 1 1 1 1 470uF x 6 470uF x 4 680uF x 1 470uF x 2 10uF x 3 4.7uF x 4 100uF x 1

C114
22uF x 9 22uF x 6 330uF x 1 10uF x 1 0.22uF x 2 0.22uF x 4 4.7uF x 1
0.22uF x 2 0.22uF x 2 22uF x 2 180pF x 2 1nF x 4 0.22uF x 1
2 2 2 2 2 2 2 2
0.01uF x 3 180pF x 3 4.7uF x 4 180pF x 4 3.3nF x 1
4 180pF x 2 0.22uF x 8 4
180pF x 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 8 of 51
A B C D E
 5 4 3 2 1

HPD Panel ENBKL +3VS

www.qdzbwx.com
+3VS

+1.5VS

1
UMA@ @

2
R59 R68
10K_0402_5% UMA@ @ 4.7K_0402_5%
R54 R60 R67

2
D 4.7K_0402_5% 100K_0402_5% D
Translator HPD 1 2 APU_ENBKL 28
10K_0402_5%

1
2

6
B
From Translator or Conn UMA@ UMA@
Q26 Q14A

E
LVDS_HPD 3 1 2N7002DW-T/R7_SOT363-6
27 LVDS_HPD DP0_HPD 7

C
MMBT3904_NL_SOT23-3 2 @

1
2 UMA@ 1 @ C @

1
R207 100K_0402_5% 1 2 2 Q15
7 DP_ENBKL
R66 2.2K_0402_5% B MMBT3904_NL_SOT23-3

2
E

3
@
R65
+3VS 100K_0402_5%

1
+1.5VS

1
UMA@

1
R62
10K_0402_5% UMA@
R154 R63

2
CRT HPD 1 2 4.7K_0402_5%
10K_0402_5%

2
2
B

From FCH UMA@ UMA@

Q16
E

FCH_CRT_HPD 3 1
24 FCH_CRT_HPD DP1_HPD 7
C

MMBT3904_NL_SOT23-3
Panel ENVDD
2 UMA@ 1
R64 100K_0402_5% +3VS

C C
+3VS

1
+1.5VS
1

2
@
IHDMI@ @ R75
1

R208 R74 4.7K_0402_5%

10K_0402_5% IHDMI@ 100K_0402_5%

2
R267 R210
APU_ENVDD 28
2

1
HDMI HPD 1 2 4.7K_0402_5%

3
10K_0402_5%
2
2
B

From HDMI Conn IHDMI@ IHDMI@ Q14B

Q27 2N7002DW-T/R7_SOT363-6
E

HDMI_HPD 3 1 5 @
23,30 HDMI_HPD DP4_HPD 7
C

MMBT3904_NL_SOT23-3

1
@ C @

4
2 IHDMI@ 1 7 DP_ENVDD 1 2 2 Q28
R199 100K_0402_5% R71 2.2K_0402_5% B MMBT3904_NL_SOT23-3
E

3
2
@
R69
100K_0402_5%

1
B B

SB-TSI Panel PWM

+3VS
Need to confirm R93 value
4.7K or 47K
Vgs of BSH111 :
+1.5VS
Min = 0.4V

1
Max = 1.3V UMA@ UMA@
R92 R93
47K_0402_5% 47K_0402_5%
1

2
R218 R219
APU_INVT_PWM 27,28
2

Q22 2.2K_0402_5% 2.2K_0402_5% Q37

1
D
G

UMA@
G

2 Q35
1 3 APU_SID_Q 3 1 G 2N7002_SOT23-3
7,23 APU_SID EC_SMB_DA2 13,32,37,38,39
S

3
1
S

UMA@ C UMA@
D

BSH111_SOT23-3 BSH111_SOT23-3 1 2 2 Q21

7 DP_INT_PWM
R89 2.2K_0402_5% B MMBT3904_NL_SOT23-3
E

3
1

UMA@
R76
2

Q25 Q42 4.7K_0402_5%

G
G

A A
1 3 APU_SIC_Q 3 1
7,23 APU_SIC EC_SMB_CK2 13,32,37,38,39
S

D
D

BSH111_SOT23-3 BSH111_SOT23-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 9 of 51
5 4 3 2 1
 5 4 3 2 1

+VREF_DQA
DDR_A_D0
+1.5V

1
3
5
JDDRH
VREF_DQ
VSS
DQ0
VSS
DQ4
DQ5
2
4
6
+1.5V

DDR_A_D4
DDR_A_D5
DDR3 SO-DIMM A
Standard Type DDR_A_DQS[0..7]

DDR_A_DQS#[0..7]
www.qdzbwx.com
6

6
DDR_A_D1 7 8
DQ1 VSS DDR_A_DQS#0
9 VSS DQS0# 10 DDR_A_D[0..63] 6
DDR_A_DM0 11 12 DDR_A_DQS0
DM0 DQS0
13 VSS VSS 14 DDR_A_MA[0..15] 6
DDR_A_D2 15 16 DDR_A_D6
DDR_A_D3 DQ2 DQ6 DDR_A_D7
17 DQ3 DQ7 18 DDR_A_DM[0..7] 6
19 VSS VSS 20
DDR_A_D8 21 22 DDR_A_D12
DDR_A_D9 DQ8 DQ12 DDR_A_D13
D
23 DQ9 DQ13 24 D
25 VSS VSS 26
DDR_A_DQS#1 27 28 DDR_A_DM1
DDR_A_DQS1 DQS1# DM1 MEM_MA_RST#
29 DQS1 RESET# 30 MEM_MA_RST# 6
31 VSS VSS 32
DDR_A_D10 33 34 DDR_A_D14
DDR_A_D11 DQ10 DQ14 DDR_A_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_A_D16 DDR_A_D20 +1.5V
39 DQ16 DQ20 40
DDR_A_D17 41 42 DDR_A_D21
DQ17 DQ21
43 VSS VSS 44

1
DDR_A_DQS#2 45 46 DDR_A_DM2
DDR_A_DQS2 DQS2# DM2 R79
47 DQS2 VSS 48
49 50 DDR_A_D22 1K_0402_1%
DDR_A_D18 VSS DQ22 DDR_A_D23
51 DQ18 DQ23 52
DDR_A_D19 53 54

2
DQ19 VSS DDR_A_D28
55 VSS DQ28 56 +VREF_DQA
DDR_A_D24 57 58 DDR_A_D29
DQ24 DQ29

1
DDR_A_D25 59 60
DQ25 VSS DDR_A_DQS#3 R81
61 VSS DQS3# 62 1 1 1
DDR_A_DM3 63 64 DDR_A_DQS3 C65 C156 C157 1K_0402_1%
DM3 DQS3 @
65 VSS VSS 66

1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K
DDR_A_D26 67 68 DDR_A_D30

2
DDR_A_D27 DQ26 DQ30 DDR_A_D31 2 2 2
69 DQ27 DQ31 70
71 VSS VSS 72
Reserve for EMI request
DDR_A_CKE0 73 74 DDR_A_CKE1
6 DDR_A_CKE0 CKE0 CKE1 DDR_A_CKE1 6 +1.5V
75 VDD VDD 76
77 78 DDR_A_MA15
DDR_A_BS2 NC A15 DDR_A_MA14
C
6 DDR_A_BS2 79 BA2 A14 80 C

DDR_A_MA12
81 VDD VDD 82
DDR_A_MA11
Close to JDDRH.1 1
C286
2
33P_0402_50V8J
83 A12/BC# A11 84
DDR_A_MA9 85 86 DDR_A_MA7
A9 A7
87 VDD VDD 88 1 2
DDR_A_MA8 89 90 DDR_A_MA6 C287 33P_0402_50V8J
DDR_A_MA5 A8 A6 DDR_A_MA4
91 A5 A4 92
93 VDD VDD 94 1 2
DDR_A_MA3 95 96 DDR_A_MA2 C291 33P_0402_50V8J
DDR_A_MA1 A3 A2 DDR_A_MA0
97 A1 A0 98
99 VDD VDD 100 1 2
DDR_A_CLK0 101 102 DDR_A_CLK1 C295 33P_0402_50V8J
6 DDR_A_CLK0 CK0 CK1 DDR_A_CLK1 6
DDR_A_CLK0# 103 104 DDR_A_CLK1#
6 DDR_A_CLK0# CK0# CK1# DDR_A_CLK1# 6
105 VDD VDD 106 1 2
DDR_A_MA10 DDR_A_BS1 +1.5V C316 33P_0402_50V8J
107 A10/AP BA1 108 DDR_A_BS1 6
DDR_A_BS0 109 110 DDR_A_RAS#
6 DDR_A_BS0 BA0 RAS# DDR_A_RAS# 6
111 VDD VDD 112 1 2

1
DDR_A_WE# 113 114 DDR_A_SCS0# C324 33P_0402_50V8J
6 DDR_A_WE# WE# S0# DDR_A_SCS0# 6
DDR_A_CAS# 115 116 DDR_A_ODT0 R80
6 DDR_A_CAS# CAS# ODT0 DDR_A_ODT0 6
117 118 1K_0402_1% 1 2
DDR_A_MA13 VDD VDD DDR_A_ODT1 C325 33P_0402_50V8J
119 A13 ODT1 120 DDR_A_ODT1 6
DDR_A_SCS1# 121 122

2
6 DDR_A_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAA
TEST VREF_CA
127 VSS VSS 128
DDR_A_D32 129 130 DDR_A_D36
DQ32 DQ36

1
DDR_A_D33 131 132 DDR_A_D37 1 1 1
DQ33 DQ37 C66 C162 C161 R82
133 VSS VSS 134
DDR_A_DQS#4 135 136 DDR_A_DM4 @ 1K_0402_1%
DQS4# DM4
1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K

DDR_A_DQS4 137 138

B DQS4 VSS DDR_A_D38 2 2 2 B
139 140 Layout Note:
2
DDR_A_D34 VSS DQ38 DDR_A_D39
141 DQ34 DQ39 142
DDR_A_D35 143 DQ35 VSS 144 Place near JDDRH
145 146 DDR_A_D44
DDR_A_D40 VSS DQ44 DDR_A_D45
147 DQ40 DQ45 148
DDR_A_D41 149 150 +1.5V
DQ41 VSS DDR_A_DQS#5
DDR_A_DM5
151 VSS DQS5# 152
DDR_A_DQS5 C218 1
Layout Note:
2 390U_2.5V_M_R10

+
153 DM5 DQS5 154
155 VSS VSS 156 Close to JDDRH.126 Place near JDDRH.203 and 204
DDR_A_D42 157 158 DDR_A_D46
DDR_A_D43 DQ42 DQ46 DDR_A_D47 C166 1
159 DQ43 DQ47 160 2 0.1U_0402_16V4Z
161 VSS VSS 162
DDR_A_D48 163 164 DDR_A_D52 C168 1 2 0.1U_0402_16V4Z
DDR_A_D49 DQ48 DQ52 DDR_A_D53
165 DQ49 DQ53 166
167 168 C171 1 2 0.1U_0402_16V4Z +0.75VS +1.5V
DDR_A_DQS#6 VSS VSS DDR_A_DM6
169 DQS6# DM6 170
DDR_A_DQS6 171 172 C174 1 2 0.1U_0402_16V4Z @
DQS6 VSS DDR_A_D54 C85
173 VSS DQ54 174 1 2 0.1U_0402_16V4Z
DDR_A_D50 175 176 DDR_A_D55 C173 1 2 0.1U_0402_16V4Z
DDR_A_D51 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_A_D60 C176 1 2 0.1U_0402_16V4Z
DDR_A_D56 VSS DQ60 DDR_A_D61 C84
181 DQ56 DQ61 182 1 2 4.7U_0603_6.3V6K
DDR_A_D57 183 184 C179 1 2 0.1U_0402_16V4Z
DQ57 VSS DDR_A_DQS#7
185 VSS DQS7# 186
DDR_A_DM7 187 188 DDR_A_DQS7 C178 1 2 0.1U_0402_16V4Z C186 1 2 0.1U_0402_16V4Z
DM7 DQS7
189 VSS VSS 190
DDR_A_D58 191 192 DDR_A_D62 C185 1 2 0.1U_0402_16V4Z C205 1 2 0.1U_0402_16V4Z
DDR_A_D59 DQ58 DQ62 DDR_A_D63
193 DQ59 DQ63 194
R90 1 2 195 196 C180 1 2 0.1U_0402_16V4Z
10K_0402_5% VSS VSS MEM_MA_EVENT#
A 197 SA0 EVENT# 198 MEM_MA_EVENT# 6 A
199 200 FCH_SDATA0
+3VS VDDSPD SDA FCH_SDATA0 11,23,32
FCH_SCLK0
0.1U_0402_16V4Z
2.2U_0603_6.3V6K

201 SA1 SCL 202 FCH_SCLK0 11,23,32

1 1 +0.75VS 203 VTT VTT 204 +0.75VS
1

C182
C181 205 GND2 206
R91 GND1 BOSS1
207 208
2 2 10K_0402_5% GND2
BOSS1 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title
2

LOTES_AAA-DDR-111-K01_204P
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 10 of 51
5 4 3 2 1
 A B C D E

+VREF_DQB
DDR_B_D0
+1.5V

1
3
5
JDDRL
VREF_DQ
VSS
DQ0
VSS
DQ4
DQ5
2
4
6
+1.5V

DDR_B_D4
DDR_B_D5
DDR3 SO-DIMM B
Standard Type
DDR_B_DQS#[0..7]

DDR_B_DQS[0..7]
www.qdzbwx.com 6
6

DDR_B_D1 7 8 DDR_B_D[0..63] 6
DQ1 VSS DDR_B_DQS#0
9 VSS DQS0# 10
DDR_B_DM0 11 12 DDR_B_DQS0 DDR_B_MA[0..15] 6
DM0 DQS0
13 VSS VSS 14
DDR_B_D2 15 16 DDR_B_D6 DDR_B_DM[0..7] 6
DDR_B_D3 DQ2 DQ6 DDR_B_D7
17 DQ3 DQ7 18
19 VSS VSS 20
DDR_B_D8 21 22 DDR_B_D12
DDR_B_D9 DQ8 DQ12 DDR_B_D13
1
23 DQ9 DQ13 24 1
25 VSS VSS 26
DDR_B_DQS#1 27 28 DDR_B_DM1
DDR_B_DQS1 DQS1# DM1 MEM_MB_RST#
29 DQS1 RESET# 30 MEM_MB_RST# 6
31 VSS VSS 32
DDR_B_D10 33 34 DDR_B_D14
DDR_B_D11 DQ10 DQ14 DDR_B_D15
35 DQ11 DQ15 36
37 VSS VSS 38
DDR_B_D16 39 40 DDR_B_D20
DDR_B_D17 DQ16 DQ20 DDR_B_D21
41 DQ17 DQ21 42
+1.5V
43 VSS VSS 44
DDR_B_DQS#2 45 46 DDR_B_DM2
DDR_B_DQS2 DQS2# DM2
47 DQS2 VSS 48

1
49 50 DDR_B_D22
DDR_B_D18 VSS DQ22 DDR_B_D23 R83
51 DQ18 DQ23 52
DDR_B_D19 53 54 1K_0402_1%
DQ19 VSS DDR_B_D28
55 VSS DQ28 56
DDR_B_D24 57 58 DDR_B_D29

2
DDR_B_D25 DQ24 DQ29
59 DQ25 VSS 60
61 62 DDR_B_DQS#3 +VREF_DQB
DDR_B_DM3 VSS DQS3# DDR_B_DQS3
63 DM3 DQS3 64
65 VSS VSS 66

1
DDR_B_D26 67 68 DDR_B_D30 1 1 1
DDR_B_D27 DQ26 DQ30 DDR_B_D31 C67 C184 C183 R84
69 DQ27 DQ31 70
71 72 @ 1K_0402_1%
VSS VSS

1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K
2 2 2

2
DDR_B_CKE0 73 74 DDR_B_CKE1
6 DDR_B_CKE0 CKE0 CKE1 DDR_B_CKE1 6
75 VDD VDD 76
77 78 DDR_B_MA15
DDR_B_BS2 NC A15 DDR_B_MA14
2
6 DDR_B_BS2 79 BA2 A14 80 2
81 VDD VDD 82
DDR_B_MA12 83 84 DDR_B_MA11
DDR_B_MA9 A12/BC# A11 DDR_B_MA7
85 A9 A7 86

DDR_B_MA8
87 VDD VDD 88
DDR_B_MA6
Close to JDDRL.1
89 A8 A6 90
DDR_B_MA5 91 92 DDR_B_MA4
A5 A4
93 VDD VDD 94
DDR_B_MA3 95 96 DDR_B_MA2
DDR_B_MA1 A3 A2 DDR_B_MA0
97 A1 A0 98
99 VDD VDD 100
DDR_B_CLK0 101 102 DDR_B_CLK1
6 DDR_B_CLK0 CK0 CK1 DDR_B_CLK1 6
DDR_B_CLK0# 103 104 DDR_B_CLK1#
6 DDR_B_CLK0# CK0# CK1# DDR_B_CLK1# 6
105 VDD VDD 106
DDR_B_MA10 DDR_B_BS1 +1.5V
107 A10/AP BA1 108 DDR_B_BS1 6
DDR_B_BS0 109 110 DDR_B_RAS#
6 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 6
111 VDD VDD 112

1
DDR_B_WE# 113 114 DDR_B_SCS0#
6 DDR_B_WE# WE# S0# DDR_B_SCS0# 6
DDR_B_CAS# 115 116 DDR_B_ODT0 R86
6 DDR_B_CAS# CAS# ODT0 DDR_B_ODT0 6
117 118 1K_0402_1%
DDR_B_MA13 VDD VDD DDR_B_ODT1
119 A13 ODT1 120 DDR_B_ODT1 6
DDR_B_SCS1# 121 122

2
6 DDR_B_SCS1# S1# NC
123 VDD VDD 124
125 126 +VREF_CAB
TEST VREF_CA
127 VSS VSS 128
DDR_B_D37 129 130 DDR_B_D32
DQ32 DQ36

1
DDR_B_D36 131 132 DDR_B_D33 1 1 1
DQ33 DQ37 C68 C188 C187 R94
133 VSS VSS 134
DDR_B_DQS#4 135 136 DDR_B_DM4 @ 1K_0402_1%
DQS4# DM4
1000P_0402_50V7K

0.1U_0402_16V7K

2.2U_0603_6.3V6K
DDR_B_DQS4 137 138
3 DQS4 VSS DDR_B_D38 2 2 2 3
139 140 Layout Note:

2
DDR_B_D34 VSS DQ38 DDR_B_D39
141 DQ34 DQ39 142
DDR_B_D35 143 DQ35 VSS 144 Place near JDDRH
145 146 DDR_B_D44
DDR_B_D40 VSS DQ44 DDR_B_D45
147 DQ40 DQ45 148
DDR_B_D41 149 150
DQ41 VSS DDR_B_DQS#5
DDR_B_DM5
151 VSS DQS5# 152
DDR_B_DQS5 +1.5V Layout Note:
153 DM5 DQS5 154
155 VSS VSS 156 Close to JDDRL.126 Place near JDDRH.203 and 204
DDR_B_D42 157 158 DDR_B_D46
DDR_B_D43 DQ42 DQ46 DDR_B_D47 C167 1
159 DQ43 DQ47 160 2 0.1U_0402_16V4Z
161 VSS VSS 162
DDR_B_D48 163 164 DDR_B_D52 C169 1 2 0.1U_0402_16V4Z
DDR_B_D49 DQ48 DQ52 DDR_B_D53
165 DQ49 DQ53 166
167 168 C172 1 2 0.1U_0402_16V4Z +0.75VS +1.5V
DDR_B_DQS#6 VSS VSS DDR_B_DM6
169 DQS6# DM6 170
DDR_B_DQS6 171 172 C175 1 2 0.1U_0402_16V4Z @
DQS6 VSS DDR_B_D50 C87
173 VSS DQ54 174 1 2 0.1U_0402_16V4Z
DDR_B_D54 175 176 DDR_B_D51 C195 1 2 0.1U_0402_16V4Z
DDR_B_D55 DQ50 DQ55
177 DQ51 VSS 178
179 180 DDR_B_D60 C177 1 2 0.1U_0402_16V4Z
DDR_B_D56 VSS DQ60 DDR_B_D61 C86
181 DQ56 DQ61 182 1 2 4.7U_0603_6.3V6K
DDR_B_D57 183 184 C190 1 2 0.1U_0402_16V4Z
DQ57 VSS DDR_B_DQS#7
185 VSS DQS7# 186
DDR_B_DM7 187 188 DDR_B_DQS7 C191 1 2 0.1U_0402_16V4Z C194 1 2 0.1U_0402_16V4Z
DM7 DQS7
189 VSS VSS 190
DDR_B_D58 191 192 DDR_B_D62 C192 1 2 0.1U_0402_16V4Z C206 1 2 0.1U_0402_16V4Z
DDR_B_D59 DQ58 DQ62 DDR_B_D63
193 DQ59 DQ63 194
R98 1 2 195 196 C193 1 2 0.1U_0402_16V4Z
10K_0402_5% VSS VSS MEM_MB_EVENT#
4 197 SA0 EVENT# 198 MEM_MB_EVENT# 6 4
199 200 FCH_SDATA0
+3VS VDDSPD SDA FCH_SDATA0 10,23,32
201 202 FCH_SCLK0
SA1 SCL FCH_SCLK0 10,23,32
2.2U_0603_6.3V6K
1 1 +0.75VS 203 204 +0.75VS
VTT VTT
2

R99 205 GND2 206

C207 C208 10K_0402_5% GND1 BOSS1
207 208
@ 2 2 @ GND2
BOSS1 BOSS2 Security Classification Compal Secret Data Compal Electronics, Inc.
0.1U_0402_16V4Z 2011/01/06 2012/01/06 Title
Issued Date Deciphered Date
1

LOTES_AAA-DDR-111-K01_204P
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 11 of 51
A B C D E
 A B C D E

5 PCIE_FTX_C_GRX_P[0..15]

5 PCIE_FTX_C_GRX_N[0..15]
PCIE_FTX_C_GRX_P[0..15]

PCIE_FTX_C_GRX_N[0..15]
PCIE_GTX_C_FRX_P[0..15]

PCIE_GTX_C_FRX_N[0..15]
PCIE_GTX_C_FRX_P[0..15]

PCIE_GTX_C_FRX_N[0..15]
5

5
www.qdzbwx.com VGA_INVT_PWM

VGA_ENVDD
1
RV4
@ 2
10K_0402_5%
1 DIS@ 2
RV5 10K_0402_5%

UV1A WHPROR3@ UV1G WHPROR3@

LVDS CONTROL AK27 VGA_INVT_PWM

VARY_BL VGA_INVT_PWM 28
AJ27 VGA_ENVDD
DIGON VGA_ENVDD 28
PCIE_FTX_C_GRX_P0 AA38 Y33 PCIE_GTX_FRX_P0 CV1 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P0
1
PCIE_FTX_C_GRX_N0 PCIE_RX0P PCIE_TX0P PCIE_GTX_FRX_N0 CV2 1
Y37 PCIE_RX0N PCIE_TX0N Y32 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N0

TXCLK_UP_DPF3P AK35
PCIE_FTX_C_GRX_P1 Y35 W33 PCIE_GTX_FRX_P1 CV3 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P1 AL36
PCIE_FTX_C_GRX_N1 PCIE_RX1P PCIE_TX1P PCIE_GTX_FRX_N1 CV4 TXCLK_UN_DPF3N
W36 PCIE_RX1N PCIE_TX1N W32 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N1
TXOUT_U0P_DPF2P AJ38
TXOUT_U0N_DPF2N AK37
PCIE_FTX_C_GRX_P2 W38 U33 PCIE_GTX_FRX_P2 CV5 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P2 Remove FHD 3D Panel
PCIE_FTX_C_GRX_N2 PCIE_RX2P PCIE_TX2P PCIE_GTX_FRX_N2 CV6 PCIE_GTX_C_FRX_N2
V37 PCIE_RX2N PCIE_TX2N U32 1 2 VGA@ 0.1U_0402_16V7K TXOUT_U1P_DPF1P AH35
TXOUT_U1N_DPF1N AJ36

PCIE_FTX_C_GRX_P3 V35 U30 PCIE_GTX_FRX_P3 CV7 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P3 AG38

PCIE_FTX_C_GRX_N3 PCIE_RX3P PCIE_TX3P PCIE_GTX_FRX_N3 CV8 TXOUT_U2P_DPF0P
U36 PCIE_RX3N PCIE_TX3N U29 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N3
TXOUT_U2N_DPF0N AH37

PCIE_FTX_C_GRX_P4 U38 T33 PCIE_GTX_FRX_P4 CV9 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P4

For TXOUT_U3P AF35
AG36
PCIE_RX4P PCIE_TX4P TXOUT_U3N
PCIE_FTX_C_GRX_N4 T37 PCIE_RX4N PCIE_TX4N T32 PCIE_GTX_FRX_N4 CV10 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N4 PowerXpress

PCI EXPRESS INTERFACE

LVTMDP
PCIE_FTX_C_GRX_P5 T35 T30 PCIE_GTX_FRX_P5 CV11 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P5
PCIE_FTX_C_GRX_N5 PCIE_RX5P PCIE_TX5P PCIE_GTX_FRX_N5 CV12 1
R36 PCIE_RX5N PCIE_TX5N T29 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N5
TXCLK_LP_DPE3P AP34
TXCLK_LN_DPE3N AR34

PCIE_FTX_C_GRX_P6 R38 P33 PCIE_GTX_FRX_P6 CV13 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P6 AW37

PCIE_FTX_C_GRX_N6 PCIE_RX6P PCIE_TX6P PCIE_GTX_FRX_N6 CV14 1 TXOUT_L0P_DPE2P
P37 PCIE_RX6N PCIE_TX6N P32 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N6
TXOUT_L0N_DPE2N AU35 Remove LVDS channel
TXOUT_L1P_DPE1P AR37
PCIE_FTX_C_GRX_P7 P35 P30 PCIE_GTX_FRX_P7 CV15 1 2 VGA@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P7 AU39
PCIE_FTX_C_GRX_N7 PCIE_RX7P PCIE_TX7P PCIE_GTX_FRX_N7 CV16 1 PCIE_GTX_C_FRX_N7 TXOUT_L1N_DPE1N
N36 PCIE_RX7N PCIE_TX7N P29 2 VGA@ 0.1U_0402_16V7K
2
TXOUT_L2P_DPE0P AP35 2

TXOUT_L2N_DPE0N AR35
PCIE_FTX_C_GRX_P8 N38 N33 PCIE_GTX_FRX_P8 CV17 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P8
PCIE_FTX_C_GRX_N8 PCIE_RX8P PCIE_TX8P PCIE_GTX_FRX_N8 CV18 1
M37 PCIE_RX8N PCIE_TX8N N32 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N8
TXOUT_L3P AN36
TXOUT_L3N AP37

PCIE_FTX_C_GRX_P9 M35 N30 PCIE_GTX_FRX_P9 CV19 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P9

PCIE_FTX_C_GRX_N9 PCIE_RX9P PCIE_TX9P PCIE_GTX_FRX_N9 CV20 1 PCIE_GTX_C_FRX_N9
L36 PCIE_RX9N PCIE_TX9N N29 2 DIS@ 0.1U_0402_16V7K

216-0772000-PRO_FCBGA962
PCIE_FTX_C_GRX_P10 L38 L33 PCIE_GTX_FRX_P10 CV21 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P10
PCIE_FTX_C_GRX_N10 PCIE_RX10P PCIE_TX10P PCIE_GTX_FRX_N10 CV22 1
K37 PCIE_RX10N PCIE_TX10N L32 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N10

PCIE_FTX_C_GRX_P11 K35 L30 PCIE_GTX_FRX_P11 CV23 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P11

PCIE_FTX_C_GRX_N11 PCIE_RX11P PCIE_TX11P PCIE_GTX_FRX_N11 CV24 1
J36 PCIE_RX11N PCIE_TX11N L29 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N11

PCIE_FTX_C_GRX_P12 J38 K33 PCIE_GTX_FRX_P12 CV25 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P12

PCIE_FTX_C_GRX_N12 PCIE_RX12P PCIE_TX12P PCIE_GTX_FRX_N12 CV26 1 PCIE_GTX_C_FRX_N12
H37 PCIE_RX12N PCIE_TX12N K32 2 DIS@ 0.1U_0402_16V7K

PCIE_FTX_C_GRX_P13 H35 J33 PCIE_GTX_FRX_P13 CV27 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P13 +3VSG

PCIE_FTX_C_GRX_N13 PCIE_RX13P PCIE_TX13P PCIE_GTX_FRX_N13 CV28 1
G36 PCIE_RX13N PCIE_TX13N J32 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N13

PXS@
PCIE_FTX_C_GRX_P14 G38 K30 PCIE_GTX_FRX_P14 CV29 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P14 1 2
PCIE_FTX_C_GRX_N14 PCIE_RX14P PCIE_TX14P PCIE_GTX_FRX_N14 CV30 1 PCIE_GTX_C_FRX_N14
F37 PCIE_RX14N PCIE_TX14N K29 2 DIS@ 0.1U_0402_16V7K CV262 0.1U_0402_16V4Z

3 3
PCIE_FTX_C_GRX_P15 F35 H33 PCIE_GTX_FRX_P15 CV31 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_P15
PCIE_RX15P PCIE_TX15P

5
PCIE_FTX_C_GRX_N15 E37 H32 PCIE_GTX_FRX_N15 CV32 1 2 DIS@ 0.1U_0402_16V7K PCIE_GTX_C_FRX_N15 UV2
PCIE_RX15N PCIE_TX15N
1

P
22 PXS_RST# IN1
4 VGA_RST#
O
22,27,32,33 APU_PCIE_RST# 2 IN2

G
CLOCK
CLK_PEG_VGA AB35 SN74AHC1G08DCKR_SC70-5
22 CLK_PEG_VGA

3
PCIE_REFCLKP

1
CLK_PEG_VGA# AA36 PXS@
22 CLK_PEG_VGA# PCIE_REFCLKN RV10 RV13
100K_0402_5% 100K_0402_5%
CALIBRATION 1 DIS@ 2
@ @
AJ21 Y30 VGA_PCIE_CALRP RV2 1 VGA@ 2 1.27K_0402_1% RV12 0_0402_5%

2
NC#1 PCIE_CALRP
AK21 NC#2
2 VGA@ 1 AH16 PWRGOOD PCIE_CALRN Y29 VGA_PCIE_CALRN RV3 1 VGA@ 2 2K_0402_1% +1.0VSG
RV1 10K_0402_5%

VGA_RST# AA30 PERSTB

216-0772000-PRO_FCBGA962

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 12 of 51
A B C D E
 A B C D E

Strap Name

VIP_DEVICE_EN V2SYNC
Pin Name Pin Straps description <all internal PD>
VIP Device Strap Enable indicates to the software driver (Internal PD)
0: Driver would ignore the value sampled on VHAD_0 during reset
(GENLK_VSYNC) 1: VHAD_0 to determine whether or not a VIP slave device
Setting

0
Don't have this strap
for Whistler
UV1B WHPROR3@

TXCAP_DPA3P
TXCAM_DPA3N
AU24
AV23
VGA_HDMI_CLK+
VGA_HDMI_CLK-

VGA_HDMI_TX0+
VGA_HDMI_CLK+ 30
VGA_HDMI_CLK- 30
www.qdzbwx.com
VGA Disable determines (Internal PD) TX0P_DPA2P AT25 VGA_HDMI_TX0+ 30
VGA_DIS GPIO9 0: VGA Controller capacity enabled 0 MUTI GFX AR24 VGA_HDMI_TX0-
DPA TX0M_DPA2N VGA_HDMI_TX0- 30
1: The device will not be recognized as the system’s VGA controller
AU26 VGA_HDMI_TX1+
TX1P_DPA1P VGA_HDMI_TX1+ 30
Transmitter Power Saving Enable (Internal PD) AV25 VGA_HDMI_TX1-
TX1M_DPA1N VGA_HDMI_TX1- 30
TX_PWRS_ENB GPIO0 0: 50% Tx output swing 1
1: full Tx output swing AR8 AT27 VGA_HDMI_TX2+
DVPCNTL_MVP_0 TX2P_DPA0P VGA_HDMI_TX2+ 30
AU8 AR26 VGA_HDMI_TX2-
DVPCNTL_MVP_1 TX2M_DPA0N VGA_HDMI_TX2- 30
PCI Express Transmitter De-emphasis Enable (Internal PD) AP8 DVPCNTL_0
TX_DEEMPH_EN GPIO1 0: Tx de-emphasis diabled 1 AW8 DVPCNTL_1 TXCBP_DPB3P AR30
1: Tx de-emphasis enabled AR3 DVPCNTL_2 TXCBM_DPB3N AT29
1
AR1 DVPCLK 1
GPIO13,12,11 (config 2,1,0) : (Internal PD) memory apertures VRAM_ID0 AU1 AV31
VRAM_ID1 DVPDATA_0 TX3P_DPB2P
CONFIG[2] GPIO13 a) If BIOS_ROM_EN = 1, then Config[2:0] defines CONFIG[3:0] AU3 DVPDATA_1 TX3M_DPB2N AU30
VRAM_ID2 AW3 DPB
the ROM type. 128 MB 000 VRAM_ID3 DVPDATA_2
CONFIG[1] GPIO12 001 AP6 DVPDATA_3 TX4P_DPB1P AR32
b) If BIOS_ROM_EN = 0, then Config[2:0] defines 256 MB 001 * AW5 DVPDATA_4 TX4M_DPB1N AT31
+3VSG +3VSG
CONFIG[0] GPIO11 the primary memory aperture size. 64 MB 010 AU5 DVPDATA_5
AR6 AT33
32 MB 011 AW6
DVPDATA_6 TX5P_DPB0P
AU32
DVPDATA_7 TX5M_DPB0N
Enable external BIOS ROM device (Internal PD) AU6 DVPDATA_8

2
BIOS_ROM_EN GPIO22 1: Enable 0: Diable 0 AT7 AU14 VGA_EDP_TX3+
DVPDATA_9 TXCCP_DPC3P VGA_EDP_TX3+ 28
AV7 AV13 VGA_EDP_TX3- RV39 RV40
DVPDATA_10 TXCCM_DPC3N VGA_EDP_TX3- 28
00: No audio function; 10: Audio for DisplayPort only; AN7 4.7K_0402_5% 4.7K_0402_5%
AUD[1] HSYNC AV9
DVPDATA_11
AT15 VGA_EDP_TX2+ VGA@ VGA@
Internal Thermal Sensor
01: Audio for DisplayPort and HDMI if adapter is detected DVPDATA_12 TX0P_DPC2P VGA_EDP_TX2+ 28

5
11 AT9 AR14 VGA_EDP_TX2-
VGA_EDP_TX2- 28
VGA@ Address: 0x41 H

1
DVPDATA_13 TX0M_DPC2N QV1B
AUD[0] VSYNC 11: Audio for both DisplayPort and HDMI AR10 DVPDATA_14 For 3D eDP Panel
AW10 DPC AU16 VGA_EDP_TX1+ VGA_SMB_CK2 4 3
DVPDATA_15 TX1P_DPC1P VGA_EDP_TX1+ 28 EC_SMB_CK2 9,32,37,38,39
0= Advertises the PCI-E device as 2.5 GT/s capable at power-on AU10 AV15 VGA_EDP_TX1-
DVPDATA_16 TX1M_DPC1N VGA_EDP_TX1- 28

2
BIF_GEN2_EN GPIO2 1= Advertises the PCI-E device as 5.0 GT/s capable at power-on 0 AP10 VGA@ 2N7002DW-T/R7_SOT363-6
DVPDATA_17 VGA_EDP_TX0+ QV1A
5.0 GT/s capability will be controlled by software AV11 DVPDATA_18 TX2P_DPC0P AT17 VGA_EDP_TX0+ 28
AT11 AR16 VGA_EDP_TX0- VGA_SMB_DA2 1 6
DVPDATA_19 TX2M_DPC0N VGA_EDP_TX0- 28 EC_SMB_DA2 9,32,37,38,39
H2SYNC AR12 DVPDATA_20
(GENLK_CLK) Internal use only. THIS PAD HAS AN INTERNAL AW12 AU20 2N7002DW-T/R7_SOT363-6
DVPDATA_21 TXCDP_DPD3P
RESERVED GPIO8 PULL-DOWN AND MUST BE 0 V AT RESET. The NC AU12 DVPDATA_22 TXCDM_DPD3N AT19
AP12 DVPDATA_23
GPIO21 pad may be left unconnected AT21
TX3P_DPD2P
TX3M_DPD2N AR20
DPD AU22
+3VSG TX4P_DPD1P
Remove LVDS TX4M_DPD1N AV21
I2C AT23
RV36 1 VGA@ VGA_GPIO0 TX5P_DPD0P
2 3K_0402_5% TX5M_DPD0N AR22
TV2 AK26
RV37 1 VGA@ VGA_GPIO1 SCL +3VSG
2 3K_0402_5% TV3 AJ26 SDA
RV38 1 @ 2 3K_0402_5% VGA_GPIO2 AD39 VGA_CRT_R
R VGA_CRT_R 29
GENERAL PURPOSE I/O AD37 VGA_CRT_VSYNC RV26 1 DIS@ 2 3K_0402_5%
RB
RV43 1 @ 2 330K_0402_5% ACIN_VGA VGA_GPIO0 AH20 GPIO_0
VGA_GPIO1 AH18 AE36 VGA_CRT_G VGA_CRT_HSYNC RV27 1 DIS@ 2 3K_0402_5%
GPIO_1 G VGA_CRT_G 29
2 RV45 1 @ 2 3K_0402_5% VGA_GPIO9 VGA_GPIO2 AN16 AD35 2
@ DV1 VGA_SMB_DA2 GPIO_2 GB
AH23 GPIO_3_SMBDATA
RV47 1 VGA@ 2 3K_0402_5% VGA_GPIO11 RB751V40_SC76-2 VGA_SMB_CK2 AJ23 AF37 VGA_CRT_B VGA_HDMI_CLK RV20 1 DHDMI@2 4.7K_0402_5%
GPIO_4_SMBCLK B VGA_CRT_B 29
1 2 ACIN_VGA AH17 AE38
23,37,39,43 ACIN GPIO_5_AC_BATT BB
RV48 1 @ 2 3K_0402_5% VGA_GPIO12 AJ17 DAC1 VGA_HDMI_DATA RV21 1 DHDMI@2 4.7K_0402_5%
VGA_ENBKL GPIO_6 VGA_CRT_HSYNC LV1
28 VGA_ENBKL AK17 GPIO_7_BLON HSYNC AC36 VGA_CRT_HSYNC 29
RV49 1 @ 2 3K_0402_5% VGA_GPIO13 AJ13 AC38 VGA_CRT_VSYNC 0_0603_5%
GPIO_8_ROMSO VSYNC VGA_CRT_VSYNC 29
VGA_GPIO9 AH15 PXS@ VGA_CRT_CLK RV24 1 DIS@ 2 2.2K_0402_5%
RV46 1 @ VGA_GPIO22 GPIO_9_ROMSI
2 3K_0402_5% AJ16 GPIO_10_ROMSCK
VGA_GPIO11 AK16 AB34 RV9 1 VGA@ 2 499_0402_1% VGA_CRT_DATA RV25 1 DIS@ 2 2.2K_0402_5%
RV51 1 @ THM_ALERT# VGA_GPIO12 GPIO_11 RSET
2 10K_0402_5% AL16 GPIO_12 10mil LV1
VGA_GPIO13 AM16 70mA AD34 +A1VDD 1U_0402_6.3V6K 2 1 +1.8VSG
GPIO14_HPD2 GPIO_13 AVDD BLM18PG121SN1D_0603
AM14 GPIO_14_HPD2 AVSSQ AE34
RV44 1 DIS@ 2 10K_0402_5% VGA_ENBKL GPU_VID0 AM13 10mil 1 1 1 DIS@ Remove VGA_LCD_CLK/DATA
48 GPU_VID0 GPIO_15_PWRCNTL_0
AK14 45mA AC33 +VDD1DI CV33 CV34 CV35
GPIO_16_SSIN VDD1DI
RV50 1 VGA@ 2 100K_0402_5% GPIO14_HPD2 THM_ALERT# AG30 GPIO_17_THERMAL_INT VSS1DI AC34 DIS@ DIS@ 10U_0603_6.3V6M
EDP_HPD AN14 0.1U_0402_16V7K DIS@
28 EDP_HPD GPIO_18_HPD3 2 2 2
RV52 1 VGA@ 2 100K_0402_5% EDP_HPD AM17 GPIO_19_CTF
H2SYNC RV14 1 @ 2 3K_0402_5%
GPU_VID1 AL13 AC30
48 GPU_VID1 GPIO_20_PWRCNTL_1 R2
RV53 1 VGA@ 2 100K_0402_5% VGA_HDMI_HPD VGA_GPIO21 AJ14 GPIO_21_BB_EN R2B AC31 LV2 V2SYNC RV15 1 @ 2 3K_0402_5%
VGA_GPIO22 AK13 1U_0402_6.3V6K 2 1 +1.8VSG
RV54 1 @ VGA_GPIO21 PEG_CLKREQ#_R GPIO_22_ROMCSB
2 10K_0402_5% 23 PEG_CLKREQ# 1 @ 2 AN13 GPIO_23_CLKREQB G2 AD30 BLM18PG121SN1D_0603
RV55 0_0402_5% JTAG_TRSTB AM23 AD31 1 1 1 DIS@ NC for Whistler
JTAG_TRSTB G2B
RV61 1 VGA@ 2 100K_0402_5% VGA_HPD4 JTAG_TDI AN23 JTAG_TDI
CV37 CV38 CV36
JTAG_TCK AK23 AF30 DIS@ DIS@ 10U_0603_6.3V6M VGA_CRT_R RV6 1 DIS@ 2 150_0402_1%
JTAG_TCK B2
RV84 1 VGA@ 2 100K_0402_5% VGA_HPD5 JTAG_TMS AL24 JTAG_TMS B2B AF31 0.1U_0402_16V7K DIS@
TV1 JTAG_TDO AM24 2 2 2 VGA_CRT_G RV7 1 DIS@ 2 150_0402_1%
JTAG_TDO
RV85 1 VGA@ 2 100K_0402_5% VGA_HPD6 32 STEREO_SYNC 1 EDP@ 2 GENERICA AJ19 GENERICA
LV2
1 RV62 0_0402_5% AK19 AC32 0_0603_5% VGA_CRT_B RV8 1 DIS@ 2 150_0402_1%
CV261 GENERICB C PXS@
AJ20 GENERICC Y AD32
RV62 0.1U_0402_16V7K AK20 AF32 Close to GPU
0_0402_5% @ VGA_HPD4 GENERICD COMP
AJ24 GENERICE_HPD4
3D@ 2 VGA_HPD5 AH26 DAC2
VGA_HPD6 GENERICF H2SYNC
AH24 GENERICG H2SYNC AD29
AC29 V2SYNC
V2SYNC
+3VSG For Debug For Capilano
VGA_HDMI_HPD AK24 10mil
30 VGA_HDMI_HPD HPD1
50mA AG31 +VDD2DI 1 @ 2 +1.8VSG
VDD2DI RV16 0_0402_5%
VSS2DI AG32
1 @ 2 JTAG_TMS
3 3
RV60 10K_0402_5% +1.8VSG RV86 1 VGA@ 2 499_0402_1% 10mil
1 @ 2 JTAG_TDI 130mA A2VDD AG33 +A2VDD 1 @ 2 +3VSG
RV58 10K_0402_5% RV87 1 VGA@ 2 249_0402_1% 20mil 10mil RV17 0_0402_5% NC for Whistler
1 @ 2 JTAG_TRSTB 1 @ 2 2mA A2VDDQ AD33 +A2VDDQ 1 @ 2 +1.8VSG
RV56 10K_0402_5% RV57 10K_0402_5% CV39 1 2 0.1U_0402_16V7K +VGA_VREF AH13 RV18 0_0402_5% Except A2VSSQ change to TSVSSQ
JTAG_TCK @ VREFG
1 2 A2VSSQ AF33
RV59 10K_0402_5% VGA@
+1.8VSG
LV3
20mil @
R2SET AA29 1 2
2 1 1U_0402_6.3V6K +DPLL_PVDD AM32 RV19 715_0402_1%
BLM18PG121SN1D_0603 DPLL_PVDD
AN32 DPLL_PVSS 75mA For Capilano
VGA@ 1 1 1 20mil
CV40 CV42 CV41 DDC/AUX AM26 VGA_HDMI_CLK
DDC1CLK VGA_HDMI_CLK 30
10U_0603_6.3V6M VGA@ VGA@ +DPLL_VDDC AN31 PLL/CLOCK AN26 VGA_HDMI_DATA HDMI
DPLL_VDDC DDC1DATA VGA_HDMI_DATA 30
VGA@ 0.1U_0402_16V7K 125mA
2 2 2
For DDR3/GDDR3 +1.0VSG XTALIN AUX1P AM27
AV33 XTALIN AUX1N AL27
LV4 XTALOUT AU34
VGA@ 2 1 0.1U_0402_16V7K XTALOUT
DDC2CLK AM19 VRAM STRAP
XTALOUT 2 1 XTALIN BLM18PG121SN1D_0603 AL19
RV88 1M_0402_5% VGA@ XO_IN DDC2DATA
1 1 1 AW34 XO_IN +1.8VSG
(VRAM_ID[0:3] internal pull-down)
CV45 CV43 CV44 AN20
YV1 10U_0603_6.3V6M VGA@ VGA@ XO_IN2 AUX2P
AW35 SS_IN AUX2N AM20
2 1 VGA@ 1U_0402_6.3V6K
2 2 2 VGA_EDP_AUX+ @ VRAM_ID0 @
DDCCLK_AUX3P AL30 VGA_EDP_AUX+ 28 1 2 1 2
27MHZ_16PF_X5H027000FG1H AM30 VGA_EDP_AUX- eDP RV28 10K_0402_5% RV29 10K_0402_5%
DDCDATA_AUX3N VGA_EDP_AUX- 28
VGA@ VGA@ VGA@ 1 @ 2 VRAM_ID1 1 @ 2
CV46 CV47 AL29 RV30 10K_0402_5% RV31 10K_0402_5%
18P_0402_50V8J 18P_0402_50V8J DDCCLK_AUX4P @ VRAM_ID2 @
AF29 DPLUS DDCDATA_AUX4N AM29 1 2 1 2
THERMAL RV32 10K_0402_5% RV33 10K_0402_5%
Remove Thermal InterfaceAG29 DMINUS @ VRAM_ID3 @
DDCCLK_AUX5P AN21 1 2 1 2
AM21 RV34 10K_0402_5% RV35 10K_0402_5%
DDCDATA_AUX5N
AK32 TS_FDO
AJ30 VGA_CRT_CLK
DDC6CLK VGA_CRT_CLK 29
AL31 AJ31 VGA_CRT_DATA CRT
+1.8VSG TS_A DDC6DATA VGA_CRT_DATA 29
For GDDR5 LV5
10mil
DDCCLK_AUX7P AK30 Location
2 1 1U_0402_6.3V6K +TSVDD AJ32 20mA AK29 DDR3 Type Part Number VRAM_ID0 VRAM_ID1 VRAM_ID2 VRAM_ID3
RV89 1 VGA@ 2 10K_0402_5% XO_IN BLM18PG121SN1D_0603 TSVDD DDCDATA_AUX7N
27 MHz AJ33 TSVSS VRAM
4 VGA@ 1 1 1 4
RV90 1 VGA@ 2 10K_0402_5% XO_IN2 100 MHz CV50 CV48 CV49 Samsung (1GB) 64Mx16 900MHz K4W1G1646G-BC11 0 0 0 0
10U_0603_6.3V6M VGA@ VGA@ 216-0772000-PRO_FCBGA962
VGA@ 0.1U_0402_16V7K HYNIX (1GB) 64Mx16 900MHz H5TQ1G63DFR-11C 1 0 0 0
2 2 2
Samsung (2GB) 128Mx16 900MHz K4W2G1646C-HC11 0 1 0 0
HYNIX (2GB) 128Mx16 900MHz H5TQ2G63BFR-11C 1 1 0 0

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 13 of 51
A B C D E
 A B C D E

18,19 MDA[0..63]
MDA[0..63]
UV1C
DDR2
GDDR3/GDDR5
DDR3
WHPROR3@
DDR2
GDDR5/GDDR3
DDR3
MAA[0..12]
MAA[0..12] 18,19
20,21 MDB[0..63]
MDB[0..63]
www.qdzbwx.com
UV1D
DDR2
GDDR3/GDDR5
DDR3
WHPROR3@
DDR2
GDDR5/GDDR3
DDR3
MAB[0..12]
MAB[0..12] 20,21
MDA0 C37 G24 MAA0 MDB0 C5 P8 MAB0
MDA1 DQA0_0/DQA_0 MAA0_0/MAA_0 MAA1 MDB1 DQB0_0/DQB_0 MAB0_0/MAB_0 MAB1
C35 DQA0_1/DQA_1 MAA0_1/MAA_1 J23 C3 DQB0_1/DQB_1 MAB0_1/MAB_1 T9
MDA2 MAA2 MDB2 MAB2

MEMORY INTERFACE A
A35 DQA0_2/DQA_2 MAA0_2/MAA_2 H24 E3 DQB0_2/DQB_2 MAB0_2/MAB_2 P9
MDA3 MAA3 MDB3 MAB3

MEMORY INTERFACE B
E34 DQA0_3/DQA_3 MAA0_3/MAA_3 J24 E1 DQB0_3/DQB_3 MAB0_3/MAB_3 N7
MDA4 G32 H26 MAA4 MDB4 F1 N8 MAB4
MDA5 DQA0_4/DQA_4 MAA0_4/MAA_4 MAA5 MDB5 DQB0_4/DQB_4 MAB0_4/MAB_4 MAB5
D33 DQA0_5/DQA_5 MAA0_5/MAA_5 J26 F3 DQB0_5/DQB_5 MAB0_5/MAB_5 N9
MDA6 F32 H21 MAA6 MDB6 F5 U9 MAB6
MDA7 DQA0_6/DQA_6 MAA0_6/MAA_6 MAA7 MDB7 DQB0_6/DQB_6 MAB0_6/MAB_6 MAB7
E32 DQA0_7/DQA_7 MAA0_7/MAA_7 G21 G4 DQB0_7/DQB_7 MAB0_7/MAB_7 U8
MDA8 D31 H19 MAA8 MDB8 H5 Y9 MAB8
MDA9 DQA0_8/DQA_8 MAA1_0/MAA_8 MAA9 MDB9 DQB0_8/DQB_8 MAB1_0/MAB_8 MAB9
F30 DQA0_9/DQA_9 MAA1_1/MAA_9 H20 H6 DQB0_9/DQB_9 MAB1_1/MAB_9 W9
1 MDA10 C30 L13 MAA10 MDB10 J4 AC8 MAB10 1
MDA11 DQA0_10/DQA_10 MAA1_2/MAA_10 MAA11 MDB11 DQB0_10/DQB_10 MAB1_2/MAB_10 MAB11
A30 DQA0_11/DQA_11 MAA1_3/MAA_11 G16 K6 DQB0_11/DQB_11 MAB1_3/MAB_11 AC9
MDA12 F28 J16 MAA12 A_BA[0..2] MDB12 K5 AA7 MAB12 B_BA[0..2]
DQA0_12/DQA_12 MAA1_4/MAA_12 A_BA[0..2] 18,19 DQB0_12/DQB_12 MAB1_4/MAB_12 B_BA[0..2] 20,21
MDA13 C28 H16 A_BA2 MDB13 L4 AA8 B_BA2
MDA14 DQA0_13/DQA_13 MAA1_5/MAA_13_BA2 A_BA0 MDB14 DQB0_13/DQB_13 MAB1_5/BA2 B_BA0
A28 DQA0_14/DQA_14 MAA1_6/MAA_14_BA0 J17 M6 DQB0_14/DQB_14 MAB1_6/BA0 Y8
MDA15 E28 H17 A_BA1 MDB15 M1 AA9 B_BA1
MDA16 DQA0_15/DQA_15 MAA1_7/MAA_A15_BA1 DQMA[0..7] +1.5VSG MDB16 DQB0_15/DQB_15 MAB1_7/BA1 DQMB[0..7]
D27 DQA0_16/DQA_16 DQMA[0..7] 18,19 M3 DQB0_16/DQB_16 DQMB[0..7] 20,21
+1.5VSG MDA17 F26 A32 DQMA0 MDB17 M5 H3 DQMB0
MDA18 DQA0_17/DQA_17 WCKA0_0/DQMA_0 DQMA1 MDB18 DQB0_17/DQB_17 WCKB0_0/DQMB_0 DQMB1
C26 DQA0_18/DQA_18 WCKA0B_0/DQMA_1 C32 N4 DQB0_18/DQB_18 WCKB0B_0/DQMB_1 H1

1
MDA19 A26 D23 DQMA2 MDB19 P6 T3 DQMB2
DQA0_19/DQA_19 WCKA0_1/DQMA_2 DQB0_19/DQB_19 WCKB0_1/DQMB_2
1

MDA20 F24 E22 DQMA3 RV95 MDB20 P5 T5 DQMB3

RV91 MDA21 DQA0_20/DQA_20 WCKA0B_1/DQMA_3 DQMA4 VGA@ MDB21 DQB0_20/DQB_20 WCKB0B_1/DQMB_3 DQMB4
C24 DQA0_21/DQA_21 WCKA1_0/DQMA_4 C14 R4 DQB0_21/DQB_21 WCKB1_0/DQMB_4 AE4
VGA@ MDA22 A24 A14 DQMA5 40.2_0402_1% 15mil MDB22 T6 AF5 DQMB5
40.2_0402_1% MDA23 DQA0_22/DQA_22 WCKA1B_0/DQMA_5 DQMA6 MDB23 DQB0_22/DQB_22 WCKB1B_0/DQMB_5 DQMB6
15mil E24 E10 T1 AK6

2
MDA24 DQA0_23/DQA_23 WCKA1_1/DQMA_6 DQMA7 +MVREFDB MDB24 DQB0_23/DQB_23 WCKB1_1/DQMB_6 DQMB7
C22 D9 U4 AK5
2

+MVREFDA MDA25 DQA0_24/DQA_24 WCKA1B_1/DQMA_7 DQSA[0..7] MDB25 DQB0_24/DQB_24 WCKB1B_1/DQMB_7 DQSB[0..7]

A22 DQA0_25/DQA_25 DQSA[0..7] 18,19 V6 DQB0_25/DQB_25 DQSB[0..7] 20,21

1
MDA26 GDDR5/DDR2/GDDR3 DQSA0 MDB26 GDDR5/DDR2/GDDR3 DQSB0
F22 DQA0_26/DQA_26 EDCA0_0/QSA_0/RDQSA_0 C34 1 V1 DQB0_26/DQB_26 EDCB0_0/QSB_0/RDQSB_0 F6
1

1 MDA27 D21 D29 DQSA1 RV96 CV56 MDB27 V3 K3 DQSB1

RV92 CV51 MDA28 DQA0_27/DQA_27 EDCA0_1/QSA_1/RDQSA_1 DQSA2 VGA@ VGA@ MDB28 DQB0_27/DQB_27 EDCB0_1/QSB_1/RDQSB_1 DQSB2
A20 DQA0_28/DQA_28 EDCA0_2/QSA_2/RDQSA_2 D25 Y6 DQB0_28/DQB_28 EDCB0_2/QSB_2/RDQSB_2 P3
VGA@ VGA@ MDA29 F20 E20 DQSA3 100_0402_1% 0.1U_0402_16V7K MDB29 Y1 V5 DQSB3
100_0402_1% 0.1U_0402_16V7K MDA30 DQA0_29/DQA_29 EDCA0_3/QSA_3/RDQSA_3 DQSA4 2 MDB30 DQB0_29/DQB_29 EDCB0_3/QSB_3/RDQSB_3 DQSB4
D19 E16 Y3 AB5

2
2 MDA31 DQA0_30/DQA_30 EDCA1_0/QSA_4/RDQSA_4 DQSA5 MDB31 DQB0_30/DQB_30 EDCB1_0/QSB_4/RDQSB_4 DQSB5
E18 E12 Y5 AH1
2

MDA32 DQA0_31/DQA_31 EDCA1_1/QSA_5/RDQSA_5 DQSA6 MDB32 DQB0_31/DQB_31 EDCB1_1/QSB_5/RDQSB_5 DQSB6

C18 DQA1_0/DQA_32 EDCA1_2/QSA_6/RDQSA_6 J10 AA4 DQB1_0/DQB_32 EDCB1_2/QSB_6/RDQSB_6 AJ9
MDA33 A18 D7 DQSA7 MDB33 AB6 AM5 DQSB7
MDA34 DQA1_1/DQA_33 EDCA1_3/QSA_7/RDQSA_7 DQSA#[0..7] MDB34 DQB1_1/DQB_33 EDCB1_3/QSB_7/RDQSB_7 DQSB#[0..7]
F18 DQA1_2/DQA_34 DQSA#[0..7] 18,19 AB1 DQB1_2/DQB_34 DQSB#[0..7] 20,21
MDA35 D17 A34 DQSA#0 MDB35 AB3 G7 DQSB#0
MDA36 DQA1_3/DQA_35 DDBIA0_0/QSA_0B/WDQSA_0 DQSA#1 MDB36 DQB1_3/DQB_35 DDBIB0_0/QSB_0B/WDQSB_0 DQSB#1
A16 DQA1_4/DQA_36 DDBIA0_1/QSA_1B/WDQSA_1 E30 AD6 DQB1_4/DQB_36 DDBIB0_1/QSB_1B/WDQSB_1 K1
MDA37 F16 E26 DQSA#2 +1.5VSG MDB37 AD1 P1 DQSB#2
+1.5VSG MDA38 DQA1_5/DQA_37 DDBIA0_2/QSA_2B/WDQSA_2 DQSA#3 MDB38 DQB1_5/DQB_37 DDBIB0_2/QSB_2B/WDQSB_2 DQSB#3
D15 DQA1_6/DQA_38 DDBIA0_3/QSA_3B/WDQSA_3 C20 AD3 DQB1_6/DQB_38 DDBIB0_3/QSB_3B/WDQSB_3 W4
MDA39 E14 C16 DQSA#4 MDB39 AD5 AC4 DQSB#4
DQA1_7/DQA_39 DDBIA1_0/QSA_4B/WDQSA_4 DQB1_7/DQB_39 DDBIB1_0/QSB_4B/WDQSB_4

1
MDA40 F14 C12 DQSA#5 MDB40 AF1 AH3 DQSB#5
DQA1_8/DQA_40 DDBIA1_1/QSA_5B/WDQSA_5 DQB1_8/DQB_40 DDBIB1_1/QSB_5B/WDQSB_5
1

MDA41 D13 J11 DQSA#6 RV97 MDB41 AF3 AJ8 DQSB#6

RV93 MDA42 DQA1_9/DQA_41 DDBIA1_2/QSA_6B/WDQSA_6 DQSA#7 VGA@ MDB42 DQB1_9/DQB_41 DDBIB1_2/QSB_6B/WDQSB_6 DQSB#7
F12 DQA1_10/DQA_42 DDBIA1_3/QSA_7B/WDQSA_7 F8 AF6 DQB1_10/DQB_42 DDBIB1_3/QSB_7B/WDQSB_7 AM3
VGA@ MDA43 A12 40.2_0402_1% 15mil MDB43 AG4
40.2_0402_1% MDA44 DQA1_11/DQA_43 ODTA0 MDB44 DQB1_11/DQB_43 ODTB0
2 15mil D11 J21 ODTA0 18 AH5 T7 ODTB0 20 2

2
MDA45 DQA1_12/DQA_44 ADBIA0/ODTA0 ODTA1 +MVREFSB MDB45 DQB1_12/DQB_44 ADBIB0/ODTB0 ODTB1
F10 G19 ODTA1 19 AH6 W7 ODTB1 21
2

+MVREFSA MDA46 DQA1_13/DQA_45 ADBIA1/ODTA1 MDB46 DQB1_13/DQB_45 ADBIB1/ODTB1

A10 DQA1_14/DQA_46 AJ4 DQB1_14/DQB_46

1
MDA47 C10 H27 CLKA0 1 MDB47 AK3 L9 CLKB0
DQA1_15/DQA_47 CLKA0 CLKA0 18 DQB1_15/DQB_47 CLKB0 CLKB0 20
1

1 MDA48 G13 G27 CLKA0# RV99 CV55 MDB48 AF8 L8 CLKB0#

DQA1_16/DQA_48 CLKA0B CLKA0# 18 DQB1_16/DQB_48 CLKB0B CLKB0# 20
RV94 CV52 MDA49 H13 VGA@ VGA@ MDB49 AF9
VGA@ VGA@ MDA50 DQA1_17/DQA_49 CLKA1 100_0402_1% 0.1U_0402_16V7K MDB50 DQB1_17/DQB_49 CLKB1
J13 DQA1_18/DQA_50 CLKA1 J14 CLKA1 19 AG8 DQB1_18/DQB_50 CLKB1 AD8 CLKB1 21
100_0402_1% 0.1U_0402_16V7K MDA51 H11 H14 CLKA1# 2 MDB51 AG7 AD7 CLKB1#
CLKA1# 19 CLKB1# 21

2
2 MDA52 DQA1_19/DQA_51 CLKA1B MDB52 DQB1_19/DQB_51 CLKB1B
G10 AK9
2

MDA53 DQA1_20/DQA_52 RASA0# MDB53 DQB1_20/DQB_52 RASB0#

G8 DQA1_21/DQA_53 RASA0B K23 RASA0# 18 AL7 DQB1_21/DQB_53 RASB0B T10 RASB0# 20
MDA54 K9 K19 RASA1# MDB54 AM8 Y10 RASB1#
DQA1_22/DQA_54 RASA1B RASA1# 19 DQB1_22/DQB_54 RASB1B RASB1# 21
MDA55 K10 MDB55 AM7
MDA56 DQA1_23/DQA_55 CASA0# MDB56 DQB1_23/DQB_55 CASB0#
G9 DQA1_24/DQA_56 CASA0B K20 CASA0# 18 AK1 DQB1_24/DQB_56 CASB0B W10 CASB0# 20
MDA57 A8 K17 CASA1# MDB57 AL4 AA10 CASB1#
DQA1_25/DQA_57 CASA1B CASA1# 19 DQB1_25/DQB_57 CASB1B CASB1# 21
MDA58 C8 MDB58 AM6
MDA59 DQA1_26/DQA_58 CSA0#_0 MDB59 DQB1_26/DQB_58 CSB0#_0
E8 DQA1_27/DQA_59 CSA0B_0 K24 CSA0#_0 18 AM1 DQB1_27/DQB_59 CSB0B_0 P10 CSB0#_0 20
MDA60 A6 K27 MDB60 AN4 L10
MDA61 DQA1_28/DQA_60 CSA0B_1 MDB61 DQB1_28/DQB_60 CSB0B_1
C6 DQA1_29/DQA_61 AP3 DQB1_29/DQB_61
MDA62 E6 M13 CSA1#_0 +3VSG MDB62 AP1 AD10 CSB1#_0
DQA1_30/DQA_62 CSA1B_0 CSA1#_0 19 DQB1_30/DQB_62 CSB1B_0 CSB1#_0 21
MDA63 A5 K16 MDB63 AP5 AC10
DQA1_31/DQA_63 CSA1B_1 DQB1_31/DQB_63 CSB1B_1
+MVREFDA L18 K21 CKEA0 U10 CKEB0
MVREFDA CKEA0 CKEA0 18 CKEB0 CKEB0 20

1
+1.5VSG +MVREFSA L20 J20 CKEA1 +MVREFDB Y12 AA11 CKEB1
MVREFSA CKEA1 CKEA1 19 MVREFDB CKEB1 CKEB1 21
RV113 +MVREFSBAA12
RV101 MVREFSB
1 VGA@ 2 240_0402_1% L27 MEM_CALRN0 WEA0B K26 WEA0#
WEA0# 18 5.11K_0402_1% WEB0B N10 WEB0#
WEB0# 20
RV103 1 VGA@ 2 240_0402_1% N12 L15 WEA1# @ AB11 WEB1#
MEM_CALRN1 WEA1B WEA1# 19 WEB1B WEB1# 21
RV105 1 VGA@ 2 240_0402_1% AG12

2
MEM_CALRN2
RV110 1 VGA@ 2 240_0402_1% M12 H23 MAA13 TESTEN AD28 T8 MAB13 For 128MbX16
MEM_CALRP1 MAA0_8 MAA13 18,19 TESTEN MAB0_8 MAB13 20,21

GDDR5
GDDR5

RV107 1 VGA@ 2 240_0402_1% M27 J19 W8

RV109 MEM_CALRP0 MAA1_8 MAB1_8
1 VGA@ 2 240_0402_1% AH12 MEM_CALRP2 For 128MbX16 TEST_MCLK AK10 CLKTESTA

1
TEST_YCLK AL10 AH11 1 VGA@ 2 1 VGA@ 2
CLKTESTB DRAM_RST VRAM_RST# 18,19,20,21
RV114 RV76 10_0402_5% RV65 51.1_0402_1%
1K_0402_5%

1
VGA@ 2 2 1
3 3
CV58 CV57 RV117 CV59

2
0.1U_0402_16V4Z 0.1U_0402_16V4Z 4.99K_0402_1% 120P_0402_50V8
@ @ 216-0772000-PRO_FCBGA962 VGA@ VGA@
216-0772000-PRO_FCBGA962 1 1 2

2
1

1
RV116 RV115 Place all these components close
51.1_0402_1% 51.1_0402_1%
@ @ to GPU (Within 25mm) and
keep all component close to

2
each Other (within5mm) except Rser2

Route 50ohm single-ended

and 100ohm diff and keep short

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 14 of 51
A B C D E
 A B C D E

+1.5VSG 1U_0402_6.3V6K

CV96
1
CV97
1
1U_0402_6.3V6K

CV99
1
CV98
1
1U_0402_6.3V6K

CV100
1
CV101
1
1U_0402_6.3V6K

CV103
1
CV102
1 UV1E

MEM I/O
WHPROR3@

PCIE
40mil
www.qdzbwx.com
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ LV11
2 2 2 2 2 2 2 2 +PCIE_VDDR 0.1U_0402_16V7K 1U_0402_6.3V6K 10U_0603_6.3V6M 2
AC7 VDDR1#1 PCIE_VDDR#1 AA31 1 +1.8VSG
AD11 AA32 FBMA-L11-201209-221LMA30T_0805
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K VDDR1#2 PCIE_VDDR#2 VGA@
AF7 VDDR1#3 PCIE_VDDR#3 AA33 1 1 1 1 1 1
AG10 AA34 CV147 CV146 CV144 CV145 CV143 CV142
VDDR1#4 PCIE_VDDR#4
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
AJ7 VDDR1#5 440mA PCIE_VDDR#5 V28
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
AK8 VDDR1#6 PCIE_VDDR#6 W29
2 2 2 2 2 2
AL9 VDDR1#7 PCIE_VDDR#7 W30
1 1 1 1 1 1 1 1 G11 VDDR1#8 PCIE_VDDR#8 Y31
CV104 CV105 CV107 CV106 CV108 CV110 CV111 CV109 G14 0.1U_0402_16V7K 1U_0402_6.3V6K 1U_0402_6.3V6K
VDDR1#9
1 G17 VDDR1#10
1
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ G20 G30 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M +1.0VSG
2 2 2 2 2 2 2 2 VDDR1#11 PCIE_VDDC#1
G23 VDDR1#12 PCIE_VDDC#2 G31
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K G26 H29 1 1 1 1 1 1 1 1
VDDR1#13 PCIE_VDDC#3 CV148 CV149 CV150 CV151 CV181 CV193 CV194 CV195
G29 VDDR1#14 PCIE_VDDC#4 H30
10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K H10 J29
VDDR1#15 PCIE_VDDC#5 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
J7 VDDR1#16 PCIE_VDDC#6 J30
2 2 2 2 2 2 2 2
CV116
1
CV117
1
CV118
1
CV119
1
CV120
1
CV112
1
CV114
1
CV115
1
CV113
1 J9 VDDR1#17 2A PCIE_VDDC#7 L28
K11 VDDR1#18 3.4A PCIE_VDDC#8 M28
1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
K13 VDDR1#19 PCIE_VDDC#9 N28
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ K8 R28
2 2 2 2 2 2 2 2 2 VDDR1#20 PCIE_VDDC#10
L12 VDDR1#21 PCIE_VDDC#11 T28
L16 VDDR1#22 PCIE_VDDC#12 U28
10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K L21 VDDR1#23
L23 VDDR1#24
LV6 L26 AA15 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K +VGA_CORE
1U_0402_6.3V6K VDDR1#25 CORE VDDC#1
+1.8VSG 2 1 L7 VDDR1#26 VDDC#2 AA17 1 1 1 1 1 1 1 1 1 1
BLM18PG121SN1D_0603 M11 AA20 CV196 CV197 CV198 CV199 CV200 CV201 CV202 CV203 CV204 CV205 Capilano LP: VDDC+VDDCI= 27.6A
VGA@ VDDR1#27 VDDC#3
1 1 1 N11 VDDR1#28 VDDC#4 AA22
CV121 CV123 CV124 P7 AA24 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ (Eng. clock= 500MHz, Mem. clock= 900 MHz)
VDDR1#29 VDDC#5 2 2 2 2 2 2 2 2 2 2
R11 VDDR1#30 VDDC#6 AA27
VGA@ VGA@ VGA@ U11 AB16
2 2 2 VDDR1#31 VDDC#7 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K Whistler LP: VDDC+VDDCI= 24.7A
U7 VDDR1#32 VDDC#8 AB18
Y11 VDDR1#33 VDDC#9 AB21 (Eng. clock= 485MHz, Mem. clock= 800 MHz)
10U_0603_6.3V6M 0.1U_0402_16V7K Y7 AB23 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
VDDR1#34 VDDC#10
VDDC#11 AB26 1 1 1 1 1 1 1 1 1 1
1U_0402_6.3V6K AB28 CV206 CV207 CV208 CV209 CV210 CV211 CV212 CV213 CV215 CV214
+3VSG VDDC#12 Whistler PRO: VDDC+VDDCI= 32.6A
VDDC#13 AC17
1 1 1 VDDC#14 AC20 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ (Eng. clock= 600MHz, Mem. clock= 900 MHz)
CV127 CV125 CV126 LEVEL 2 2 2 2 2 2 2 2 2 2
20mil TRANSLATION VDDC#15 AC22
VDDC#16 AC24

POWER
VGA@ VGA@ VGA@ +VDD_CT AF26 AC27 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
2 2 2 VDD_CT#1 VDDC#17
AF27 VDD_CT#2 VDDC#18 AD18
10U_0603_6.3V6M 0.1U_0402_16V7K AG26 219mA AD21 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
VDD_CT#3 VDDC#19
2
AG27 VDD_CT#4 VDDC#20 AD23 1 1 1 1 1 1 1 1 1 2
LV7 AD26 CV216 CV217 CV219 CV218 CV223 CV220 CV222
1U_0402_6.3V6K VDDC#21 + CV221 + CV224
+1.8VSG 2 1 VDDC#22 AF17
BLM18PG121SN1D_0603 I/O VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 390U_2.5V_M_R10 390U_2.5V_M_R10
VGA@
10mil VDDC#23 AF20
2 2 2 2 2 2 2 VGA@ VGA@
1 1 1 AF23 VDDR3#1 VDDC#24 AF22
CV130 CV128 CV129 2 2
AF24 VDDR3#2 VDDC#25 AG16
AG23 60mA AG18 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M 10U_0603_6.3V6M
VGA@ VGA@ VGA@ VDDR3#3 VDDC#26
AG24 VDDR3#4 VDDC#27 AG21
2 2 2
10U_0603_6.3V6M 0.1U_0402_16V7K
20mil 25A VDDC#28 AH22
VDDC#29 AH27
+VDDR4_5 AF13 AH28
VDDR4#4 VDDC#30
AF15 VDDR4#5 VDDC#31 M26 55mA +BIF_VDDC：
AG13 VDDR4#7 VDDC#32 N24 Capilano: Connect to +VGA_CORE
AG15 N27 +BIF_VDDC +BIF_VDDC
VDDR4#8 VDDC#33 Whisler:
170mA VDDC#34 R18
VDDC#35 R21 Normal mode: +VGA_CORE
AD12 VDDR4#1 VDDC#36 R23 BACO mode: +1.0VSG
AF11 VDDR4#2 VDDC#37 R26
AF12 VDDR4#3 VDDC#38 T17
AG11 VDDR4#6 VDDC#39 T20
VDDC#40 T22
VDDC#41 T24
VDDC#42 T27
VDDC#43 U16
M20 NC_VDDRHA VDDC#44 U18
M21 NC_VSSRHA VDDC#45 U21
VDDC#46 U23
VDDC#47 U26
LV8 V12 V17
1U_0402_6.3V6K 0.1U_0402_16V7K NC_VDDRHB VDDC#48
+1.8VSG 2 1 U12 NC_VSSRHB VDDC#49 V20
BLM18PG121SN1D_0603 V22
VGA@ VDDC#50
1 1 1 1 1 VDDC#51 V24
CV131 CV132 CV133 CV135 CV134 Combined with PCIE_VDDR V27
VDDC#52
VDDC#53 Y16
VGA@ VGA@ VGA@ VGA@ VGA@ PLL Y18
2 2 2 2 2 +PCIE_VDDR VDDC#54
3 AB37 PCIE_PVDD VDDC#55 Y21 3

VDDC#56 Y23
10U_0603_6.3V6M 1U_0402_6.3V6K 0.1U_0402_16V7K 20mil H7 Y26
+MPV_18 MPV18#1 VDDC#57
H8 MPV18#2 150mA VDDC#58 Y28

LV9 10mil
+1.8VSG 2 1 1U_0402_6.3V6K +SPV_18 AM10 75mA LV12
BLM18PG121SN1D_0603 LV10 SPV18 +VDDCI 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
VGA@ 1U_0402_6.3V6K
20mil +SPV10 VDDCI#1 AA13 2 1
FBMA-L11-201209-121LMA50T_0805
+VGA_CORE
1 1
CV136 CV137 CV138
1 +1.0VSG 2 1
BLM18PG121SN1D_0603
AN9 SPV10 120mA VDDCI#2 AB13
CV225
1
CV226
1
CV227
1
CV228
1
CV229
1
CV230
1
CV231
1
CV232
1
CV234
1
CV233
1
VGA@
VDDCI#3 AC12
VGA@ 1 1 1 AN10 AC15
VGA@ VGA@ VGA@ CV139 CV140 CV141 SPVSS VDDCI#4 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VDDCI#5 AD13
2 2 2 2 2 2 2 2 2 2 2 2 2
VDDCI#6 AD16
VGA@ VGA@ VGA@ M15
10U_0603_6.3V6M 0.1U_0402_16V7K 2 2 2 VDDCI#7 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K 1U_0402_6.3V6K
VDDCI#8 M16
VOLTAGE M18
10U_0603_6.3V6M 0.1U_0402_16V7K SENESE VDDCI#9
VDDCI#10 M23
VDDCI#11 N13
VCORE_SENSE AF28 4A VDDCI#12 N15
48 VCORE_SENSE FB_VDDC
VDDCI#13 N17
N20 0.1U_0402_16V7K 10U_0603_6.3V6M
VDDCI#14
AG28 FB_VDDCI N22
ISOLATED VDDCI#15 R12
CORE I/O VDDCI#16 R13 1 1 1 1 1
VDDCI#17 CV235 CV236 CV237 CV239 CV238
AH29 FB_GND VDDCI#18 R16
VDDCI#19 T12
T15 VGA@ VGA@ VGA@ VGA@ VGA@
VDDCI#20 2 2 2 2 2
VDDCI#21 V15
VDDCI#22 Y13
1U_0402_6.3V6K 10U_0603_6.3V6M 10U_0603_6.3V6M

216-0772000-PRO_FCBGA962

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 15 of 51
A B C D E
 A B C D E

AB39
UV1F WHPROR3@

A3
www.qdzbwx.com
PCIE_VSS#1 GND#1
E39 PCIE_VSS#2 GND#2 A37
F34 PCIE_VSS#3 GND#3 AA16
F39 PCIE_VSS#4 GND#4 AA18
G33 PCIE_VSS#5 GND#5 AA2
G34 PCIE_VSS#6 GND#6 AA21
H31 PCIE_VSS#7 GND#7 AA23
H34 PCIE_VSS#8 GND#8 AA26
H39 PCIE_VSS#9 GND#9 AA28
J31 PCIE_VSS#10 GND#10 AA6
1 1
J34 PCIE_VSS#11 GND#11 AB12
K31 AB15 LV13
PCIE_VSS#12 GND#12 LV15 LV15 0_0603_5%
K34 PCIE_VSS#13 GND#13 AB17
K39 AB20 0_0603_5% 0_0603_5% UV1H WHPROR3@ PXS@
PCIE_VSS#14 GND#14 NOEDP@ PXS@
L31 PCIE_VSS#15 GND#15 AB22
L34 AB24 DP C/D POWER DP A/B POWER
PCIE_VSS#16 GND#16
M34 PCIE_VSS#17 GND#17 AB27
LV15
20mil 20mil LV13
M39 PCIE_VSS#18 GND#18 AC11 AP20 DPC_VDD18#1 DPA_VDD18#1 AN24
N31 AC13 +1.8VSG 1 2 1U_0402_6.3V6K +DPCD_VDD18 AP21 130mA130mA AP24 +DPAB_VDD18 1U_0402_6.3V6K 2 1 +1.8VSG
PCIE_VSS#19 GND#19 BLM18PG121SN1D_0603 DPC_VDD18#2 DPA_VDD18#2 BLM18PG121SN1D_0603
N34 PCIE_VSS#20 GND#20 AC16
P31 AC18 EDP@ 1 1 1 1 1 1 DHDMI@
PCIE_VSS#21 GND#21 CV250 CV249 CV251 CV245 CV243 CV244
P34 PCIE_VSS#22 GND#22 AC2 20mil 20mil
P39 PCIE_VSS#23 GND#23 AC21 AP13 DPC_VDD10#1 DPA_VDD10#1 AP31
R34 AC23 EDP@ EDP@ EDP@ +DPCD_VDD10 AT13 110mA 110mA AP32 +DPAB_VDD10 DHDMI@ DHDMI@ DHDMI@
PCIE_VSS#24 GND#24 2 2 2 DPC_VDD10#2 DPA_VDD10#2 2 2 2
T31 PCIE_VSS#25 GND#25 AC26
T34 PCIE_VSS#26 GND#26 AC28
T39 AC6 10U_0603_6.3V6M 0.1U_0402_16V7K AN17 AN27 0.1U_0402_16V7K 10U_0603_6.3V6M
PCIE_VSS#27 GND#27 DPC_VSSR#1 DPA_VSSR#1
U31 PCIE_VSS#28 GND#28 AD15 AP16 DPC_VSSR#2 DPA_VSSR#2 AP27
U34 PCIE_VSS#29 GND#29 AD17 AP17 DPC_VSSR#3 DPA_VSSR#3 AP28
V34 PCIE_VSS#30 GND#30 AD20 AW14 DPC_VSSR#4 DPA_VSSR#4 AW24
V39 PCIE_VSS#31 GND#31 AD22 AW16 DPC_VSSR#5 DPA_VSSR#5 AW26
W31 PCIE_VSS#32 GND#32 AD24
W34 PCIE_VSS#33 GND#33 AD27
Y34 AD9 LV16 LV16 20mil 20mil
PCIE_VSS#34 GND#34 0_0603_5% 0_0603_5% LV14
Y39 PCIE_VSS#35 GND#35 AE2 AP22 DPD_VDD18#1 DPB_VDD18#1 AP25
AE6 NOEDP@ PXS@ +DPCD_VDD18 AP23 130mA 130mA AP26 +DPAB_VDD18 0_0603_5%
GND#36 DPD_VDD18#2 DPB_VDD18#2 PXS@
GND#37 AF10
GND#38 AF16
LV16
20mil
GND#39 AF18
1U_0402_6.3V6K +DPCD_VDD10
20mil LV14
AF21 1 2 AP14 AN33

F15 GND#100
GND GND#40
GND#41
GND#42
AG17
AG2
+1.0VSG
BLM18PG121SN1D_0603
EDP@ 1 1 1
AP15
DPD_VDD10#1
DPD_VDD10#2
DPB_VDD10#1
110mA 110mA
DPB_VDD10#2 AP33 +DPAB_VDD10 1U_0402_6.3V6K 2 1
BLM18PG121SN1D_0603
+1.0VSG
2 CV253 CV252 CV254 DHDMI@ 2
F17 GND#101 GND#43 AG20 1 1 1
F19 AG22 CV248 CV246 CV247
GND#102 GND#44 EDP@ EDP@ EDP@
F21 GND#103 GND#45 AG6 AN19 DPD_VSSR#1 DPB_VSSR#1 AN29
2 2 2 DHDMI@ DHDMI@ DHDMI@
F23 GND#104 GND#46 AG9 AP18 DPD_VSSR#2 DPB_VSSR#2 AP29
2 2 2
F25 GND#105 GND#47 AH21 AP19 DPD_VSSR#3 DPB_VSSR#3 AP30
F27 AJ10 10U_0603_6.3V6M 0.1U_0402_16V7K AW20 AW30
GND#106 GND#48 DPD_VSSR#4 DPB_VSSR#4 0.1U_0402_16V7K 10U_0603_6.3V6M
F29 GND#107 GND#49 AJ11 AW22 DPD_VSSR#5 DPB_VSSR#5 AW32
F31 GND#108 GND#50 AJ2
F33 GND#109 GND#51 AJ28
F7 GND#110 GND#52 AJ6
F9 GND#111 GND#53 AK11 2 VGA@ 1 AW18 DPCD_CALR DPAB_CALR AW28 1 VGA@ 2
G2 AK31 RV162 150_0402_1% RV163 150_0402_1%
GND#112 GND#54
G6 GND#113 GND#55 AK7
LV17
20mil 10mil
H9 GND#114 GND#56 AL11 DP E/F POWER DP PLL POWER
J2 AL14 +1.8VSG 1 2 1U_0402_6.3V6K +DPEF_VDD18 AH34 20mA AU28 +DPAB_VDD18
GND#115 GND#57 BLM18PG121SN1D_0603 DPE_VDD18#1 DPA_PVDD
J27 GND#116 GND#58 AL17 AJ34 DPE_VDD18#2125mA DPA_PVSS AV27
J6 AL2 DIS@ 1 1 1
GND#117 GND#59 CV256 CV255 CV257
J8 GND#118 GND#60 AL20 20mil 10mil
K14 GND#119 GND#61 AL21 PX_EN 17
K7 AL23 DIS@ DIS@ DIS@ +DPEF_VDD10 AL33 20mA AV29 +DPAB_VDD18
GND#120 GND#62 LV17 2 2 2 DPE_VDD10#1 DPB_PVDD
L11 GND#121 GND#63 AL26
0_0603_5%
AM33 DPE_VDD10#2 90mA DPB_PVSS AR28
L17 GND#122 GND#64 AL32
L2 AL6 PXS@ 10U_0603_6.3V6M 0.1U_0402_16V7K 10mil
GND#123 GND#65
L22 GND#124 GND#66 AL8
L24 AM11 AN34 20mA AU18 +DPCD_VDD18
GND#125 GND#67 DPE_VSSR#1 DPC_PVDD
L6 GND#126 GND#68 AM31 AP39 DPE_VSSR#2 DPC_PVSS AV17
M17 GND#127 GND#69 AM9 AR39 DPE_VSSR#3
M22 GND#128 GND#70 AN11 AU37 DPE_VSSR#4 10mil
M24 GND#129 GND#71 AN2
N16 AN30 20mA AV19 +DPCD_VDD18
GND#130 GND#72 DPD_PVDD
N18 GND#131 GND#73 AN6 DPD_PVSS AR18
3
N2 GND#132 GND#74 AN8
LV18
20mil 3
N21 GND#133 GND#75 AP11
0_0603_5% +DPEF_VDD18
AF34 DPF_VDD18#1 10mil
N23 GND#134 GND#76 AP7 AG34 125mA
DPF_VDD18#2
N26 AP9 PXS@ 20mA AM37 +DPEF_VDD18
GND#135 GND#77 DPE_PVDD
N6 GND#136 GND#78 AR5 DPE_PVSS AN38
R15 GND#137 GND#79 B11
LV18
20mil
R17 GND#138 GND#80 B13
1U_0402_6.3V6K +DPEF_VDD10
AK33 DPF_VDD10#1 10mil
R2 GND#139 GND#81 B15 +1.0VSG 1 2 AK34 DPF_VDD10#2 90mA
R20 B17 BLM18PG121SN1D_0603 20mA AL38 +DPEF_VDD18
GND#140 GND#82 DIS@ DPF_PVDD
R22 GND#141 GND#83 B19 1 1 1 DPF_PVSS AM35
R24 B21 CV259 CV258 CV260
GND#142 GND#84
R27 GND#143 GND#85 B23 AF39 DPF_VSSR#1
R6 B25 DIS@ DIS@ DIS@ AH39
GND#144 GND#86 2 2 2 DPF_VSSR#2
T11 GND#145 GND#87 B27 AK39 DPF_VSSR#3
T13 GND#146 GND#88 B29 AL34 DPF_VSSR#4
T16 B31 10U_0603_6.3V6M 0.1U_0402_16V7K AM34
GND#147 GND#89 DPF_VSSR#5
T18 GND#148 GND#90 B33
T21 GND#149 GND#91 B7
T23 GND#150 GND#92 B9
T26 GND#151 GND#93 C1 2 VGA@ 1 AM39 DPEF_CALR
U15 C39 RV111 150_0402_1%
GND#153 GND#94
U17 GND#154 GND#95 E35
U2 E5 216-0772000-PRO_FCBGA962
GND#155 GND#96
U20 GND#156 GND#97 F11
U22 GND#157 GND#98 F13
U24 GND#158
U27 GND#159
U6 GND#160
V11 GND#161
V16 GND#163
V18 GND#164
V21 GND#165
V23 GND#166
4 4
V26 GND#167
W2 GND#168
W6 GND#169
Y15 GND#170
Y17 GND#171
Y20 GND#172
Y22 GND#173 VSS_MECH#1 A39
Y24 AW1
Y27
GND#174
GND#175
VSS_MECH#2
VSS_MECH#3 AW39
Security Classification Compal Secret Data Compal Electronics, Inc.
U13 GND#152 Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title
V13 GND#162
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
216-0772000-PRO_FCBGA962 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 16 of 51
A B C D E
 1 2 3 4 5

www.qdzbwx.com
+3VS CV240
0.1U_0402_16V4Z
1 2

1 BACO@ 1

5
UV4
PXS_PWREN 1

P
22,40 PXS_PWREN IN1
4 BACO_EN#
O BACO_EN# 37,40
+3VS 1 RV74 2 PX_EN# 2 IN2

G
10K_0402_5%
BACO@ SN74AHC1G08DCKR_SC70-5

3
BACO@

1
D BACO@
16 PX_EN 1 BACO@ 2 2 QV2
RV77 0_0402_5% G 2N7002_SOT23-3

1
PX_EN= H : BACO mode S

3
BACO@
PX_EN= L : Normal mode RV78
5.11K_0402_1% +5VS +5VS

2
BACO@ BACO@
RV80 RV82
1K_0402_5% 1K_0402_5%

1
VDDC_EN
CV241 +3VS
0.1U_0402_16V4Z 1.0_EN
2 1

3
2 BACO@ 2

5
UV13 QV7A QV7B
BACO_EN# 1 BACO@ 2 1 BACO@ 2N7002DW-T/R7_SOT363-6

P
RV79 0_0402_5% IN1 BACO@
O 4 2 5
2 2N7002DW-T/R7_SOT363-6
22,40,48 VGA_PWRGD IN2

4
SN74AHC1G08DCKR_SC70-5

3
BACO@

+BIF_VDDC +VGA_CORE
BACO mode: +1.0VSG QV4 20mil QV5
+VGA_CORE: off 30mil NOBACO@
S

+1.5VSG: off +1.0VSG_Q

D

3 1 1 S
3 2 1
RV83 0_0603_5%
+BIF_VDDC= +1.0VSG AO3416_SOT23-3 AO3416_SOT23-3 1
BACO@ BACO@ BACO@
G

G
2

CV242
1.0_EN 22U_0805_6.3V6M
2
3 3

Normal mode:
VDDC_EN
+BIF_VDDC= +VGA_CORE
2

+VGA_CORE
G

QV3 QV6
G

30mil
AO3416 NMOS
3 1 +VGA_CORE_Q1 3 Vgs(th)(Max)= 1V
S

AO3416_SOT23-3 AO3416_SOT23-3 Rds(on)(Max)= 22m ohm @Vgs=4.5V

BACO@ BACO@

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 17 of 51
1 2 3 4 5
 5 4 3 2 1

Memory Partition A - Lower 32 bits www.qdzbwx.com MDA[0..63] 14,19

MAA[0..13] 14,19

DQMA[0..7] 14,19
UV5 UV6
DQSA[0..7] 14,19
+VREFCA_A1 M8 E3 MDA29 +VREFCA_A2 M8 E3 MDA19
VREFCA DQL0 VREFCA DQL0 DQSA#[0..7] 14,19
+VREFDQ_A1 H1 F7 MDA26 +VREFDQ_A2 H1 F7 MDA21
VREFDQ DQL1 MDA30 VREFDQ DQL1 MDA16
DQL2 F2 DQL2 F2 A_BA[0..2] 14,19
D MAA0 N3 F8 MDA24 MAA0 N3 F8 MDA23 Group2 D
MAA1 A0 DQL3 MDA27 MAA1 A0 DQL3 MDA18
P7 A1 DQL4 H3 Group3 P7 A1 DQL4 H3
MAA2 P3 H8 MDA25 MAA2 P3 H8 MDA22
MAA3 A2 DQL5 MDA31 MAA3 A2 DQL5 MDA17
N2 A3 DQL6 G2 N2 A3 DQL6 G2
MAA4 P8 H7 MDA28 MAA4 P8 H7 MDA20
MAA5 A4 DQL7 MAA5 A4 DQL7
P2 A5 P2 A5
MAA6 R8 MAA6 R8
MAA7 A6 MDA3 MAA7 A6 MDA13
R2 A7 DQU0 D7 R2 A7 DQU0 D7
MAA8 T8 C3 MDA6 MAA8 T8 C3 MDA10
VGA@ MAA9 A8 DQU1 MDA1 MAA9 A8 DQU1 MDA15 +1.5VSG +1.5VSG
R3 A9 DQU2 C8 R3 A9 DQU2 C8
CLKA0 1 2 MAA10 L7 C2 MDA4 MAA10 L7 C2 MDA9
RV64 56_0402_1% MAA11 A10/AP DQU3 MDA2 MAA11 A10/AP DQU3 MDA14
R7 A11 DQU4 A7 Group0 R7 A11 DQU4 A7 Group1

1
MAA12 N7 A2 MDA7 MAA12 N7 A2 MDA8
VGA@ MAA13 A12 DQU5 MDA0 MAA13 A12 DQU5 MDA12 RV122 RV124
T3 A13 DQU6 B8 T3 A13 DQU6 B8
CLKA0# 1 2 T7 A3 MDA5 T7 A3 MDA11 4.99K_0402_1% 4.99K_0402_1%
RV118 56_0402_1% A14 DQU7 A14 DQU7 VGA@ VGA@
M7 A15/BA3 M7 A15/BA3
+1.5VSG +1.5VSG
1

2
CV60 +VREFCA_A1 +VREFDQ_A1
0.01U_0402_16V7K A_BA0 M2 B2 A_BA0 M2 B2
BA0 VDD BA0 VDD

1
VGA@ A_BA1 N8 D9 A_BA1 N8 D9 1 1
2 A_BA2 BA1 VDD A_BA2 BA1 VDD RV123 CV64 RV125 CV65
M3 BA2 VDD G7 M3 BA2 VDD G7
K2 K2 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
VDD VDD VGA@ VGA@ VGA@ VGA@
VDD K8 VDD K8
2 2
N1 N1

2
CLKA0 VDD CLKA0 VDD
14 CLKA0 J7 CK VDD N9 J7 CK VDD N9
CLKA0# K7 R1 CLKA0# K7 R1
14 CLKA0# CK VDD CK VDD
CKEA0 K9 R9 CKEA0 K9 R9
14 CKEA0 CKE/CKE0 VDD CKE/CKE0 VDD
C C

ODTA0 K1 A1 ODTA0 K1 A1
14 ODTA0 ODT/ODT0 VDDQ ODT/ODT0 VDDQ +1.5VSG +1.5VSG
CSA0#_0 L2 A8 CSA0#_0 L2 A8
14 CSA0#_0 CS/CS0 VDDQ CS/CS0 VDDQ
RASA0# J3 C1 RASA0# J3 C1
14 RASA0# RAS VDDQ RAS VDDQ
CASA0# K3 C9 CASA0# K3 C9
14 CASA0# CAS VDDQ CAS VDDQ

1
WEA0# L3 D2 WEA0# L3 D2
14 WEA0# WE VDDQ WE VDDQ
E9 E9 RV126 RV128
VDDQ VDDQ 4.99K_0402_1% 4.99K_0402_1%
VDDQ F1 VDDQ F1
DQSA3 F3 H2 DQSA2 F3 H2 VGA@ VGA@
DQSA0 DQSL VDDQ DQSA1 DQSL VDDQ
C7 H9 C7 H9

2
DQSU VDDQ DQSU VDDQ +VREFCA_A2 +VREFDQ_A2

1
DQMA3 E7 A9 DQMA2 E7 A9 1 1
DQMA0 DML VSS DQMA1 DML VSS RV127 CV66 RV129 CV67
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
VSS VSS VGA@ VGA@ VGA@ VGA@
VSS G8 VSS G8
DQSA#3 DQSA#2 2 2
G3 J2 G3 J2

2
DQSA#0 DQSL VSS DQSA#1 DQSL VSS
B7 DQSU VSS J8 B7 DQSU VSS J8
VSS M1 VSS M1
VSS M9 VSS M9
VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9
14,19,20,21 VRAM_RST# RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
RV138 L1 B9 RV139 L1 B9
240_0402_1% NC/CS1 VSSQ 240_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
VGA@ L9 D8 VGA@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
@ @

+1.5VSG +1.5VSG
+1.5VSG
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
+ CV122 CV72 CV73 CV152 CV153 CV154 CV155 CV156 CV75 CV74 CV157 CV158 CV159 CV160 CV161
390U_2.5V_M_R10 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ 1U_0402_6.3V6K 1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 18 of 51
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits www.qdzbwx.com MDA[0..63] 14,18

MAA[0..13] 14,18

DQMA[0..7] 14,18
UV8 UV7
DQSA[0..7] 14,18
+VREFCA_A3 M8 E3 MDA38 +VREFCA_A4 M8 E3 MDA51
+VREFDQ_A3 H1 VREFCA DQL0 MDA34 +VREFDQ_A4 H1 VREFCA DQL0 MDA52
VREFDQ DQL1 F7 VREFDQ DQL1 F7 DQSA#[0..7] 14,18
F2 MDA39 F2 MDA48
MAA0 DQL2 MDA36 MAA0 DQL2 MDA53
D N3 A0 DQL3 F8 N3 A0 DQL3 F8 A_BA[0..2] 14,18 D
MAA1 P7 H3 MDA35 Group4 MAA1 P7 H3 MDA49 Group6
MAA2 A1 DQL4 MDA33 MAA2 A1 DQL4 MDA54
P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAA3 N2 G2 MDA37 MAA3 N2 G2 MDA50
MAA4 A3 DQL6 MDA32 MAA4 A3 DQL6 MDA55
P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAA5 P2 MAA5 P2
MAA6 A5 MAA6 A5
R8 A6 R8 A6
MAA7 R2 D7 MDA42 MAA7 R2 D7 MDA61
MAA8 A7 DQU0 MDA44 MAA8 A7 DQU0 MDA57
T8 A8 DQU1 C3 T8 A8 DQU1 C3
VGA@ MAA9 R3 C8 MDA40 MAA9 R3 C8 MDA63
CLKA1 MAA10 A9 DQU2 MDA46 MAA10 A9 DQU2 MDA58
1 2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
RV70 56_0402_1% MAA11 R7 A7 MDA43 Group5 MAA11 R7 A7 MDA60 Group7
MAA12 A11 DQU4 MDA45 MAA12 A11 DQU4 MDA56
N7 A12 DQU5 A2 N7 A12 DQU5 A2
VGA@ MAA13 T3 B8 MDA41 MAA13 T3 B8 MDA62
CLKA1# A13 DQU6 MDA47 A13 DQU6 MDA59 +1.5VSG +1.5VSG
1 2 T7 A14 DQU7 A3 T7 A14 DQU7 A3
RV119 56_0402_1% M7 M7
A15/BA3 +1.5VSG A15/BA3 +1.5VSG
1

1
CV61
0.01U_0402_16V7K A_BA0 M2 B2 A_BA0 M2 B2 RV130 RV136
VGA@ A_BA1 BA0 VDD A_BA1 BA0 VDD 4.99K_0402_1% 4.99K_0402_1%
N8 BA1 VDD D9 N8 BA1 VDD D9
2 A_BA2 A_BA2 VGA@ VGA@
M3 BA2 VDD G7 M3 BA2 VDD G7
K2 K2

2
VDD VDD +VREFCA_A3 +VREFDQ_A3
VDD K8 VDD K8
VDD N1 VDD N1

1
CLKA1 J7 N9 CLKA1 J7 N9 1 1
14 CLKA1 CK VDD CK VDD
CLKA1# K7 R1 CLKA1# K7 R1 RV131 CV68 RV137 CV71
14 CLKA1# CK VDD CK VDD
CKEA1 K9 R9 CKEA1 K9 R9 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
14 CKEA1 CKE/CKE0 VDD CKE/CKE0 VDD
C VGA@ VGA@ VGA@ VGA@ C
2 2

2
ODTA1 K1 A1 ODTA1 K1 A1
14 ODTA1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
CSA1#_0 L2 A8 CSA1#_0 L2 A8
14 CSA1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
RASA1# J3 C1 RASA1# J3 C1
14 RASA1# RAS VDDQ RAS VDDQ
CASA1# K3 C9 CASA1# K3 C9
14 CASA1# CAS VDDQ CAS VDDQ
WEA1# L3 D2 WEA1# L3 D2
14 WEA1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 +1.5VSG +1.5VSG
DQSA4 VDDQ DQSA6 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSA5 C7 H9 DQSA7 C7 H9
DQSU VDDQ DQSU VDDQ

1
RV132 RV134
DQMA4 E7 A9 DQMA6 E7 A9 4.99K_0402_1% 4.99K_0402_1%
DQMA5 DML VSS DQMA7 DML VSS VGA@ VGA@
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1

2
VSS VSS +VREFCA_A4 +VREFDQ_A4
VSS G8 VSS G8
DQSA#4 G3 J2 DQSA#6 G3 J2
DQSL VSS DQSL VSS

1
DQSA#5 B7 J8 DQSA#7 B7 J8 1 1
DQSU VSS DQSU VSS RV133 CV69 RV135 CV70
VSS M1 VSS M1
M9 M9 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
VSS VSS VGA@ VGA@ VGA@ VGA@
VSS P1 VSS P1
VRAM_RST# T2 VRAM_RST# T2 2 2
14,18,20,21 VRAM_RST# P9 P9

2
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
1

1
B J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1 B
RV140 L1 B9 RV141 L1 B9
240_0402_1% NC/CS1 VSSQ 240_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
VGA@ L9 D8 VGA@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
@ @

+1.5VSG
+1.5VSG
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
1 1 1 1 1 1 1
1 1 1 1 1 1 1 CV87 CV86 CV167 CV168 CV169 CV170 CV171
CV85 CV84 CV162 CV163 CV164 CV165 CV166 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1U_0402_6.3V6K
1U_0402_6.3V6K 2 2 2 2 2 2 2
2 2 2 2 2 2 2 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 19 of 51
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits www.qdzbwx.com MDB[0..63] 14,21

MAB[0..13] 14,21

DQMB[0..7] 14,21

DQSB[0..7] 14,21
UV9 UV10
DQSB#[0..7] 14,21
+VREFCA_B1 M8 E3 MDB31 +VREFCA_B2 M8 E3 MDB16
+VREFDQ_B1 H1 VREFCA DQL0 MDB26 +VREFDQ_B2 H1 VREFCA DQL0 MDB17
D VREFDQ DQL1 F7 VREFDQ DQL1 F7 B_BA[0..2] 14,21 D
F2 MDB29 F2 MDB19
MAB0 DQL2 MDB24 MAB0 DQL2 MDB18
N3 A0 DQL3 F8 Group3 N3 A0 DQL3 F8
MAB1 P7 H3 MDB28 MAB1 P7 H3 MDB23 Group2
MAB2 A1 DQL4 MDB25 MAB2 A1 DQL4 MDB21
P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB30 MAB3 N2 G2 MDB22
MAB4 A3 DQL6 MDB27 MAB4 A3 DQL6 MDB20
P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5
R8 A6 R8 A6
MAB7 R2 D7 MDB3 MAB7 R2 D7 MDB13
MAB8 A7 DQU0 MDB5 MAB8 A7 DQU0 MDB10
T8 A8 DQU1 C3 T8 A8 DQU1 C3
VGA@ MAB9 R3 C8 MDB2 MAB9 R3 C8 MDB15
CLKB0 MAB10 A9 DQU2 MDB4 MAB10 A9 DQU2 MDB11
1 2 L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
RV75 56_0402_1% MAB11 R7 A7 MDB1 Group0 MAB11 R7 A7 MDB12 Group1
MAB12 A11 DQU4 MDB6 MAB12 A11 DQU4 MDB9
N7 A12 DQU5 A2 N7 A12 DQU5 A2
VGA@ MAB13 T3 B8 MDB0 MAB13 T3 B8 MDB14
CLKB0# A13 DQU6 MDB7 A13 DQU6 MDB8
1 2 T7 A14 DQU7 A3 T7 A14 DQU7 A3
RV120 56_0402_1% M7 M7 +1.5VSG +1.5VSG
A15/BA3 +1.5VSG A15/BA3 +1.5VSG
1
CV62

1
0.01U_0402_16V7K B_BA0 M2 B2 B_BA0 M2 B2
VGA@ B_BA1 BA0 VDD B_BA1 BA0 VDD RV154 RV160
N8 BA1 VDD D9 N8 BA1 VDD D9
2 B_BA2 B_BA2 4.99K_0402_1% 4.99K_0402_1%
M3 BA2 VDD G7 M3 BA2 VDD G7
K2 K2 VGA@ VGA@
VDD VDD
K8 K8

2
VDD VDD +VREFCA_B1 +VREFDQ_B1
VDD N1 VDD N1
CLKB0 J7 N9 CLKB0 J7 N9
14 CLKB0 CK VDD CK VDD

1
C CLKB0# K7 R1 CLKB0# K7 R1 1 1 C
14 CLKB0# CK VDD CK VDD
CKEB0 K9 R9 CKEB0 K9 R9 RV155 CV80 RV161 CV83
14 CKEB0 CKE/CKE0 VDD CKE/CKE0 VDD 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
VGA@ VGA@ VGA@ VGA@
ODTB0 ODTB0 2 2
14 ODTB0 K1 A1 K1 A1

2
CSB0#_0 ODT/ODT0 VDDQ CSB0#_0 ODT/ODT0 VDDQ
14 CSB0#_0 L2 CS/CS0 VDDQ A8 L2 CS/CS0 VDDQ A8
RASB0# J3 C1 RASB0# J3 C1
14 RASB0# RAS VDDQ RAS VDDQ
CASB0# K3 C9 CASB0# K3 C9
14 CASB0# CAS VDDQ CAS VDDQ
WEB0# L3 D2 WEB0# L3 D2
14 WEB0# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
VDDQ F1 VDDQ F1
DQSB3 F3 H2 DQSB2 F3 H2 +1.5VSG +1.5VSG
DQSB0 DQSL VDDQ DQSB1 DQSL VDDQ
C7 DQSU VDDQ H9 C7 DQSU VDDQ H9

1
DQMB3 E7 A9 DQMB2 E7 A9 RV156 RV158
DQMB0 DML VSS DQMB1 DML VSS 4.99K_0402_1% 4.99K_0402_1%
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1 VGA@ VGA@
VSS VSS
G8 G8

2
DQSB#3 VSS DQSB#2 VSS +VREFCA_B2 +VREFDQ_B2
G3 DQSL VSS J2 G3 DQSL VSS J2
DQSB#0 B7 J8 DQSB#1 B7 J8
DQSU VSS DQSU VSS

1
VSS M1 VSS M1 1 1
M9 M9 RV157 CV81 RV159 CV82
VSS VSS 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
VSS P1 VSS P1
VRAM_RST# T2 P9 VRAM_RST# T2 P9 VGA@ VGA@ VGA@ VGA@
14,18,19,21 VRAM_RST# RESET VSS RESET VSS 2 2
T1 T1

2
VSS VSS
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9
B B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV142 L1 B9 RV143 L1 B9
240_0402_1% NC/CS1 VSSQ 240_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
VGA@ L9 D8 VGA@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
@ @
+1.5VSG
+1.5VSG
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
1 1 1 1 1 1 1
1 1 1 1 1 1 1 CV91 CV90 CV177 CV178 CV179 CV180 CV182
CV89 CV88 CV172 CV173 CV174 CV175 CV176 VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ 1U_0402_6.3V6K
1U_0402_6.3V6K 2 2 2 2 2 2 2
2 2 2 2 2 2 2 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 20 of 51
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits

www.qdzbwx.com MDB[0..63] 14,20

MAB[0..13] 14,20

DQMB[0..7] 14,20
UV11 UV12
DQSB[0..7] 14,20
+VREFCA_B3 M8 E3 MDB49 +VREFCA_B4 M8 E3 MDB37
+VREFDQ_B3 H1 VREFCA DQL0 MDB55 +VREFDQ_B4 H1 VREFCA DQL0 MDB35
VREFDQ DQL1 F7 VREFDQ DQL1 F7 DQSB#[0..7] 14,20
D F2 MDB48 F2 MDB36 D
MAB0 DQL2 MDB53 MAB0 DQL2 MDB34
N3 A0 DQL3 F8 N3 A0 DQL3 F8 B_BA[0..2] 14,20
MAB1 P7 H3 MDB51 Group6 MAB1 P7 H3 MDB38 Group4
MAB2 A1 DQL4 MDB52 MAB2 A1 DQL4 MDB32
P3 A2 DQL5 H8 P3 A2 DQL5 H8
MAB3 N2 G2 MDB50 MAB3 N2 G2 MDB39
MAB4 A3 DQL6 MDB54 MAB4 A3 DQL6 MDB33
P8 A4 DQL7 H7 P8 A4 DQL7 H7
MAB5 P2 MAB5 P2
MAB6 A5 MAB6 A5
R8 A6 R8 A6
MAB7 R2 D7 MDB45 MAB7 R2 D7 MDB63
MAB8 A7 DQU0 MDB41 MAB8 A7 DQU0 MDB59
T8 A8 DQU1 C3 T8 A8 DQU1 C3
MAB9 R3 C8 MDB47 MAB9 R3 C8 MDB57
MAB10 A9 DQU2 MDB40 MAB10 A9 DQU2 MDB62
L7 A10/AP DQU3 C2 L7 A10/AP DQU3 C2
MAB11 R7 A7 MDB44 Group5 MAB11 R7 A7 MDB58 Group7
MAB12 A11 DQU4 MDB42 MAB12 A11 DQU4 MDB60
N7 A12 DQU5 A2 N7 A12 DQU5 A2
MAB13 T3 B8 MDB46 MAB13 T3 B8 MDB56
A13 DQU6 MDB43 A13 DQU6 MDB61 +1.5VSG +1.5VSG
T7 A14 DQU7 A3 T7 A14 DQU7 A3
M7 A15/BA3 M7 A15/BA3
+1.5VSG +1.5VSG

1
B_BA0 M2 B2 B_BA0 M2 B2 RV146 RV152
B_BA1 BA0 VDD B_BA1 BA0 VDD 4.99K_0402_1% 4.99K_0402_1%
N8 BA1 VDD D9 N8 BA1 VDD D9
B_BA2 M3 G7 B_BA2 M3 G7 VGA@ VGA@
BA2 VDD BA2 VDD
K2 K2

2
VDD VDD +VREFCA_B3 +VREFDQ_B3
VDD K8 VDD K8
VGA@ N1 N1
VDD VDD

1
CLKB1 1 2 CLKB1 J7 N9 CLKB1 J7 N9 1 1
14 CLKB1 CK VDD CK VDD
RV81 56_0402_1% CLKB1# K7 R1 CLKB1# K7 R1 RV147 CV76 RV153 CV79
14 CLKB1# CK VDD CK VDD
C CKEB1 K9 R9 CKEB1 K9 R9 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K C
14 CKEB1 CKE/CKE0 VDD CKE/CKE0 VDD
VGA@ VGA@ VGA@ VGA@ VGA@
CLKB1# 2 2
1 2

2
RV121 56_0402_1% ODTB1 K1 A1 ODTB1 K1 A1
14 ODTB1 ODT/ODT0 VDDQ ODT/ODT0 VDDQ
1 CSB1#_0 L2 A8 CSB1#_0 L2 A8
14 CSB1#_0 CS/CS0 VDDQ CS/CS0 VDDQ
CV63 RASB1# J3 C1 RASB1# J3 C1
14 RASB1# RAS VDDQ RAS VDDQ
0.01U_0402_16V7K CASB1# K3 C9 CASB1# K3 C9
14 CASB1# CAS VDDQ CAS VDDQ
VGA@ WEB1# L3 D2 WEB1# L3 D2
2 14 WEB1# WE VDDQ WE VDDQ
VDDQ E9 VDDQ E9
F1 F1 +1.5VSG +1.5VSG
DQSB6 VDDQ DQSB4 VDDQ
F3 DQSL VDDQ H2 F3 DQSL VDDQ H2
DQSB5 C7 H9 DQSB7 C7 H9
DQSU VDDQ DQSU VDDQ

1
RV148 RV150
DQMB6 E7 A9 DQMB4 E7 A9 4.99K_0402_1% 4.99K_0402_1%
DQMB5 DML VSS DQMB7 DML VSS VGA@ VGA@
D3 DMU VSS B3 D3 DMU VSS B3
E1 E1

2
VSS VSS +VREFCA_B4 +VREFDQ_B4
VSS G8 VSS G8
DQSB#6 G3 J2 DQSB#4 G3 J2
DQSL VSS DQSL VSS

1
DQSB#5 B7 J8 DQSB#7 B7 J8 1 1
DQSU VSS DQSU VSS RV149 CV77 RV151 CV78
VSS M1 VSS M1
M9 M9 4.99K_0402_1% 0.1U_0402_16V7K 4.99K_0402_1% 0.1U_0402_16V7K
VSS VSS VGA@ VGA@ VGA@ VGA@
VSS P1 VSS P1
VRAM_RST# T2 VRAM_RST# T2 2 2
14,18,19,20 VRAM_RST# P9 P9

2
RESET VSS RESET VSS
VSS T1 VSS T1
L8 ZQ/ZQ0 VSS T9 L8 ZQ/ZQ0 VSS T9

B B
1

1
J1 NC/ODT1 VSSQ B1 J1 NC/ODT1 VSSQ B1
RV144 L1 B9 RV145 L1 B9
240_0402_1% NC/CS1 VSSQ 240_0402_1% NC/CS1 VSSQ
J9 NC/CE1 VSSQ D1 J9 NC/CE1 VSSQ D1
VGA@ L9 D8 VGA@ L9 D8
NCZQ1 VSSQ NCZQ1 VSSQ
E2 E2
2

2
VSSQ VSSQ
VSSQ E8 VSSQ E8
VSSQ F9 VSSQ F9
VSSQ G1 VSSQ G1
VSSQ G9 VSSQ G9

96-BALL 96-BALL
SDRAM DDR3 SDRAM DDR3
H5TQ2G63BFR-11C_FBGA96 H5TQ2G63BFR-11C_FBGA96
@ @

+1.5VSG +1.5VSG

10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K

1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV93 CV92 CV183 CV184 CV185 CV186 CV187 CV95 CV94 CV188 CV189 CV190 CV191 CV192
VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@ VGA@
1U_0402_6.3V6K 1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K 10U_0603_6.3V6M 1U_0402_6.3V6K 1U_0402_6.3V6K
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 21 of 51
5 4 3 2 1
 A B C D E

APU_PCIE_RST#_R
LPC_RST#_R
AE2
U1A

PCIE_RST#
HUDSON-2
HUDM3R3@

PCICLK0 AF3
PCI_CLK1
www.qdzbwx.com PCIE_RST# is for PCIE devices on APU

PCI CLKS
AD5 A_RST# PCICLK1/GPO36 AF1 PCI_CLK1 25
AF5 APU_PCIE_RST#_R R225 1 2 33_0402_5%
PCICLK2/GPO37 APU_PCIE_RST# 12,27,32,33
C202 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P0 AE30 AG2 PCI_CLK3 Strap
5 UMI_MTX_C_FRX_P0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 25

2
C203 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N0 AE32 AF6 PCI_CLK4 1
5 UMI_MTX_C_FRX_N0 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 25
C204 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P1 AD33 C221 R223
5 UMI_MTX_C_FRX_P1 UMI_TX1P
C209 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N1 AD31 AB5 100K_0402_5%
5 UMI_MTX_C_FRX_N1 UMI_TX1N PCIRST#
C210 1 2 0.1U_0402_16V7K UMI_MTX_FRX_P2 AD28 150P_0402_50V8J @
5 UMI_MTX_C_FRX_P2 UMI_TX2P 2
C211 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N2 AD29
5 UMI_MTX_C_FRX_N2

1
C213 0.1U_0402_16V7K UMI_MTX_FRX_P3 UMI_TX2N
5 UMI_MTX_C_FRX_P3 1 2 AC30 UMI_TX3P AD0/GPIO0 AJ3
C212 1 2 0.1U_0402_16V7K UMI_MTX_FRX_N3 AC32 AL5
5 UMI_MTX_C_FRX_N3 UMI_TX3N AD1/GPIO1
1 UMI_FTX_C_MRX_P0 AD2/GPIO2 AG4 A_RST# is for LPC devices 1
5 UMI_FTX_C_MRX_P0 AB33 UMI_RX0P AD3/GPIO3 AL6
UMI_FTX_C_MRX_N0 AB31 AH3 LPC_RST#_R R226 1 2 33_0402_5%

PCI EXPRESS INTERFACES

5 UMI_FTX_C_MRX_N0 UMI_RX0N AD4/GPIO4 LPC_RST# 37,38
UMI_FTX_C_MRX_P1 AB28 AJ5
5 UMI_FTX_C_MRX_P1 UMI_RX1P AD5/GPIO5

2
UMI_FTX_C_MRX_N1 AB29 AL1 1
5 UMI_FTX_C_MRX_N1 UMI_RX1N AD6/GPIO6
UMI_FTX_C_MRX_P2 Y33 AN5 C222 R224
5 UMI_FTX_C_MRX_P2 UMI_RX2P AD7/GPIO7
UMI_FTX_C_MRX_N2 Y31 AN6 100K_0402_5%
5 UMI_FTX_C_MRX_N2 UMI_RX2N AD8/GPIO8
UMI_FTX_C_MRX_P3 Y28 AJ1 150P_0402_50V8J @
5 UMI_FTX_C_MRX_P3 UMI_RX3P AD9/GPIO9 2
UMI_FTX_C_MRX_N3 Y29 AL8
5 UMI_FTX_C_MRX_N3

1
UMI_RX3N AD10/GPIO10
AD11/GPIO11 AL3
R220 1 2 590_0402_1% PCIE_CALRP AF29 AM7
PCIE_CALRP AD12/GPIO12
+PCIE_VDDR_FCH R221 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRN AD13/GPIO13 AJ6
AD14/GPIO14 AK7
V33 GPP_TX0P AD15/GPIO15 AN8
RENE@ V31 AG9
C214 0.1U_0402_16V7K PCIE_MTX_USBRX_P1 GPP_TX0N AD16/GPIO16
35 PCIE_MTX_C_USBRX_P1
1 2 W30 GPP_TX1P AD17/GPIO17 AM11 3D_EN# (Internal 15K PU)
USB3.0 C215 1RENE@
2 0.1U_0402_16V7K PCIE_MTX_USBRX_N1 W32 AJ10
35 PCIE_MTX_C_USBRX_N1 C216 0.1U_0402_16V7K PCIE_MTX_CRRX_P2 GPP_TX1N AD18/GPIO18
1 2 AB26 GPP_TX2P AD19/GPIO19 AL12
34 PCIE_MTX_C_CRRX_P2 C219 0.1U_0402_16V7K PCIE_MTX_CRRX_N2
Cardreader 34 PCIE_MTX_C_CRRX_N2
1 2 AB27 GPP_TX2N AD20/GPIO20 AK11 3D_EN# H L
AA24 GPP_TX3P AD21/GPIO21 AN12
AA23 GPP_TX3N AD22/GPIO22 AG12
AE12 PCI_AD23
AD23/GPIO23 PCI_AD23 25
AA27 AC12 PCI_AD24 Strap SKU Non-3D 3D(LVDS/eDP)
GPP_RX0P AD24/GPIO24 PCI_AD24 25
AA26 AE13 PCI_AD25
GPP_RX0N AD25/GPIO25 PCI_AD25 25
PCIE_MRX_C_USBTX_P1 W27 PCI_AD26 For PowerXpress

PCI INTERFACE
35 PCIE_MRX_C_USBTX_P1 GPP_RX1P AD26/GPIO26 AF13 PCI_AD26 25
PCIE_MRX_C_USBTX_N1 V27 AH13 PCI_AD27
35 PCIE_MRX_C_USBTX_N1 GPP_RX1N AD27/GPIO27 PCI_AD27 25
PCIE_MRX_C_CRTX_P2 V26 AH14 VGA_PWRGD_R 1 2 VGA_PWRGD 17,40,48
34 PCIE_MRX_C_CRTX_P2 GPP_RX2P AD28/GPIO28
PCIE_MRX_C_CRTX_N2 W26 AD15 R254 PXS@ 0_0402_5% PXS_EN# (Internal 15K PU)
34 PCIE_MRX_C_CRTX_N2 GPP_RX2N AD29/GPIO29
W24 GPP_RX3P AD30/GPIO30 AC15
W23 AE16 FELICA_PWR
GPP_RX3N AD31/GPIO31
CBE0# AN3 PXS_EN# H L
AJ8 CROSSEN@
CBE1# CROSS_EN#
CBE2# AN10 2 1
2 2
+1.1VS_CKVDD R228 1 2 2K_0402_1% CLK_CALRN F27 CLK_CALRN CBE3# AD12 R135 1K_0402_5% Non-
R126 3D_EN# 2 3D@ SKU
FRAME# AG10
AK9 1K_0402_5% R126
1
1K_0402_5% PowerXpress PowerXpress
DEVSEL# EDP@ PXS_EN#
Input from external clock generator IRDY# AL10 2 PXSEN@1
G30 AF10 R85 1K_0402_5%
NC for internal clock generator PCIE_RCLKP TRDY#
SS G28 PCIE_RCLKN PAR AE10
AH1 CROSS_EN# (Internal 8.2K PU)
APU_DISP_CLKP STOP# FELICA_PWR
7 APU_DISP_CLKP R26 DISP_CLKP PERR# AM9 2 1
APU Display APU_DISP_CLKN T26 AH8 R72 100K_0402_5%
7 APU_DISP_CLKN DISP_CLKN SERR#
REQ0# AG15 CROSS_EN# H L
TRAVIS_CLK
NSS LVDS IC
27 TRAVIS_CLK
TRAVIS_CLK#
H33
H31
DISP2_CLKP REQ1#/GPIO40 AG13
AF15 3D_EN#
27 TRAVIS_CLK# DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41
AM17 PXS_EN# For PowerXpress Non-
APU_CLKP REQ3#/CLK_REQ5#/GPIO42
7 APU_CLKP T24 APU_CLKP GNT0# AD16 SKU CrossFire CrossFire
APU APU_CLKN T23 AD13 PXS_RST#_R R252 1 PXS@ 2 0_0402_5%
7 APU_CLKN APU_CLKN GNT1#/GPO44 PXS_RST# 12
AD21 PXS_PWREN_R R253 1 PXS@ 2 0_0402_5%
GNT2#/SD_LED/GPO45 PXS_PWREN 17,40
CLK_PEG_VGA J30 AK17
12 CLK_PEG_VGA SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 CLKREQ_USB30# 35
VGA CLK_PEG_VGA# K29 AD19
12 CLK_PEG_VGA# SLT_GFX_CLKN CLKRUN#
LOCK# AH9 1 2 +3VS 2 PXS@ 1
CLK_CR H27 R283 8.2K_0402_5% R257 10K_0402_5%
34 CLK_CR GPP_CLK0P
Cardreader CLK_CR# H28 AF18
34 CLK_CR# GPP_CLK0N INTE#/GPIO32 +1.5VS +3VS
INTF#/GPIO33 AE18
J27 GPP_CLK1P INTG#/GPIO34 AC16
K26 AD18 CROSS_EN#
GPP_CLK1N INTH#/GPIO35

2
CLK_WLAN F33 R269 R270
CLOCK GENERATOR

32 CLK_WLAN GPP_CLK2P
WLAN CLK_WLAN# F31
32 CLK_WLAN# GPP_CLK2N LPC_CLK0 R255 1 2 22_0402_5% 10K_0402_5% 4.7K_0402_5%
SS CLK_LAN E33
LPCCLK0 B25 CLK_PCI_EC 25,37
Strap
33 CLK_LAN

2 2

1
CLK_LAN# GPP_CLK3P LPC_CLK1 R258 1
LAN 33 CLK_LAN# E31 GPP_CLK3N LPCCLK1 D25 2 22_0402_5% CLK_PCI_DDR 25,38

B
D27 LPC_AD0
LAD0 LPC_AD0 37,38
CLK_JET M23 C28 LPC_AD1 Q46
32 CLK_JET GPP_CLK4P LAD1 LPC_AD1 37,38

E
3 CLK_JET# LPC_AD2 APU_PWRGD 3
JET 32 CLK_JET# M24 GPP_CLK4N LAD2 A26 LPC_AD2 37,38 3 1 APU_PWRGD_L 49

C
LPC_AD3
LPC

LAD3 A29 LPC_AD3 37,38

M27 A31 LPC_FRAME# MMBT3904_NL_SOT23-3
GPP_CLK5P LFRAME# LPC_FRAME# 37,38
M26 GPP_CLK5N LDRQ0# B27
LDRQ1#/CLK_REQ6#/GPIO49 AE27
N25 AE19 SERIRQ SERIRQ 37,38
GPP_CLK6P SERIRQ/GPIO48
N26 GPP_CLK6N +RTCBATT
DMA active. The FCH drives the DMA_ACTIVE# to
CLK_USB30 R23
35 CLK_USB30
CLK_USB30# GPP_CLK7P DMA_ACTIVE# APU to notify DMA activity. This will cause the APU
USB3.0 35 CLK_USB30# R24 GPP_CLK7N DMA_ACTIVE# G25 DMA_ACTIVE# 7 2
PROCHOT# E28 APU_PROCHOT#_R 1 2 APU_PROCHOT# 7 to reestablish the UMI link quicker. C231
N27 E26 APU_PWRGD R259 0_0402_5% 22P_0402_50V8J
GPP_CLK8P APU_PG APU_PWRGD 7
@
APU

R27 GPP_CLK8N LDT_STP# G26

APU_RST# 1
APU_RST# F26 APU_RST# 7
S5_CORE_EN is for S5+ mode
J26 14M_25M_48M_OSC
H7
used to turn off +1.1VALW and Reserver for ESD test
S5_CORE_EN T25
RTCCLK F1 RTC_CLK_R 1 2 RTC_CLK 25,37 Strap +3VALW of FCH on S5+ mode
F3 R260 0_0402_5% +RTCBATT
C220 1 INTRUDER_ALERT#
2 27P_0402_50V8J 25M_X1 C31 25M_X1 VDDBT_RTC_G E6 +RTCVCC_R

1
S5 PLUS
1

G2 32K_X1
Y1 R229 32K_X1 D13
1M_0402_5% 25M_X2 C33 +RTCVCC BAS40-04_SOT23-3
25MHZ_20PF_7A25000012 25M_X2
2

G4 32K_X2 20 mils R271 R355 R268

2
32K_X2
1 2 1 2 1 2+RTCBATT_R 1 2+RTCBATT_D +3VL
C230 27P_0402_50V8J 120_0402_5% 120_0402_5% 1K_0402_5%
1 1

1
HUDSON-M3_FCBGA656 C250 C252 JCMOS 1
@ C256
0.1U_0402_16V4Z 1U_0402_6.3V6K

2
4 2 2 0.1U_0402_16V4Z 4
C248 1 32K_X1 2
2 18P_0402_50V8J

Y2 CMOS Setting
1

4 3
R230 OSC NC Place under DDR
20M_0402_5% 1 OSC NC 2 Door
32.768KHZ_12.5PF_Q13MC14610002 Security Classification Compal Secret Data Compal Electronics, Inc.
2

1 2 32K_X2 2011/01/06 2012/01/06 Title

C249 18P_0402_50V8J Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 22 of 51
A B C D E
 A B C D E

R227 2

C19 1
@ 1 100K_0402_5%

2 150P_0402_50V8J R222
33_0402_5%
PCIE_RST2# is for PCIE devices on FCH

FCH_PCIE_RST#_R
U1D

HUDSON-2
HUDM3R3@ www.qdzbwx.com

USB MISC
34,35 FCH_PCIE_RST# 1 2 AB6 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC G8
EC_LID_OUT# R2
37 EC_LID_OUT# RI#/GEVENT22#
T68 W7 B9 USB_RCOMP R329 1 2 11.8K_0402_1%
SLP_S3# SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
37 SLP_S3# T3 SLP_S3#
SLP_S5# W2 H1
37 SLP_S5# SLP_S5# USB_FSD1P/GPIO186
PBTN_OUT# J4 H3
37 PBTN_OUT# PWR_BTN# USB_FSD1N
FCH_PWRGD N7 Hudson-M2/M3
37 FCH_PWRGD PWR_GOOD

USB 1.1
H6

ACPI / WAKE UP EVENTS

TEST0 T9
USB_FSD0P/GPIO185
H5
OHCI (DEV-20, FUN-5)
TEST1 TEST0 USB_FSD0N
T10 TEST1/TMS
TEST2 V9 H10
1 +3VS TEST2 USB_HSD13P 1
USB_HSD13N G10
GATEA20 AE22 Hudson-M2
37 GATEA20 GA20IN/GEVENT0#
1 @ 2 PEG_CLKREQ# K10
R301 8.2K_0402_5% KB_RST#
AG19
USB_HSD12P
J12
OHCI (DEV-22, FUN-0)
37 KB_RST# KBRST#/GEVENT1# USB_HSD12N
2 VGA@ 1 37 EC_SCI#
EC_SCI#
R9 LPC_PME#/GEVENT3#
EHCI (DEV-22, FUN-2)
R295 1K_0402_5% EC_SMI#
C26 G12
37 EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P
T5 T69 F12 Hudson-M3
LPC_PD#/GEVENT5# USB_HSD11N
FCH_PCIE_WAKE#
U4 SYS_RESET#/GEVENT19# USB20_P10
USB 3.0 XHCI (DEV-16, FUN-0)
33,35 FCH_PCIE_WAKE# K1 WAKE#/GEVENT8# USB_HSD10P K12 USB20_P10 32
T67 V7 K13 USB20_N10
USB20_N10 32
(For Hudson M3 only) XHCI (DEV-16, FUN-1)
H_THERMTRIP# IR_RX1/GEVENT20# USB_HSD10N
7 H_THERMTRIP# R10 THRMTRIP#/SMBALERT#/GEVENT2#
+3VS 1 2 WD_PWRGD AF19 B11
R279 10K_0402_5% WD_PWRGD USB_HSD9P
EC_RSMRST# USB_HSD9N D11 Remove Felica
37 EC_RSMRST# U2 RSMRST#
E10 USB20_P8
USB_HSD8P USB20_P8 32
@ CLKREQ_JET# AG24 F10 USB20_N8 WLAN (BT)
32 CLKREQ_JET# CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N USB20_N8 32
1 2 CLKREQ_LAN#_R AE24 Hudson-M2/M3
33 CLKREQ_LAN# CLK_REQ3#/SATA_IS1#/GPIO63
D17 RB751V40_SC76-2 AE26 C10
CLKREQ_CR# SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P OHCI (DEV-19, FUN-0)
1 2 AF22 A10 Remove Finger Printer

USB 2.0
CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
R361 0_0402_5% AH17 SATA_IS4#/FANOUT3/GPIO55
EHCI (DEV-19, FUN-2)
AG18 SATA_IS5#/FANIN3/GPIO59 USB_HSD6P H9
FCH_SPKR AF24 G9 Remove 3G/TV #1
36 FCH_SPKR SPKR/GPIO66 USB_HSD6N
FCH_SCLK0

GPIO
SM Bus 0-->S0 PWR domain 10,11,32 FCH_SCLK0 AD26 SCL0/GPIO43
FCH_SDATA0 AD25 A8 USB20_P5
SM Bus 1-->S5 PWR domain 10,11,32 FCH_SDATA0
FCH_SCLK1 SDA0/GPIO47 USB_HSD5P USB20_N5
USB20_P5 28
T7 SCL1/GPIO227 USB_HSD5N C8 USB20_N5 28 Int. Camera
(for ASF device only) FCH_SDATA1 R7 SDA1/GPIO228
CLKREQ_WLAN# AG25 F8
32 CLKREQ_WLAN# CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P
AG22 CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N E8
T30 J2 IR_LED#/LLB#/GPIO184
AG26 SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P C6
VGA_PD: Support CRT power saving 25 R292 1 @ 2 0_0402_5% VGA_PD_FCH V8 A6 Remove TV #2 Hudson-M2/M3
VGA_PD DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N
W8
L: MLDAC power on T65 Y6
GBE_LED0/GPIO183
C5 USB20_P2 OHCI (DEV-18, FUN-0)
2 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P USB20_P2 31 2
H: MLDAC power off HDMI_HPD_FCH_R V10 GBE_LED2/GEVENT10# USB_HSD2N A5 USB20_N2
USB20_N2 31 USB-Left EHCI (DEV-18, FUN-2)
AA8 GBE_STAT0/GEVENT11#
PEG_CLKREQ# AF25 C1 USB20_P1 <Support Wakeup>
13 PEG_CLKREQ# CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P USB20_P1 31
C3 USB20_N1 USB-Right2
USB_HSD1N USB20_N1 31
USB30_SMI# M7 E1 USB20_P0
35 USB30_SMI# BLINK/USB_OC7#/GEVENT18# USB_HSD0P USB20_P0 31
R8 E3 USB20_N0 USB-Right1
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N USB20_N0 31

USB OC
Internal PU 10K 31 ODD_PLUGIN# T1 USB_OC5#/IR_TX0/GEVENT17#
ODD_DA#_FCH P6 C16 USBSS_CALRP R330 1 M3@ 2 1K_0402_1%
USB_OC3# USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP USBSS_CALRN R334 1
37 USB_OC3# F5 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN A16 2 1K_0402_1%
CR_CPPE# P5 M3@ +VDDANCR_11_SSUSB
34 CR_CPPE# USB_OC2#/TCK/GEVENT14#
USB_OC1# is for USB port2 USB_OC1# J7 A14
32,35,37 USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# T8 C14
31,37 USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
USB_OC0# is for USB port0 and port1
USB_SS_RX3P C12
USB_SS_RX3N A12

R320 1 2 33_0402_5% HDA_BITCLK AB3 D15

36 AZ_BITCLK_HD AZ_BITCLK USB_SS_TX2P
R321 1 2 33_0402_5% HDA_SDOUT AB1 B15
36 AZ_SDOUT_HD AZ_SDOUT USB_SS_TX2N
AZ_SDIN0_HD

HD AUDIO
36 AZ_SDIN0_HD AA2 AZ_SDIN0/GPIO167
Y5 E14 Hudson-M3

USB 3.0
AZ_SDIN1/GPIO168 USB_SS_RX2P
Y3 F14
Y1
AZ_SDIN2/GPIO169 USB_SS_RX2N XHCI (DEV-16, FUN-0)
AZ_SDIN3/GPIO170
36 AZ_SYNC_HD
R322 1 2 33_0402_5% HDA_SYNC AD6 AZ_SYNC USB_SS_TX1P F15 XHCI (DEV-16, FUN-1)
R323 1 2 33_0402_5% HDA_RST# AE4 G15
36 AZ_RST_HD# AZ_RST# USB_SS_TX1N

USB_SS_RX1P H13
+3VALW G13
USB_SS_RX1N
1 2 CR_CPPE# T26 K19 J16 USB30_TX0P
PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB30_TX0P 35
R421 10K_0402_5% CIR@ T27 J19 H16 USB30_TX0N USB 3.0
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N USB30_TX0N 35
1 @ 2 VGA_PD_FCH 2 1 CIR_EN# J21
R293 10K_0402_5% R442 1K_0402_5% SPI_CS2#/GBE_STAT2/GPIO166 USB30_RX0P (For Hudson M3 only)
USB_SS_RX0P J15 USB30_RX0P 35
3 1 2 H_THERMTRIP# K15 USB30_RX0N 3
USB_SS_RX0N USB30_RX0N 35
R278 10K_0402_5%
1 2 FCH_SCLK1 ACIN_FCH# D21
R288 10K_0402_5% PS2KB_DAT/GPIO189 R326 1
C20 PS2KB_CLK/GPIO190 SCL2/GPIO193 H19 2 10K_0402_5% +3VALW
1 2 FCH_SDATA1 D23 G19 R328 1 2 10K_0402_5%
R289 10K_0402_5% PS2M_DAT/GPIO191 EMBEDDED CTRL SDA2/GPIO194 FCH_SIC
@ EC_LID_OUT#
Change to low active for AC_IN LED issue C22 PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G22
FCH_SID
1
R338 1
2 APU_SIC 7,9
1 2 SDA3_LV/GPIO196 G21 2 0_0402_5% APU_SID 7,9 SB-TSI
R272 10K_0402_5% E22 R343 0_0402_5%
EC_PWM0/EC_TIMER0/GPIO197
1

FCH_PCIE_WAKE# Q191 D
1 2 EC_PWM1/EC_TIMER1/GPIO198 H22
R276 10K_0402_5% 2 T33 F21 J22 EC_PWM2 Strap
13,37,39,43 ACIN KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM2 25
1 RENE@ 2 USB30_SMI# G T32 E20 H21
R306 10K_0402_5% 2N7002_SOT23-3 T35 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
S F20
3

USB_OC0# T34 KSO_2/GPIO211

1 2 A22 KSO_3/GPIO212 KSI_0/GPIO201 K21
R318 10K_0402_5% T37 E18 K22 +3VALW +3VS
USB_OC1# T36 KSO_4/GPIO213 KSI_1/GPIO202
1 2 A20 KSO_5/GPIO214 KSI_2/GPIO203 F22
R319 10K_0402_5% T38 J18 F24 +3VS
KSO_6/GPIO215 KSI_3/GPIO204

2
1 @ 2 ACIN_FCH# T39 H18 E24
R436 330K_0402_5% T45 KSO_7/GPIO216 KSI_4/GPIO205 R312 R311
G18 KSO_8/GPIO217 KSI_5/GPIO206 B23 Place R425 and C363
T44 B21 C24 10K_0402_5% 10K_0402_5%
@ USB_OC3# T46 KSO_9/GPIO218 KSI_6/GPIO207 close to FCH for ESD @
1 2 K18 KSO_10/GPIO219 KSI_7/GPIO208 F18

2
R332 10K_0402_5% T47 Q208

G
D19

1
T41 KSO_11/GPIO220
A18 KSO_12/GPIO221
T40 C18 ODD_DA#_FCH 1 2 ODD_DA#_Q 1 3
KSO_13/GPIO222 ODD_DA# 31
T42 B19 R425 0_0402_5%

S
KSO_14/GPIO223 1
+3VS T43 B17 C379
T49 KSO_15/GPIO224 0.1U_0402_16V4Z 2N7002_SOT23-3
A24 KSO_16/GPIO225
1 2 FCH_SCLK0 T48 D17
R286 2.2K_0402_5% KSO_17/GPIO226 2
1 2 FCH_SDATA0
R287 2.2K_0402_5% HUDSON-M3_FCBGA656
1 @ 2 CLKREQ_WLAN# +3VALW
R291 8.2K_0402_5% Set cardreader clock
2

1 @ 2 CLKREQ_JET# +3VS
4 R290 8.2K_0402_5% as free-running R331 4
1 @ 2 CLKREQ_CR# 2 1 CEC@ 10K_0402_5%
2
G

R281 8.2K_0402_5% R282 1K_0402_5% Q192 @

1 @ 2 CLKREQ_LAN#_R
1

R284 8.2K_0402_5% For FCH internal debug use 9,30 HDMI_HPD 3 1 1 CEC@ 2HDMI_HPD_FCH_R
+3VALW R419 0_0402_5%
S

(Internal 10K pull-down) 2N7002_SOT23-3

2 1 EC_RSMRST#
R280 100K_0402_5% 1 @ 2 TEST0
1 @ 2 HDA_BITCLK R273 2.2K_0402_5% Security Classification Compal Secret Data Compal Electronics, Inc.
R324 10K_0402_5% 1 @ 2 TEST1 2011/01/06 2012/01/06 Title
@ AZ_SDIN0_HD R274 2.2K_0402_5%
Issued Date Deciphered Date
1
R325
2
10K_0402_5% 1 @ 2 TEST2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
R275 2.2K_0402_5% Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 23 of 51
A B C D E
 A B C D E

1st HDD
31 SATA_FTX_DRX_P0
31 SATA_FTX_DRX_N0
SATA_FTX_DRX_P0
SATA_FTX_DRX_N0
AK19
AM19
U1B

SATA_TX0P
SATA_TX0N
HUDSON-2
HUDM3R3@

SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
AL14
AN14
AJ12
HDMI_EN# 2
R443
HDMI@
1
1K_0402_1%
www.qdzbwx.com HDMI_EN# (Internal 8.2K PU)

HDMI_EN# H L
SATA_FRX_C_DTX_N0 SD_CD/GPIO75
31 SATA_FRX_C_DTX_N0 AL20 SATA_RX0N SD_WP/GPIO76 AH12

SD CARD
SATA_FRX_C_DTX_P0 AN20 AK13 Non-HDMI
31 SATA_FRX_C_DTX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78 AM13 SKU SKU HDMI SKU
SATA_FTX_DRX_P1 AN22 AH15
31 SATA_FTX_DRX_P1 SATA_TX1P SD_DATA2/GPIO79
SATA_FTX_DRX_N1 AL22 AJ14
31 SATA_FTX_DRX_N1 SATA_TX1N SD_DATA3/GPIO80
ODD SATA_FRX_C_DTX_N1 GBE_COL R346 1
31 SATA_FRX_C_DTX_N1 AH20 SATA_RX1N GBE_COL AC4 2 10K_0402_5%
SATA_FRX_C_DTX_P1 AJ20 AD3 GBE_CRS R347 1 2 10K_0402_5%
31 SATA_FRX_C_DTX_P1 SATA_RX1P GBE_CRS
GBE_MDCK AD9
SATA_FTX_DRX_P2 AJ22 W10 GBE_MDIO 1 2 +3VALW
31 SATA_FTX_DRX_P2 SATA_TX2P GBE_MDIO
1 SATA_FTX_DRX_N2 AH22 AB8 R345 10K_0402_5% 1
31 SATA_FTX_DRX_N2 SATA_TX2N GBE_RXCLK
2nd HDD SATA_FRX_C_DTX_N2 GBE_RXD3 AH7
31 SATA_FRX_C_DTX_N2 AM23 SATA_RX2N GBE_RXD2 AF7
SATA_FRX_C_DTX_P2 AK23 AE7
31 SATA_FRX_C_DTX_P2 SATA_RX2P GBE_RXD1
GBE_RXD0 AD7
AH24 SATA_TX3P GBE_RXCTL/RXDV AG8
AJ24 AD1 GBE_RXERR 1 2
SATA_TX3N GBE_RXERR R348 10K_0402_5%
AB7

GBE LAN
GBE_TXCLK
AN24 SATA_RX3N GBE_TXD3 AF9
AL24 SATA_RX3P GBE_TXD2 AG6
+1.5V AE8
+3VALW GBE_TXD1
AL26 SATA_TX4P GBE_TXD0 AD8
AN26 SATA_TX4N GBE_TXCTL/TXEN AB9
1

AC2

SERIAL ATA
GBE_PHY_PD

1
R285 AJ26 AA7
10K_0402_5% R437 SATA_RX4N GBE_PHY_RST# GBE_PHY_INTR 1
AH26 SATA_RX4P GBE_PHY_INTR W9 2
@ 10K_0402_5% R352 10K_0402_5% +3VS
AN29
2 2

SATA_TX5P FCH_SPI_MISO
2 AL28 SATA_TX5N SPI_DI/GPIO164 V6
B

@ V5 FCH_SPI_MOSI UMA_CRT_DATA 1 UMA@ 2

SPI_DO/GPIO163

SPI ROM
Q33 AK27 V3 FCH_SPI_CLK R454 2.2K_0402_5%
SATA_RX5N SPI_CLK/GPIO162
E

3 1 FCH_ALERT# AM27 T6 FCH_SPI_CS1# UMA_CRT_CLK 1 UMA@ 2

7 APU_ALERT# SATA_RX5P SPI_CS1#/GPIO165
C

V1 R459 2.2K_0402_5%
MMBT3904_NL_SOT23-3 ROM_RST#/SPI_WP#/GPIO161
AL29 NC6
AN31 NC7
L30 UMA_CRT_R
VGA_RED UMA_CRT_R 29
AL31 NC8
AL33 NC9
L32 UMA_CRT_G
VGA_GREEN UMA_CRT_G 29
AH33 NC10
AH31 UMA_CRT_R R367 1 UMA@ 2 150_0402_1%
NC11 UMA_CRT_B
VGA_BLUE M29 UMA_CRT_B 29
AJ33 UMA_CRT_G R368 1 UMA@ 2 150_0402_1%

VGA DAC
NC12
AJ31 NC13
M28 UMA_CRT_HSYNC UMA_CRT_B R369 1 UMA@ 2 150_0402_1%
VGA_HSYNC/GPO68 UMA_CRT_HSYNC 29
To avoid LED flashing N30 UMA_CRT_VSYNC
VGA_VSYNC/GPO69 UMA_CRT_VSYNC 29

2 M33 UMA_CRT_DATA 2
+5VS VGA_DDC_SDA/GPO70 UMA_CRT_DATA 29
2 1 SATA_CALRP AF28 N32 UMA_CRT_CLK
SATA_CALRP VGA_DDC_SCL/GPO71 UMA_CRT_CLK 29
R336 1K_0402_1%
1 2 SATA_LED# +AVDD_SATA 2 1 SATA_CALRN AF27
R444 10K_0402_5% R337 1K_0402_1% SATA_CALRN VGA_DAC_RSET 1
VGA_DAC_RSET K31 2
2 1 R366 715_0402_1%
R446 20K_0402_5% SATA_LED# AD22
39 SATA_LED# SATA_ACT#/GPIO67
V28 ML_VGA_AUXP
AUX_VGA_CH_P ML_VGA_AUXP 7
V29 ML_VGA_AUXN
AUX_VGA_CH_N ML_VGA_AUXN 7
AF21

VGA MAINLINK
SATA_X1 AUXCAL
AUXCAL U28 1 2 +FCH_VDDAN_11_MLDAC
R364 100_0402_1%
+3VALW T31 ML_VGA_TXP0
ML_VGA_L0P ML_VGA_TXP0 7
T33 ML_VGA_TXN0
ML_VGA_L0N ML_VGA_TXN0 7
1 2 CR_WAKE#_R AG21 T29 ML_VGA_TXP1
SATA_X2 ML_VGA_L1P ML_VGA_TXP1 7 +FCH_VDDAN_33_DAC_R
R434 10K_0402_5% T28 ML_VGA_TXN1
ML_VGA_L1N ML_VGA_TXN1 7
R32 ML_VGA_TXP2
ML_VGA_L2P ML_VGA_TXP2 7
R30 ML_VGA_TXN2 FCH_CRT_HPD 1 UMA@ 2
ML_VGA_L2N ML_VGA_TXN2 7
P29 ML_VGA_TXP3 R365 10K_0402_5%
ML_VGA_L3P ML_VGA_TXP3 7
P28 ML_VGA_TXN3
+3VS ML_VGA_L3N ML_VGA_TXN3 7

1 @ 2 WL_OFF# C29 FCH_CRT_HPD

ML_VGA_HPD/GPIO229 FCH_CRT_HPD 9
R339 8.2K_0402_5%
1 @ 2 3G_OFF# +3VALW
R340 8.2K_0402_5% T66 AH16 N2 1 2
@ BT_ON# ODD_PWR FANOUT0/GPIO52 VIN0/GPIO175 R101 10K_0402_5% SLP_CHG_M3
1 2 40 ODD_PWR AM15 FANOUT1/GPIO53 1 2
R344 8.2K_0402_5% BT_ON# AJ16 HW MONITOR M3 LOGO_LED R418 10K_0402_5%
32 BT_ON# FANOUT2/GPIO54 VIN1/GPIO176 LOGO_LED 39
1 2 PW_CLEAR# SLP_CHG# 1 2
R363 8.2K_0402_5% PW_CLEAR# AK15 L2 WL_BT_LED R420 10K_0402_5%
WL_OFF# FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
32 WL_OFF# AN16 FANIN1/GPIO57
1 2 ODD_PWR 3G_OFF# AL16 N4 1 2
32 3G_OFF# FANIN2/GPIO58 VIN3/SDATO_1/GPIO178
R447 100K_0402_5% R106 10K_0402_5%
P1 SLP_CHG_M3
VIN4/SLOAD_1/GPIO179 SLP_CHG_M3 32
1 2 K6 TEMPIN0/GPIO171
R111 10K_0402_5% P3 SLP_CHG# LOGO_LED 1 2
VIN5/SCLK_1/GPIO180 SLP_CHG# 32
D18 R449 10K_0402_5%
3 2 1 CR_WAKE#_R K5 M1 1 2 3
34 CR_WAKE# TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181
PW_CLEAR# R115 10K_0402_5%
RB751V40_SC76-2 M5 1 2
VIN7/GBE_LED3/GPIO182 R114 10K_0402_5%
1 2 K3 TEMPIN2/GPIO173
1

JPW Place JPW R103 10K_0402_5%

@ AG16
under DDR Door FCH_ALERT# M6
NC1
AH10
2

TEMPIN3/TALERT#/GPIO174 NC2
NC3 A28
NC4 G27
NC5 L4
39 WL_BT_LED#

2N7002DW-T/R7_SOT363-6
HUDSON-M3_FCBGA656

6
Q32A

U51 @ WL_BT_LED 2
1 1OE#

1
4 FCH_SPI_MOSI R572 1 2 0_0402_5% DI

1
2OE# FCH_SPI_CLK R573 0_0402_5% CLK
10 3OE# 1 2
13 FCH_SPI_CS1# R574 1 2 0_0402_5% CS# R450
4OE# FCH_SPI_MISO R575 0_0402_5% DO 10K_0402_5%
1 2
FCH_SPI_MOSI 2 3 DI

2
FCH_SPI_CLK 1A 1B CLK
5 2A 2B 6 For MP phase Q32B in page39
FCH_SPI_CS1# 9 8 CS#
FCH_SPI_MISO 3A 3B DO
12 4A 4B 11

+3VS 14 VCC GND 7

1
C484 @ SN74CBTLV3125PWR_TSSOP14
0.1U_0402_16V4Z +3VALW
C498
2
2 1
2M Byte
0.1U_0402_16V4Z
U53 @ U13
4 EC_ON 1 8 4 4
37,39 EC_ON 1OE# VCC VSS
4 2OE#
10 3OE# 3 W
13 4OE#
7 HOLD
2 3 DI
37,38,39 KSI6 1A 1B
5 6 CLK @ @ CS# 1
37,38 KSI5 2A 2B S
9 8 CS# C257 R402
37,38 KSI3 3A 3B
12 11 DO 1 2 1 2 CLK 6
37,38 KSI7 4A 4B C
10_0402_5%
14 7 10P_0402_50V8J DI 5 2 DO
+3VALW
1
VCC GND D Q Security Classification Compal Secret Data Compal Electronics, Inc.
C485 @ SN74CBTLV3125PWR_TSSOP14 For EMI MX25L1606EM2I-12G SOP 8P 2011/01/06 2012/01/06 Title
Issued Date Deciphered Date
0.1U_0402_16V4Z SCHEMATIC, MB A7213
2 Socket: SP07000F500/SP07000H900 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 24 of 51
A B C D E
 A B C D E

www.qdzbwx.com
STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

1 1
PULL ALLOW ENABLE NON_FUSION EC CLKGEN LPC ROM S5 PLUS
HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED (INTERNAL MODE
STRAP 10K PULL-UP) DISABLED
DEFAULT DEFAULT DEFAULT

PULL FORCE DISABLE FUSION EC CLKGEN SPI ROM S5 PLUS

LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE
STRAP MODE ENABLED
DEFAULT DEFAULT DEFAULT DEFAULT
+3VS

CRT Power Down Circuit L32

1 2
MBK1608221YZF_2P
+3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW UMA@
2
C496
0.1U_0402_16V7K
@
1

1
1

3
S
R231 R241 R242 R243 R238 R245 R240 Q62
G @
@ @ @ @ VGA_PD_R 2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% +FCH_VDDAN_33_DAC +FCH_VDDAN_33_DAC_R
2 AO3413_SOT23 D
2

1
@ 30mils L31 @
C497 1 2
PCI_CLK1 0.01U_0402_25V7K MBK1608221YZF_2P
22 PCI_CLK1 1

2.2U_0603_6.3V6K

0.1U_0402_16V7K
1
PCI_CLK3 1
2 22 PCI_CLK3 2
C689 C690 1 1
PCI_CLK4 4.7U_0805_10V4Z 1U_0402_6.3V6K C277 C276 C276
22 PCI_CLK4 2 @
@ 0_0402_5%
CLK_PCI_EC 2 UMA@ UMA@ DIS@
22,37 CLK_PCI_EC 2 2
CLK_PCI_DDR
22,38 CLK_PCI_DDR
EC_PWM2
23 EC_PWM2
RTC_CLK VGA_PD: Support CRT power saving
22,37 RTC_CLK +1.1VS
L: MLDAC power on
H: MLDAC power off
1

1
R232 R233 R234 R237 R244 R239 R246
@ @ @ 2
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 2.2K_0402_5% 2.2K_0402_5% C494 AO3413 Vgs(max)= -1V
0.1U_0402_16V7K
2

2
@

2
1

3
S
Q61
G @ R303
1 @ 2 VGA_PD_R 2 0_0603_5%
23 VGA_PD
R439 47K_0402_5% UMA@

1
AO3413_SOT23 D +FCH_VDDAN_11_MLDAC
2

1
R294 @ 30mils
2.2K_0402_5% C495
DEBUG STRAPS @
1
0.01U_0402_25V7K
1

2
1
FCH HAS 15K INTERNAL PU-UP FOR PCI_AD[27:23] C687 C688
4.7U_0805_10V4Z 1U_0402_6.3V6K
@ 2
3 2 3

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI

PULL PLL ILA PLL PCIE STRAPS MEM BOOT
HIGH AUTORUN
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI

LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
AUTORUN

PCI_AD27
22 PCI_AD27
PCI_AD26
22 PCI_AD26
PCI_AD25
22 PCI_AD25
PCI_AD24
22 PCI_AD24
PCI_AD23
22 PCI_AD23

4 4
1

R247 R248 R249 R250 R251

@ @ @ @ @
2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5% 2.2K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 25 of 51
A B C D E
 A B C D E

www.qdzbwx.com +VCC_FCH_R +1.1VS

U1C HUDM3R3@ U1E HUDM3R3@
+3VS +VCC_FCH_R
10mils 1 2

2.2U_0603_6.3V6K
HUDSON-2 R193 0_0805_5% HUDSON-2
+3VS 50mils

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M
1 2 +VDDIO_33_PCIGP AB17 T14 A3 T25
VDDIO_33_PCIGP_1 VDDCR_11_1 VSS VSS

22U_0805_6.3V6M
L30 R20 0_0603_5% AB18 T17 1 1 1 1 1 1 Add Q40 for A33 T27
VDDIO_33_PCIGP_2 VDDCR_11_2 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
+VDDPL_3.3V C311 C312 C313 C314 C315 C317

PCI/GPIO I/O
1 2 AE9 VDDIO_33_PCIGP_3 VDDCR_11_3 T20 B7 VSS VSS U6
leakage issue

2.2U_0603_6.3V6K
MBK1608221YZF_2P

0.1U_0402_16V7K
1 1 1 1 1 AD10 VDDIO_33_PCIGP_4 VDDCR_11_4 U16 B13 VSS VSS U14
220 ohm C266 C267 C269 C270 C271 AG7 131mA 1007mA U18 D9 U17
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 2 VSS VSS

CORE S0
1 1 AC13 VDDIO_33_PCIGP_6 VDDCR_11_6 V14 D13 VSS VSS U20
C272 C273 AB12 V17 +5VS E5 U21
1 2 2 2 2 2 VDDIO_33_PCIGP_7 VDDCR_11_7 VSS VSS 1
AB13 VDDIO_33_PCIGP_8 VDDCR_11_8 V20 E12 VSS VSS U30
AB14 Y17 @ E16 U32
VDDIO_33_PCIGP_9 VDDCR_11_9 VSS VSS

2
2 2 +1.1VS_CKVDD Q40 +1.1VS

G
AB16 VDDIO_33_PCIGP_10 E29 VSS VSS V11

+VDDPL_3.3V
10mils 20mils +1.1VS_CKVDD
F7 VSS VSS V16
H24 VDDPL_33_SYS 47mA VDDAN_11_CLK_1 H26 1 3 F9 VSS VSS V18

2.2U_0603_6.3V6K
10mils J25 F11 W4

S
+FCH_VDDAN_33_DAC_R VDDAN_11_CLK_2 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M
+FCH_VDDPL_33_MLDAC 20mA

CLKGEN I/O
V22 VDDPL_33_DAC VDDAN_11_CLK_3 K24 F13 VSS VSS W6
10mils L22 1 1 1 1 1 1 AO3416_SOT23-3 F16 W25
@ +FCH_VDDPL_33_MLDAC VDDAN_11_CLK_4 C319 C320 C321 C322 C323 C318 VSS VSS
1 2 U22 VDDPL_33_ML 20mA 340mAVDDAN_11_CLK_5 M22 F17 VSS VSS W28
R19 0_0603_5% 10mils N21 1 2 F19 Y14
VDDAN_11_CLK_6 VSS VSS
2.2U_0603_6.3V6K

L33 VDDPL_33_SSUSB_S +FCH_VDDAN_33_DAC_R 30mA R371 0_0603_5%

0.1U_0402_16V7K
T22 VDDAN_33_DAC VDDAN_11_CLK_7 N22 F23 VSS VSS Y16
2 2 2 2 2 2
+3VS 1 2
MBK1608221YZF_2P
For Hudson M3 USB3.0 only +FCH_VDDPL_33_SSUSB
10mils VDDAN_11_CLK_8 P22 F25 VSS VSS Y18
1 1
For Hudson M2, connect to GND
L18 VDDPL_33_SSUSB_S 20mA F29 VSS VSS AA6
UMA@ C275 C274 10mils G6 AA12
+FCH_VDDPL_33_USB +PCIE_VDDR_FCH +1.1VS VSS VSS
D7 VDDPL_33_USB_S 17mA 50mils G16 VSS VSS AA13
UMA@ UMA@ 10mils AB24 G32 AA14
C274 2 2 +VDDPL_33_PCIE VDDAN_11_PCIE_1 +PCIE_VDDR_FCH VSS VSS
AH29 VDDPL_33_PCIE 43mA VDDAN_11_PCIE_2 Y21 1 2 H12 VSS VSS AA16

PCI EXPRESS

2.2U_0603_6.3V6K
0_0402_5% 10mils AE25 R194 0_0805_5% H15 AA17
VDDAN_11_PCIE_3 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M
DIS@ +VDDPL_33_SATA 93mA

GROUND
AG28 VDDPL_33_SATA VDDAN_11_PCIE_4 AD24 H29 VSS VSS AA25
LDO_CAP: Internally generated 1.8V 1088mA
VDDAN_11_PCIE_5 AB23 1 1 1 1 1 1 J6 VSS VSS AA28
@ 15mils AA22 C327 C328 C329 C330 C499 C326 J9 AA30
+3VALW supply for the RGB output LDO_CAP VDDAN_11_PCIE_6 VSS VSS
1 2 M31 LDO_CAP VDDAN_11_PCIE_7 AF26 J10 VSS VSS AA32
M3@ L34 +FCH_VDDAN_11_MLDAC C298 2.2U_0603_6.3V6K AG27 J13 AB25
+FCH_VDDPL_33_SSUSB L24 UMA@ VDDAN_11_PCIE_8 2 2 2 2 2 2 VSS VSS
1 2 10mils J28 VSS VSS AC6
2.2U_0603_6.3V6K

MBK1608221YZF_2P +VDDAN_11_DAC 7mA

0.1U_0402_16V7K

1 2 V21 VDDPL_11_DAC J32 VSS VSS AC18

220 ohm MBK1608221YZF_2P +1.1VS
60mils +AVDD_SATA
K7 VSS VSS AC28
1 1 220 ohm VDDAN_11_SATA_1 AA21 K16 VSS VSS AD27
C279 C278 20mils Y20 +AVDD_SATA 1 2 K27 AE6
VDDAN_11_SATA_4 VSS VSS

2.2U_0603_6.3V6K
C278 +FCH_VDDAN_11_MLDAC Y22 AB21 R370 0_0805_5% K28 AE15
VDDAN_11_ML_1 VDDAN_11_SATA_2 VSS VSS

MAIN LINK
2.2U_0603_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

22U_0805_6.3V6M
0_0402_5% M3@ M3@

SERIAL ATA
0.1U_0402_16V7K

0.1U_0402_16V7K
V23 VDDAN_11_ML_2 VDDAN_11_SATA_3 AB22 L6 VSS VSS AE21
M2@ 2 2
V24 VDDAN_11_ML_3 226mA VDDAN_11_SATA_5 AC22 1 1 1 1 1 1 L12 VSS VSS AE28
1 1 1 V25 1337mA AC21 C501 C502 C503 C504 C505 C500 L13 AF8
C299 C300 C301 VDDAN_11_ML_4 VDDAN_11_SATA_6 VSS VSS
VDDAN_11_SATA_7 AA20 L15 VSS VSS AF12
2 2
VDDAN_11_SATA_8 AA18 L16 VSS VSS AF16
+VDDAN_33_USB C301 C300 UMA@ UMA@ UMA@ 2 2 2 2 2 2
VDDAN_11_SATA_9 AB20 L21 VSS VSS AF33
L35 0_0402_5% 0_0402_5% 2 2 2
VDDAN_11_SATA_10 AC19 M13 VSS VSS AG30
1 2 +FCH_VDDPL_33_USB DIS@ DIS@ AB10 +3VALW M16 AG32
VDDIO_33_GBE_S VSS VSS
2.2U_0603_6.3V6K

MBK1608221YZF_2P 10mils
0.1U_0402_16V7K

M21 VSS VSS AH5

220 ohm AB11 N18 +VDDIO_33_S 1 2 M25 AH11

GBE LAN
VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS VSS

2.2U_0603_6.3V6K
1 1 AA11 L19 R26 0_0402_5% N6 AH18
VDDCR_11_GBE_S_2 VDDIO_33_S_2 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K
C280 C281 M18 N11 AH19
VDDIO_33_S_3 VSS VSS

3.3V_S5 I/O
AA9 VDDIO_GBE_S_1 VDDIO_33_S_4 V12 1 1 1 N13 VSS VSS AH21
AA10 59mA V13 C507 C508 C506 N23 AH23
2 2 +3VALW VDDIO_GBE_S_2 VDDIO_33_S_5 VSS VSS
VDDIO_33_S_6 Y12 N24 VSS VSS AH25
L56 30mils Y13 P12 AH27
+VDDAN_33_USB VDDIO_33_S_7 2 2 2 VSS VSS
1 2 G7 VDDAN_33_USB_S_1 VDDIO_33_S_8 W11 P18 VSS VSS AJ18
22U_0805_6.3V6M

FBMA-L11-201209-221LMA30T_0805 H8 P20 AJ28

+3VS VDDAN_33_USB_S_2 +3VALW VSS VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

220 ohm/3A J8 VDDAN_33_USB_S_3 P21 VSS VSS AJ29

L36 1 1 1 K8 10mils L28 P31 AK21
+VDDPL_33_PCIE C289 C290 C292 VDDAN_33_USB_S_4 +VDDXL_3.3V VSS VSS
1 2 K9 VDDAN_33_USB_S_5 5mA VDDXL_33_S G24 1 2 P33 VSS VSS AK25
2.2U_0603_6.3V6K

2.2U_0603_6.3V6K
MBK1608221YZF_2P MBK1608221YZF_2P
0.1U_0402_16V7K

0.1U_0402_16V7K
M9 VDDAN_33_USB_S_6 R4 VSS VSS AL18
220 ohm 2 2 2
M10 VDDAN_33_USB_S_7 658mA 220 ohm R11 VSS VSS AM21
1 1 N9 VDDAN_33_USB_S_8 1 1 R25 VSS VSS AM25
C294 C293 N10 C510 C509 R28 AN1
VDDAN_33_USB_S_9 VSS VSS
M12 VDDAN_33_USB_S_10 T11 VSS VSS AN18
N12 VDDAN_33_USB_S_11 T16 VSS VSS AN28
2 2 2 2
M11 VDDAN_33_USB_S_12 T18 VSS VSS AN33
+1.1VALW
L58 +1.1VALW
20mils N8 T21

USB
+VDDANCR_11_USB VSSAN_HWM VSSPL_DAC
1 2 U12 VDDAN_11_USB_S_1 10mils VSSAN_DAC L28
2.2U_0603_6.3V6K

MBK1608221YZF_2P 140mA +VDDCR_1.1V

0.1U_0402_16V7K

0.1U_0402_16V7K

U13 VDDAN_11_USB_S_2 VDDCR_11_S_1 N20 1 2 K25 VSSXL VSSANQ_DAC K33

+3VS

2.2U_0603_6.3V6K
220 ohm 187mA VDDCR_11_S_2 M20 R373 0_0603_5% N28
VSSIO_DAC

1U_0402_6.3V6K
L22 1 1 1 H25
+VDDPL_33_SATA C303 C302 C304 VSSPL_SYS
1 2 1 1 EFUSE R6
2.2U_0603_6.3V6K

MBK1608221YZF_2P C512 C511

0.1U_0402_16V7K

220 ohm 2 2 2
3 1 1 3
C297 C296 2 2 HUDSON-M3_FCBGA656

2 2 +1.1VALW Connect to GND through a dedicated via

T12 197mA 10mils L29
VDDCR_11_USB_S_1 +VDDPL_1.1V
T13 VDDCR_11_USB_S_2 70mA VDDPL_11_SYS_S J24 1 2

2.2U_0603_6.3V6K
MBK1608221YZF_2P

0.1U_0402_16V7K
220 ohm
1 1
C514 C513

2 2

+3VALW
+1.1VALW +VDDANCR_11_SSUSB
L62 M3@
40mils 10mils +VDDAN_33_HWM
P16 VDDAN_11_SSUSB_S_1 12mA VDDAN_33_HWM_S M8 1 2

2.2U_0603_6.3V6K
+VDDANCR_11_SSUSB R27 0_0402_5%

0.1U_0402_16V7K
2 1 M14 VDDAN_11_SSUSB_S_2
10U_0603_6.3V6M

FBMA-L11-201209-221LMA30T_0805
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

N14 VDDAN_11_SSUSB_S_3
1U_0402_6.3V6K

1U_0402_6.3V6K

220 ohm/3A P13 VDDAN_11_SSUSB_S_4 282mA 1 1

1 1 1 1 1 1 1 P14 C516 C515
C197 C305 C306 C307 C308 C309 C310 VDDAN_11_SSUSB_S_5
USB SS

M3@ M3@ M3@ M3@ M3@ M3@ M3@ 2 2

2 2 2 2 2 2 2
N16 VDDCR_11_SSUSB_S_1
N17 +3VS
VDDCR_11_SSUSB_S_2
P17 VDDCR_11_SSUSB_S_3 424mA 10mils +VDDIO_AZ
M17 VDDCR_11_SSUSB_S_4 26mA VDDIO_AZ_S AA4 1 2
R28 0_0402_5%
C310 POWER 1
0_0402_5% C517
M2@ HUDSON-M3_FCBGA656 1U_0402_6.3V6K
4 4
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 26 of 51
A B C D E
 5 4 3 2 1

www.qdzbwx.com
+DVDD12 +DVDD33

+3VS +3VS_ANX
40mil
UMA@ +3VS_ANX

32
46
59

13
53
9
1 UMA@ 2 U8
R944 0_0805_5% +AVDD12 +AVDD33 UMA_LCD_CLK R1314 1 UMA@ 2 4.7K_0402_5%

DVDD12
DVDD12
DVDD12
DVDD12

DVDD33
DVDD33
D UMA_LCD_DATA R1313 1 UMA@ 2 4.7K_0402_5% D
1 AVDD12 AVDD33 8
+1.2VS +1.2VS_ANX
40mil AVDD33 25
AVDD33 33
AVDD33 39
AVDD33 63
1 UMA@ 2
R946 0_0805_5% DP0_AUXN_C 60
7 DP0_AUXN_C DPRX_AUX_N
DP0_AUXP_C 61
7 DP0_AUXP_C DPRX_AUX_P
PD 100K at Page10 9 LVDS_HPD LVDS_HPD 1 UMA@ 2 58 26 APU_TXOUT_CLK- 28
R1317 0_0402_5% 4 DPPX_HPD LVDS_CLKL_N
7 DP0_TXN0_C DPRX_LN0_N LVDS_CLKL_P 27 APU_TXOUT_CLK+ 28
7 DP0_TXP0_C 3 DPRX_LN0_P LVDS_L0_N 19 APU_TXOUT0- 28
7 DP0_TXN1_C 7 DPRX_LN1_N LVDS_L0_P 20 APU_TXOUT0+ 28
+DVDD12
L150UMA@
20mil 7 DP0_TXP1_C 6 DPRX_LN1_P LVDS_L1_N 21 APU_TXOUT1- 28
LVDS_L1_P 22 APU_TXOUT1+ 28
+1.2VS_ANX FBMA-L11-201209-221LMA30T_0805 23 APU_TXOUT2- 28
0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K LVDS_L2_N
2 1 +3VS_ANX 1 UMA@ 2 10 CLK_SEL LVDS_L2_P 24 APU_TXOUT2+ 28
2 2 2 2 1 1 1 R30 10K_0402_5% 12 28
12,22,32,33 APU_PCIE_RST# RESET_L LVDS_L3_N
C1513 C1514 C1515 C1516 C1517 C1518 C1519 28 ANX_ENVDD 14 29
DIGON LVDS_L3_P
UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ UMA@ +3VS_ANX 1 UMA@ 2
1 1 1 1 2 2 2 R1312 1M_0402_5%
LVDS_CLKU_N 42 APU_TZOUT_CLK- 28
0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V4Z 2 1 34 43 APU_TZOUT_CLK+ 28
C1509 0.1U_0402_16V7K POR LVDS_CLKU_P
LVDS_U0_N 35 APU_TZOUT0- 28
UMA@ 36 APU_TZOUT0+ 28
+AVDD12 LVDS_U0_P
T57 51 CFG_SCL LVDS_U1_N 37 APU_TZOUT1- 28
L151UMA@ 20mil T58 52 38 APU_TZOUT1+ 28
CFG_SDA LVDS_U1_P
+1.2VS_ANX FBMA-L11-201209-221LMA30T_0805 LVDS_U2_N 40 APU_TZOUT2- 28
2 1 0.1U_0402_16V7K 0.01U_0402_16V7K R78 1 UMA@ 2 10K_0402_5% 16 41 APU_TZOUT2+ 28
GPIO_0 LVDS_U2_P
2 2 1 1 1 T59 17 GPIO_1 LVDS_U3_N 44
C1521 C1522 C1525 C1526 C1527 T60 18 45
GPIO_2 LVDS_U3_P
2 1
UMA@ UMA@ UMA@ UMA@ UMA@ R1315 UMA@ 12K_0402_1%
C 1 1 2 2 2 UMA@1 R_BIAS UMA_LCD_CLK C
2 64 R_BIAS DDC_CLK 49 UMA_LCD_CLK 28
0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V4Z C1510 100P_0402_50V8J 50 UMA_LCD_DATA UMA_LCD_DATA 28
DDC_DATA

T61 55 TDI
20mil +DVDD33 T62 57 TMS BL_EN 15 ANX_BKOFF# 28
T63 56 TCK VARY_BL 47 ANX_INVT_PWM 28
L152UMA@ T64 54 48
TDO CPU_VARY_BL APU_INVT_PWM 9,28
+3VS_ANX FBMA-L11-201209-221LMA30T_0805 1 2 11 31
TEST_EN OSC_OUT TRAVIS_CLK# 22
2 1 0.1U_0402_16V7K R96 10K_0402_5%
OSC_IN 30 TRAVIS_CLK 22
2 1 65 PAD

AVSS
AVSS
AVSS
C1529 C1530

UMA@ UMA@
1 2 ANX3110_QFN64_9X9

2
5
62
2.2U_0603_6.3V4Z +3VS_ANX

DP0_AUXP_C 2 @ 1
+AVDD33 R1321 1M_0402_5%
L153UMA@
20mil
+3VS_ANX FBMA-L11-201209-221LMA30T_0805 DP0_AUXN_C 2 @ 1
2 1 0.1U_0402_16V7K 0.1U_0402_16V7K 0.01U_0402_16V7K R1323 1M_0402_5%
2 2 2 1 1 1
C1532 C1533 C1534 C1535 C1536 C1537

UMA@ UMA@ UMA@ UMA@ UMA@ UMA@

1 1 1 2 2 2
0.1U_0402_16V7K 0.01U_0402_16V7K 2.2U_0603_6.3V4Z Place via on each trace bus and let resistor very close the via.

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2010/12/30 Deciphered Date 2012/01/01 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019D8 B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, July 04, 2011 Sheet 27 of 51
5 4 3 2 1
 A B C D E F G H

27 APU_TXOUT0+
For UMA & PowerXpress
1 UMA@ 2 LVDS_TXOUT0+
To prevent EC pin damage
1
RD449
@ 2
0_0402_5%
www.qdzbwx.com
+LCD_VDD +3VS +5VS
RD107
150_0603_5%
EDP@
CD229
0.01U_0402_25V7K
RD109
47K_0402_5%
EDP@
QD1
CD233
0.1U_0402_16V4Z
EDP@

2N7002DW-T/R7_SOT363-6

1
RD262 0_0402_5% DD29 EDP@ EDP@

1
27 APU_TXOUT0- 1 UMA@ 2 LVDS_TXOUT0- LED_PWM 2 1 LED_PWM_D RD107
RD263 0_0402_5% 150_0603_5% RD108 RD120
+3VS +5VS
27 APU_TXOUT1+ 1 UMA@ 2 LVDS_TXOUT1+ RB751V40_SC76-2 1 2 UMA@ 100K_0402_5% 100K_0402_5%
RD265 0_0402_5% RD144 47K_0402_5% UMA@ EDP@

2
27 APU_TXOUT1- 1 UMA@ 2 LVDS_TXOUT1-

2
RD264 0_0402_5% DD30

6
27 APU_TXOUT2+ 1 UMA@ 2 LVDS_TXOUT2+
37 BKOFF# 2 1 BKOFF#_D
RD298 0_0402_5% UMA@ 2 W=80mils EDP@ 2 W=80mils
1 1
27 APU_TXOUT2- 1 UMA@ 2 LVDS_TXOUT2- RB751V40_SC76-2 1 2 QD1A CD228 CD251
RD277 0_0402_5% RD113 10K_0402_5% UMA@ 2 0.1U_0402_16V7K 0.1U_0402_16V7K

3
S S
27 APU_TXOUT_CLK+ 1 UMA@ 2 LVDS_TXCLK+ 2N7002DW-T/R7_SOT363-6 UMA@ EDP@
RD297 0_0402_5% RD1092LCDPWR_GATE 1 G
QD17 LCDPWR_GATE 1 G
QD23
1 2 2

1
27 APU_TXOUT_CLK- 1 UMA@ 2 LVDS_TXCLK- 47K_0402_5% 1 AO3413_SOT23 AO3413_SOT23

3
RD296 0_0402_5% Reserve for EMI request UMA@ D D

1
1 UMA@ 2 LVDS_TZOUT0+ CD229 +LCD_VDD
27 APU_TZOUT0+
RD268 0_0402_5% 0.01U_0402_25V7K +LCD_VDD
UMA@ 2
W=80mils
27 APU_TZOUT0- 1 UMA@ 2 LVDS_TZOUT0- 1 CAM@ 2 LCD_ENVDD 5
RD267 0_0402_5% RD78 0_0402_5% QD1B 1
27 APU_TZOUT1+ 1 UMA@ 2 LVDS_TZOUT1+ LD55 @ 2N7002DW-T/R7_SOT363-6 CD233 W=80mils

4
RD269 0_0402_5% 1 1 USB20_N5_R UMA@ 0.1U_0402_16V4Z
23 USB20_N5 2 2

2
27 APU_TZOUT1- 1 UMA@ 2 LVDS_TZOUT1- UMA@
RD266 0_0402_5% RD112 2
27 APU_TZOUT2+ 1 UMA@ 2 LVDS_TZOUT2+ 23 USB20_P5 4 4 3 3 USB20_P5_R 100K_0402_5%
RD302 0_0402_5% UMA@
27 APU_TZOUT2- 1 UMA@ 2 LVDS_TZOUT2- WCM-2012-900T_0805

1
RD278 0_0402_5% RD107 RD108 RD109 CD228
27 APU_TZOUT_CLK+ 1 UMA@ 2 LVDS_TZCLK+ 1 CAM@ 2 150_0603_5% 100K_0402_5% 47K_0402_5% 0.1U_0402_16V7K
RD301 0_0402_5% RD96 0_0402_5% NO3D@ NO3D@ NO3D@ NO3D@
27 APU_TZOUT_CLK- 1 UMA@ 2 LVDS_TZCLK-
RD303 0_0402_5% QD1 CD229 CD233
27 UMA_LCD_CLK 1 UMA@ 2 LVDS_EDID_CLK 2N7002DW-T/R7_SOT363-6 0.01U_0402_25V7K 0.1U_0402_16V4Z
RD300 0_0402_5% NO3D@ NO3D@ NO3D@
27 UMA_LCD_DATA 1 UMA@ 2 LVDS_EDID_DATA EC PWM
RD299 0_0402_5% QD17
9,27 APU_INVT_PWM 1 @ 2 LED_PWM AO3413_SOT23
RD332 0_0402_5% 1 @ 2 LED_PWM NO3D@
37 INVT_PWM
1 @ 2 LCD_ENVDD RD387 0_0402_5%
9 APU_ENVDD
2 RD350 0_0402_5% 2
1 @ 2 EC_ENBKL
9 APU_ENBKL EC_ENBKL 37
RD357 0_0402_5%

Close to LVDS Connector

For DISCRETE LCD/PANEL BD. Conn. RD1440

0_0603_5%
UMA@

W=20mils CAM@
Remove LVDS channel 0.1U_0402_16V4Z 1 RD143 2 EDP@ EDP_HPD 13
+3VS 1 CAM@ 2 +3VS_LVDS_CAM 1 2 0_0402_5%
RD388 0_0603_5% CD225
JLVDS @ +3VS_LVDSDDC 2 RD1440 1 NOEDP@ +3VS
1 2 0_0603_5%
LED_PWM USB20_P5_R 1 2 LVDS_TXCLK+
12 VGA_INVT_PWM 1 DIS@ 2 3 3 4 4
RD349 0_0402_5% USB20_N5_R 5 6 LVDS_TXCLK- DD84 For EMI
5 6
12 VGA_ENVDD 1 DIS@ 2 LCD_ENVDD 7 7 8 8 2 1 1
RD356 0_0402_5% LVDS_TXOUT0+ 9 10 LVDS_TZCLK+ 1 @ NOEDP@
9 10
13 VGA_ENBKL 1 DIS@ 2 EC_ENBKL LVDS_TXOUT0- 11 11 12 12 LVDS_TZCLK- 3 CD231 CD232
RD358 0_0402_5% LVDS_TXOUT1+ 13 14 680P_0402_50V7K 0.1U_0402_16V4Z
LVDS_TXOUT1- 13 14 LVDS_EDID_CLK YSLC05CH_SOT23-3 2 2
15 15 16 16
Close to LVDS Connector LVDS_TXOUT2+ 17 18 LVDS_EDID_DATA
LVDS_TXOUT2- 17 18 INT_MIC_CLK
19 19 20 20 INT_MIC_CLK 36
21 22 INT_MIC_DATA
21 22 INT_MIC_DATA 36
LVDS_TZOUT0+ 23 24 LCD_ENVDD
LVDS_TZOUT0- 23 24 LED_PWM_D
25 26
3 Remove DISCRETE for 3D LVDS Panel LVDS_TZOUT1+ 27
25
27
26
28 28 +3VS_LVDSDDC 3A CD232 3

LVDS_TZOUT1- 29 30 +LCD_VDD 0.1U_0402_16V4Z

LVDS_TZOUT2+ 29 30 +LCD_INV B+ UMA@
31 31 32 32 1 1
LVDS_TZOUT2- 33 34 LD2
BKOFF#_D 33 34 CD226 CD227
35 36 2 1
Remove 3D LVDS Panel 37
35
37
36
38 38
2
0.1U_0402_16V4Z
2
4.7U_0805_10V4Z 1 1 FBMA-L11-201209-221LMA30T_0805
+LCD_INV 39 39 40 40 +LCD_INV
41 42 CD234 CD235
GMD GND 68P_0402_50V8J 0.1U_0402_25V6
ACES_87242-4001-09 2 2
DISCRETE for 3D eDP Panel
EDP@
CD880 1 20.1U_0402_16V7K LVDS_TXOUT0+
13 VGA_EDP_TX0+
EDP@
CD881 1 20.1U_0402_16V7K LVDS_TXOUT0-
13 VGA_EDP_TX0- B+
EDP@
CD882 1 20.1U_0402_16V7K LVDS_TXOUT1+ For EMI
13 VGA_EDP_TX1+
EDP@
CD883 1 20.1U_0402_16V7K LVDS_TXOUT1-
13 VGA_EDP_TX1-
EDP@
CD884 1 20.1U_0402_16V7K LVDS_TXOUT2+ 1 1 1 1
13 VGA_EDP_TX2+
EDP@

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
CD885 1 20.1U_0402_16V7K LVDS_TXOUT2-
For LVDS Translator CD236 CD268 CD489 CD490
13 VGA_EDP_TX2- +3VS
EDP@ @ @ @ @
CD886 2 2 2 2
13 VGA_EDP_TX3+ 1 20.1U_0402_16V7K LVDS_TXCLK+
EDP@
CD887 1 20.1U_0402_16V7K LVDS_TXCLK- 2 EDP@ 1 LVDS_EDID_DATA 27 ANX_INVT_PWM 1 UMA@ 2 LED_PWM
13 VGA_EDP_TX3-
RD209 100K_0402_5% RD333 0_0402_5%
Close to LVDS1 Connector 1 UMA@ 2 LCD_ENVDD
27 ANX_ENVDD
4 2 EDP@ 1 LVDS_EDID_CLK RD351 0_0402_5% 4
RD256 100K_0402_5% 1 UMA@ 2 EC_ENBKL
27 ANX_BKOFF#
RD360 0_0402_5%
EDP@
13 VGA_EDP_AUX+
CD888 1 20.1U_0402_16V7K LVDS_EDID_CLK
EDP@
CD889 1 20.1U_0402_16V7K LVDS_EDID_DATA
13 VGA_EDP_AUX- Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title
Close to LVDS Connector SCHEMATIC, MB A7213
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 28 of 51
A B C D E F G H
 A B C D E

www.qdzbwx.com
CRT CONNECTOR

1
D3 @ D4 @ D5 @
+3VS
If=1A
+5VS +CRT_VCC_R +CRT_VCC
D6
For UMA & PowerXpress DAN217_SC59 DAN217_SC59 DAN217_SC59 2 F1 40 mils

3
1 1 2
1 3 RB491D_SOT23-3 1 1
24 UMA_CRT_R 1 UMA@ 2 CRT_R 0.5A_8V_KMC3S050RY
R200 0_0402_5% C237
24 UMA_CRT_G 1 UMA@ 2 CRT_G 0.1U_0402_16V4Z
R204 0_0402_5% CRT_R L3 2
1 2 NBQ100505T-800Y_0402 CRT_R_L @
24 UMA_CRT_B 1 UMA@ 2 CRT_B
R211 0_0402_5% CRT_G L4 1 2 NBQ100505T-800Y_0402 CRT_G_L
24 UMA_CRT_HSYNC 1 UMA@ 2 CRT_HSYNC
R213 0_0402_5% CRT_B L5 1 2 NBQ100505T-800Y_0402 CRT_B_L
24 UMA_CRT_VSYNC 1 UMA@ 2 CRT_VSYNC
R235 0_0402_5% JCRT @
24 UMA_CRT_CLK 1 UMA@ 2 CRT_CLK 6 6
R236 0_0402_5% T75 PAD 11 11

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C

2.2P_0402_50V8C
24 UMA_CRT_DATA 1 UMA@ 2 CRT_DATA R138 R139 R140 CRT_R_L 1 1

150_0402_1%

150_0402_1%

150_0402_1%
R261 0_0402_5% 1 1 1 1 1 1 7 7

1
CRT_DDC_DAT 12
C238 C239 C240 C241 C242 C243 CRT_G_L 12
2 2
Close to CRT Connector 2 2 2 2 2 2
8 8
HSYNC 13
CRT_B_L 13
3

2
3
+CRT_VCC 9 9
VSYNC 14 16
14 G
T76 PAD 4 4 G 17
10 10
CRT_DDC_CLK 15 15
5 5
ALLTO_C10532-11505-L_15P-T

2 2
+CRT_VCC

1 2
C244 0.1U_0402_16V4Z 2 1
R141 10K_0402_5%

5
1
For DISCRETE

P
OE#
CRT_HSYNC 2 4 D_CRT_HSYNC 1 2 HSYNC
A Y L6 10_0402_5%
+CRT_VCC

G
13 VGA_CRT_R 1 DIS@ 2 CRT_R U6
R178 0_0402_5% 74AHCT1G125GW_SOT353-5

5
1
13 VGA_CRT_G 1 DIS@ 2 CRT_G
R181 0_0402_5%

P
OE#
13 VGA_CRT_B 1 DIS@ 2 CRT_B CRT_VSYNC 2 A Y 4 D_CRT_VSYNC 1 2 VSYNC

10P_0402_50V8J

10P_0402_50V8J
R167 0_0402_5% L7 10_0402_5% 1 1

G
1 DIS@ 2 CRT_HSYNC U7
13 VGA_CRT_HSYNC
R177 0_0402_5% 74AHCT1G125GW_SOT353-5 C245 C246

3
13 VGA_CRT_VSYNC 1 DIS@ 2 CRT_VSYNC @ @
R179 0_0402_5% 2 2
13 VGA_CRT_CLK 1 DIS@ 2 CRT_CLK
R209 0_0402_5%
13 VGA_CRT_DATA 1 DIS@ 2 CRT_DATA
R256 0_0402_5%

Close to CRT Connector

3 3

+CRT_VCC

+3VS

2
R153 R159
4.7K_0402_5% 4.7K_0402_5%

1
2
Q205A
CRT_CLK 5 1 6 CRT_DDC_CLK

2N7002DW-T/R7_SOT363-6
Q205B
CRT_DATA 4 3 CRT_DDC_DAT
1 1
1 1 2N7002DW-T/R7_SOT363-6
C284 C283
C282 C285 470P_0402_50V8J 470P_0402_50V8J
33P_0402_50V8K 33P_0402_50V8K @ 2 2 @
@ 2 2 @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 29 of 51
A B C D E
 5 4 3 2 1

HDMI CEC Controller

+3VL +3VL
Address: 0011010X
37,42 EC_SMB_CK1 1
U16

P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 11 CEC_INT#

CEC_INT# 37 +3VL
www.qdzbwx.com
+3VL 2 12 CEC_TEST 1 CEC@ 2
P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# R168 4.7K_0402_5%

2
+3VL +3VL
R162 D9 2 CEC@ 1CEC_RST# 3 13 CEC_FSHUPD1 CEC@ 2
R169 4.7K_0402_5% RESET# P1_4/TXD0 R170 4.7K_0402_5%
10K_0402_5% RB751V40_SC76-2
CEC@ CEC@ CEC_FSHUPD (Pin13)

1
2 CEC@ 1CEC_XOUT 4 14 Low= Force to update flash.

1 1
HDMI_CECIN R171 47K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT R166 R164
+3VL 4.7K_0402_5% 4.7K_0402_5% Q47

2
R581 5 15 CEC@ CEC@ CEC@ BSH111_SOT23-3
VSS/AVSS P1_2/KI2#/AN10/CMP0_2

G
D 27K_0402_5% CEC@ D
1 2

2
Q212A CEC@ C848 1U_0402_6.3V6K
2N7002DW-T/R7_SOT363-6 2 CEC@ 1CEC_XIN 6 16 1 2 HDMI_CLK 3 1 HDMI_SCLK

2
XIN/P4_6 P4_2/VREF

2
CEC@ 2 HDMI_CEC R174 47K_0402_5% C263 0.1U_0402_16V4Z

D
CEC@
7 17 HDMI_CLK
1

VCC/AVCC P1_1/KI1#/AN9/CMP0_1 HDMI_DATA HDMI_SDATA

3 1

D
2 CEC@ 1 8 MODE P1_0/KI0#/AN8/CMP0_0 18 HDMI_DATA Q48
Q212B R176 4.7K_0402_5% BSH111_SOT23-3
HDMI_CECOUT 1 R163 2 5 2N7002DW-T/R7_SOT363-6 C262 1 CEC@
27K_0402_5% CEC@ 0.1U_0402_16V4Z HDMI_CECIN 9 19 HDMI_HPD_R
CEC@
4
CEC@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
1

R165 2 HDMI_CECOUT 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA1 37,42

100K_0402_5%
CEC@
R5F211A4C33SP-W4_LSSOP20 CEC@
2

+1.5VS +3VSG
+HDMI_5V_OUT
+5VL HDMI@
R145

2
HDMI_HPD_U 1 2 HDMI_HPD_C
R453 R452 2 1K_0402_5%
0_0402_5% 0_0402_5% C264 2

2
0.1U_0402_16V4Z R186 C265
For DISCRETE IHDMI@ DHDMI@

1
HDMI@ U9 100K_0402_5% 0.1U_0402_16V4Z

1
C 1 C
IHDMI@ HDMI@ HDMI@

OE#
1

1
HDMI_HPD_R 1
7 UMA_HDMI_CLK 2 1 2 A Y 4
CV296 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC+ R435 0_0402_5% R184 R185
13 VGA_HDMI_CLK+

1
G
2K_0402_1% 2K_0402_1% 74AHCT1G125GW_SOT353-5
CV293 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXC- DHDMI@ HDMI@ HDMI@ HDMI@
13 VGA_HDMI_CLK-

3
2
13 VGA_HDMI_CLK 2 1

2
G
CV294 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0+ R391 0_0402_5%
13 VGA_HDMI_TX0+
CV297 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD0- 3 1 HDMI_SCLK
13 VGA_HDMI_TX0-

2
G

D
CV299 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1+ Q18
13 VGA_HDMI_TX1+
DHDMI@ BSH111_SOT23-3
CV298 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD1- 13 VGA_HDMI_DATA 2 1 3 1 HDMI@ HDMI_SDATA HDMI@ HDMI@
13 VGA_HDMI_TX1-
R401 0_0402_5% +3VL 2 1 2 1 +3VS

D
CV295 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2+ R570 R571
13 VGA_HDMI_TX2+
IHDMI@ Q19 100K_0402_5% 2.2K_0402_5%
CV300 1 2 0.1U_0402_16V7K DHDMI@ VGA_DVI_TXD2- 2 1 BSH111_SOT23-3 D55
13 VGA_HDMI_TX2- 7 UMA_HDMI_DATA
R438 0_0402_5% HDMI@ HDMI_HPD_R 1 2 HDMI_HPD 9,23
RB751V40_SC76-2
HDMI@ DHDMI@
1 2 VGA_HDMI_HPD 13
R374 0_0402_5%
VGA_DVI_TXC- 1 @ 2 HDMI_R_CK- HDMI_R_CK+ 1 2 DHDMI@
R157 0_0402_5% R195 499_0402_1%
L8 HDMI@ HDMI_R_CK- 1 2 DHDMI@
1 R197 499_0402_1%
For UMA & PowerXpress 1 2 2 HDMI_R_D1- 1 2 DHDMI@
R198 499_0402_1% HDMI@
4 3 HDMI_R_D1+ 1 2 DHDMI@ D53 F2
CV308 4 3
5 UMA_HDMI_TXC+ 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC+ R202 499_0402_1% +5VS 2 1 +HDMI_5V_OUT_F 1 2 +HDMI_5V_OUT
OCE2012120YZF HDMI_R_D0+ 1 2 DHDMI@ 1
CV304 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXC- VGA_DVI_TXC+ 1 @ 2 HDMI_R_CK+ R201 499_0402_1% PMEG2010AEH_SOD123 0.5A_8V_KMC3S050RY C259
5 UMA_HDMI_TXC-
B R173 0_0402_5% HDMI_R_D0- 1 2 DHDMI@ HDMI@ HDMI@ B
CV306 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0+ R203 499_0402_1% D54 0.1U_0402_16V4Z
5 UMA_HDMI_TX0+ 2
HDMI_R_D2- 1 2 DHDMI@ +5VL 2 1
CV302 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD0- VGA_DVI_TXD0+ 1 @ 2 HDMI_R_D0+ R205 499_0402_1%
5 UMA_HDMI_TX0-
R175 0_0402_5% HDMI_R_D2+ 1 2 DHDMI@ PMEG2010AEH_SOD123
CV303 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1+ L9 HDMI@ R206 499_0402_1% CEC@
5 UMA_HDMI_TX1+

1
D
1 1 2 2
CV301 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD1- +5VS 2 Q24
5 UMA_HDMI_TX1-
G 2N7002_SOT23-3
CV307 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2+ 4 3 S HDMI@
5 UMA_HDMI_TX2+

3
4 3
CV305 1 2 0.1U_0402_16V7K IHDMI@ VGA_DVI_TXD2- OCE2012120YZF
5 UMA_HDMI_TX2-
VGA_DVI_TXD0- 1 @ 2 HDMI_R_D0-
R180 0_0402_5%
HDMI Connector
VGA_DVI_TXD1- 1 @ 2 HDMI_R_D1- JHDMI @
R182 0_0402_5% HDMI_HPD_C 19
L10 HDMI@ HP_DET
+HDMI_5V_OUT 18 +5V
1 1 2 2 17 DDC/CEC_GND
R195 R197 HDMI_SDATA 16
604_0402_1% 604_0402_1% HDMI_SCLK SDA
15 SCL
4 3 IHDMI@ IHDMI@ 14
4 3 HDMI_CEC Reserved
13 CEC
OCE2012120YZF R198 R202 HDMI_R_CK- 12 20
VGA_DVI_TXD1+ @ HDMI_R_D1+ 604_0402_1% 604_0402_1% CK- GND
1 2 11 CK_shield GND 21
R183 0_0402_5% IHDMI@ IHDMI@ HDMI_R_CK+ 10 22
HDMI_R_D0- CK+ GND
9 D0- GND 23
R201 R203 8
VGA_DVI_TXD2+ @ HDMI_R_D2+ 604_0402_1% 604_0402_1% HDMI_R_D0+ D0_shield
1 2 7 D0+
R187 0_0402_5% IHDMI@ IHDMI@ HDMI_R_D1- 6
L11 HDMI@ D1-
5 D1_shield
1 R205 R206 HDMI_R_D1+
A
1 2 2 604_0402_1% 604_0402_1% HDMI_R_D2-
4 D1+ A
3 D2-
IHDMI@ IHDMI@ 2
HDMI_R_D2+ D2_shield
4 4 3 3 1 D2+
OCE2012120YZF TYCO_1939864-1_19P
VGA_DVI_TXD2- 1 @ 2 HDMI_R_D2-
R188 0_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 30 of 51
5 4 3 2 1
 5 4 3 2 1

SATA HDD Conn. SATA ODD Conn. www.qdzbwx.com

USB Board@ Left Side

Close to JODD Q8

Place components closely HDD CONN. JODD @

S
+USB_VCCC 1 3 +USB_VCCB
+5VS 1
1 SATA_FTX_C_DRX_P1 C376 1
D
1.2A 2 2 2 0.01U_0402_25V7K SATA_FTX_DRX_P1 24
AO3413_SOT23
D
3 SATA_FTX_C_DRX_N1 C377 1 2 0.01U_0402_25V7K 1 2

G
SATA_FTX_DRX_N1 24 +5VALW

2
3 R568 100K_0402_5%
1 1 1 1 4 4
C356 C357 C358 C359 5 SATA_FRX_DTX_N1 C378 1 2 0.01U_0402_25V7K
5 SATA_FRX_C_DTX_N1 24
10U_0805_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 6 SATA_FRX_DTX_P1 C375 1 2 0.01U_0402_25V7K 37 USB_EN# USB_EN#
6 SATA_FRX_C_DTX_P1 24
7 7
2 2 2 2 ODD_PLUGIN#_R
8 8 1 2 ODD_PLUGIN# 23
9 +5VS_ODD R561 0_0402_5%
9
10 10
11 ODD_DA#
11 ODD_DA# 23
12 12
13 +USB_VCCC
GND
GND 14

ACES_88058-120N W=60mils
@ JHDD1 Close to JHDD C428 1 2 1000P_0402_50V7K

GND 1
2 SATA_FTX_C_DRX_P0 C369 1 2 0.01U_0402_25V7K 2 @ 1 C389 1 2 0.1U_0402_16V4Z
A+ SATA_FTX_DRX_P0 24
3 SATA_FTX_C_DRX_N0 C367 1 2 0.01U_0402_25V7K R190 0_0402_5%
A- SATA_FTX_DRX_N0 24
GND 4
5 SATA_FRX_DTX_N0 C368 1 2 0.01U_0402_25V7K L15 JUSB @
B- SATA_FRX_C_DTX_N0 24
6 SATA_FRX_DTX_P0 C370 1 2 0.01U_0402_25V7K 23 USB20_N2 4 3 1
B+ SATA_FRX_C_DTX_P0 24 4 3 VCC
7 USB20_N2_R 2
GND USB20_P2_R D-
3 D+
23 USB20_P2 1 1 2 2 4 GND
V33 8 +3VS
9 WCM-2012-900T_0805 5
V33 GND1
V33 10 6 GND2
11 2 @ 1 7
GND R189 0_0402_5% GND3
GND 12 8 GND4
GND 13
C ACON_UARB2-4K1926 C
V5 14 +5VS
V5 15
V5 16
GND 17
18 D23
Reserved USB20_N2_R
GND 19 2
V12 20 1
24 21 USB20_P2_R 3
GND V12
23 GND V12 22
AZC199-02SPR7G_SOT23-3

OCTEK_SAT-22SO1G

USB Board@ Right Side W=60mils

SATA 2nd HDD Conn. +5VALW 2.5A +USB_VCCA
For EMI
U14
+5VS
Place closely JHDD2 SATA CONN. 1 GND VOUT 8 2
C361
1
1000P_0402_50V7K
1.2A 2 VIN VOUT 7
3 VIN VOUT 6
1 1 1 1 USB_EN# 4 5 USB_OC0# 23,37
C363 C372 C373 C374 EN FLG
1
10U_0805_10V6K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z RT9715BGS_SO8
R73 0_0402_5% C362
B 2 2 2 2 @ 4.7U_0805_10V4Z B
1 2
2 @
L53
23 USB20_N0 1 2 USB20_N0_R
1 2

USB20_P0_R
W=60mils
23 USB20_P0 4 4 3 3

WCM-2012-900T_0805 +USB_VCCA
ACES_85201-2005N
Close to JHDD2 1 @ 2 1
R87 0_0402_5% 1
+5VL 1 2 2 2
@ JHDD2 R149 0_0402_5% 3
R77 0_0402_5% 3
1 1 2 2 4 4
3 4 SATA_FTX_C_DRX_P2 C364 1 2 0.01U_0402_25V7K 1 @ 2 +5VALW 1 @ 2 +5V_IO 5
3 4 SATA_FTX_DRX_P2 24 5
5 6 SATA_FTX_C_DRX_N2 C365 1 2 0.01U_0402_25V7K R148 0_0402_5% USB20_N1_R 6
5 6 SATA_FTX_DRX_N2 24 6
7 8 L54 USB20_P1_R 7
7 8 SATA_FRX_DTX_N2 C366 1 7
9 9 10 10 2 0.01U_0402_25V7K SATA_FRX_C_DTX_N2 24 23 USB20_N1 1 1 2 2 USB20_N1_R 8 8
11 12 SATA_FRX_DTX_P2 C371 1 2 0.01U_0402_25V7K 9
11 12 SATA_FRX_C_DTX_P2 24 9
13 14 USB20_N0_R 10
13 14 USB20_P1_R USB20_P0_R 10
15 15 16 16 23 USB20_P1 4 4 3 3 11 11
17 17 18 18 +5VS 12 12
19 20 WCM-2012-900T_0805 13
19 20 13
21 21 22 22 36 HP_R 14 14
23 24 1 @ 2 15
23 24 36 HP_L 15
R88 0_0402_5% 16 16
ACES_85203-1202L 36 MIC1_L 17 17
36 MIC1_R 18 18
36 NBA_PLUG 19 19
D24 @ D25 @ 20
36 BACK_SENSE 20
USB20_N0_R 2 USB20_N1_R 2 21 21
1 1 22
A
Confirm SSD need 3V or not. USB20_P0_R 3 USB20_P1_R 3
22
@
A

AZC199-02S.R7G_SOT23-3 AZC199-02S.R7G_SOT23-3 JPIO

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 31 of 51
5 4 3 2 1
 A B C D E F G H

Slot 1 Half PCIe Mini Card-WLAN

WLAN&BT Combo module circuits
Slot 2 Half PCIe Mini Card- JET
Remove 3G/TV tuner
www.qdzbwx.com +3VS

1
120 mils
0.1U_0402_16V4Z
1 1
For SED +1.5VS

0.1U_0402_16V4Z
1 1 1
For SED

1
CM4 CM5 CM6 C255
BT_CTRL BT BT 47P_0402_50V8J CM12 CM11 CM10 C288
on module on module 0.01U_0402_25V7K @ @ @ @ 47P_0402_50V8J

2
2 2 2 2 2 2 @

1
D 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z
+3VS 2 2 1 1 +3V_WLAN Enable Disable +1.5VS +3VS
2 Q36
24 BT_ON#
PJ26@ JUMP_43X79 G JTV @
S 2N7002_SOT23-3 BT_CRTL H L 1 2 2.75A

3
1 2
Short PJ26 for WLAN 3 3 4 4
5 5 6 6
1 BT_ON# L H 23 CLKREQ_JET# 7 7 8 8 1
9 9 10 10
22 CLK_JET# 11 11 12 12
22 CLK_JET 13 13 14 14
15 15 16 16
17 17 18 18
19 19 20 20 3G_OFF# 24
21 22 APU_PCIE_RST#
21 22
+3V_WLAN
40 mils +1.5VS 5 PCIE_FRX_JETTX_N2 23 23 24 24
For SED 5 PCIE_FRX_JETTX_P2 25 25 26 26
For SED 27 27 28 28
0.1U_0402_16V4Z 0.1U_0402_16V4Z 29 30 FCH_SCLK0
29 30 FCH_SDATA0
1 1 1 1 1 1 5 PCIE_FTX_C_JETRX_N2 31 31 32 32
1

1
5 PCIE_FTX_C_JETRX_P2 33 33 34 34
CM1 CM2 CM3 C253 CM7 CM8 CM9 C254 35 36
47P_0402_50V8J @ @ @ 47P_0402_50V8J 35 36
37 38
2

2
2 2 2 @ 2 2 2 @ 37 38
+3VS 39 39 40 40
0.01U_0402_25V7K 4.7U_0805_10V4Z 0.01U_0402_25V7K 4.7U_0805_10V4Z 41 42
41 42
43 43 44 44
45 45 46 46
47 47 48 48
49 49 50 50
+1.5VS +3V_WLAN 51 52
@ JWLAN @ 51 52
R1443 1 2 53 54
0_0402_5% 1 2 GND1 GND2
3 3 4 4
BT_CTRL 1 2BT_CTRL_R 5 6
5 6 FOX_AS0B226-S40N-7F
23 CLKREQ_WLAN# 7 7 8 8
9 9 10 10
22 CLK_WLAN# 11 11 12 12
22 CLK_WLAN 13 13 14 14
15 16 R21
2 15 16 0_0402_5% 2
17 17 18 18
19 20 WLAN_OFF# 1 2
19 20 WL_OFF# 24
21 21 22 22 APU_PCIE_RST# 12,22,27,33 Need to double check JET pin define
5 PCIE_FRX_WLANTX_N1 23 23 24 24
5 PCIE_FRX_WLANTX_P1 25 25 26 26
27 27 28 28
29 29 30 30 FCH_SCLK0 10,11,23
5 PCIE_FTX_C_WLANRX_N1 31 31 32 32 FCH_SDATA0 10,11,23
5 PCIE_FTX_C_WLANRX_P1 33 33 34 34
35 35 36 36 USB20_N8 23
WLAN 37 37 38 38 USB20_P8 23 BT
+3V_WLAN 39 39 40 40
41 41 42 42
43 43 44 44
45 45 46 46
R16 47 48
E51_TXD_R 47 48
37,38 E51_TXD 10_0402_5%2 49 49 50 50
1 2 E51_RXD_R 51 52
37,38 E51_RXD 51 52
0_0402_5%
R17 53 54 BT_CTRL 1 R327 2 E51_RXD_R
GND1 GND2 1K_0402_5%
Debug card using
FOX_AS0B226-S40N-7F For isolate Intel Rainbow Peak and
Compal Debug Card.

USB Sleep & Charge: MAX14566B

3
Auto-Mode CB
SLP_CHG#
CEN#
SLP_CHG_M3
STATUS IR Emitter Connector
3

Mode3 0 0 AUTO MODE

Force Dedicated charger mode
0 1 (MODE3)
Pass-Through (USB) Mode:
+5VALW 2.5A +USB_VCCB 1 X Connect DP/DM to TDP/TDM
U15 W=60mils
1 8 C400
GND VOUT 0.1U_0402_16V4Z
2 VIN VOUT 7
3 6 3D@ JIR @
VIN VOUT +IR_VCC
35,37 USB_CHG_EN# 4 EN FLG 5 USB_OC1# 23,35,37 +3VS 2 3D@ 1 1 1
R262 0_0603_5% EC_SMB_CK2 2
9,13,37,38,39 EC_SMB_CK2 2
RT9715BGS_SO8 1 EC_SMB_DA2 3
9,13,37,38,39 EC_SMB_DA2 3
C383 STEREO_SYNC 4
13 STEREO_SYNC 4
4.7U_0805_10V4Z 5
@ 5
6 6
2
7 GND
8 GND
ACES_87213-0600G_6P

4 4
U5
24 SLP_CHG_M3 SLP_CHG_M3 1 8 SLP_CHG# SLP_CHG# 24
USB20_DN1_R CEN CB USB20_N10
35 USB20_DN1_R 2 DM TDM 7 USB20_N10 23
USB20_DP1_R 3 6 USB20_P10
35 USB20_DP1_R DP TDP USB20_P10 23
4 GND VCC 5 +5VALW
9 GND 1
C892
MAX14566BEETA+_TDFN-EP8_2X2 0.1U_0402_16V7K Security Classification Compal Secret Data Compal Electronics, Inc.
2 Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 32 of 51
A B C D E F G H
 A B C D E

5 PCIE_FRX_C_LANTX_P0 CL1

CL2
1

1
2 0.1U_0402_16V7K PCIE_FRX_LANTX_P0

2 0.1U_0402_16V7K PCIE_FRX_LANTX_N0
22

23
UL1

HSOP
8111E@

LED3/EEDO
LED1/EESK
31
37
40 LL1
8111E@
www.qdzbwx.com +LAN_VDD10
+3V_LAN CL3 to CL6 close to Pin 27,39,47,48
CL7 to CL8 close to Pin 12,42

1 2
5 PCIE_FRX_C_LANTX_N0 HSON LED0 +LAN_REGOUT 1 2 CL3 0.1U_0402_16V4Z
17 30 RL2 2 1 10K_0402_5% 2.2UH +-5% NLC252018T-2R2J-N 1 2
5 PCIE_FTX_C_LANRX_P0 HSIP EECS/SCL
18 32 RL1 2 1 10K_0402_5% 1 1 CL4 0.1U_0402_16V4Z
5 PCIE_FTX_C_LANRX_N0 HSIN EEDI/SDA Layout Note: LL1 must be 1 2
within 200mil to Pin36, CL13 CL9 CL5 0.1U_0402_16V4Z
CLKREQ_LAN# 2 1 16 1 LAN_MDI0+ CL13,CL9 must be within 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 1 2
23 CLKREQ_LAN# CLKREQB MDIP0
RL19 0_0402_5% 2 LAN_MDI0- 200mil to LL1 8111E@ 2 2 8111E@ CL6 0.1U_0402_16V4Z
APU_PCIE_RST# MDIN0 LAN_MDI1+
12,22,27,32 APU_PCIE_RST# 25 PERSTB MDIP1 4 1 2
5 LAN_MDI1- 8111E@ CL7 0.1U_0402_16V4Z
1 +3V_LAN CLK_LAN MDIN1 LAN_MDI2+ 1
22 CLK_LAN 19 REFCLK_P NC/MDIP2 7 1 2
CLK_LAN# 20 8 LAN_MDI2- 8111E@ CL8 0.1U_0402_16V4Z
22 CLK_LAN# REFCLK_N NC/MDIN2
10 LAN_MDI3+
RL24 2 @ NC/MDIP3
1 10K_0402_5% CLKREQ_LAN#
NC/MDIN3 11 LAN_MDI3-
LAN_X1 43
RL25 2 @ FCH_PCIE_WAKE# CKXTAL1
1 10K_0402_5%
LAN_X2 44 13 +LAN_VDD10 +LAN_EVDD10
CKXTAL2 DVDD10 +LAN_VDD10 +LAN_VDD10
29 CL19, CL20,CL21 close to pin 13,29,45, respectively
DVDD10
RTL8105E RTL8111E DVDD10 41 1 2 CL22 close to pin 3, respectively
FCH_PCIE_WAKE# 28 LL2 0_0603_5% CL23,CL24,CL25 close to pin 6,9,41, respectively
23,35 FCH_PCIE_WAKE# LANWAKEB
Pin14 NC NC 1 1
+3VS ISOLATE# 26 27 1 2
ISOLATEB DVDD33 +3V_LAN CL17
Pin15 NC 10K ohm PD 39 CL18 CL19 0.1U_0402_16V4Z
DVDD33 1U_0402_6.3V6K 0.1U_0402_16V4Z 1 2
Pin38 1K ohm Pull-high 2 2 CL20 0.1U_0402_16V4Z
14 NC/SMBCLK AVDD33 12 +3V_LAN
1

RL21 2 8111E@ 1 10K_0402_5% 15 42 1 2

RL22 1 NC/SMBDATA AVDD33
+3V_LAN 2 1K_0402_5% 38 GPO/SMBALERT AVDD33 47 CL21 0.1U_0402_16V4Z
1K_0402_5% 48 Close to Pin 21 1 2
RL6 AVDD33 8111E@ CL22 0.1U_0402_16V4Z
@ ENSWREG 33 1 2
2

ENSWREG 8111E@ CL23 0.1U_0402_16V4Z

EVDD10 21 +LAN_EVDD10
ISOLATE# 1 2 WOL_EN 34 +3V_LAN +LAN_VDDREG 1 2
+LAN_VDDREG VDDREG
RL433 0_0402_5% 35 3 +LAN_VDD10 8111E@ CL24 0.1U_0402_16V4Z
VDDREG AVDD10
AVDD10 6 1 2 1 2
9 8111E@ LL3 0_0603_5% 1 1 8111E@ CL25 0.1U_0402_16V4Z
AVDD10
1 2 46 RSET AVDD10 45
RL7 Sx Enable Sx Disable S0 RL5 2.49K_0402_1% CL28 CL29
15K_0402_5% Wake up Wake up 24 36 +LAN_REGOUT 4.7U_0603_6.3V6K 0.1U_0402_16V4Z
GND REGOUT 8111E@ 2 2 8111E@
49 PGND 60 mils
WOL_EN LOW HIGH HIGH +3V_LAN
RTL8111E-GR-VL_QFN48_6X6
2 2
SA00004LR00

1
CL684
10U_0805_10V6K
+3VALW TO +3V_LAN YL1 2
RTL8105E-VC RTL8105E-VC
LAN_X1 1 2 LAN_X2 +3V_LAN
+3VALW
RTL8111E-VB
25MHZ_20PF_7A25000012
PWM Mode LDO Mode

1
+3VALW RL4 0 ohm NC
1 1
CL26 CL27 RL4 (Pull High) FOR EMI ISN TEST DEMAND.
27P_0402_50V8J 27P_0402_50V8J 0_0402_5%
1

2 8111E@ NC 0 ohm
RL147 CL483 Vgs=-4.5V,Id=3A,Rds<97mohm 2 2 RL23 (Pull Down)

2
100K_0402_5% @ ENSWREG
@ 0.1U_0402_16V7K
2

1
1
2

S
@RL432
@ RL432 @ QL51 PJ29 RL23
2

G
1 2 2 JUMP_43X79 0_0402_5%
37 WOL_EN
@ 8105E@
+3V_LAN
1

47K_0402_5% 2 AO3413_SOT23 D
1

2
@
1

CL482
0.01U_0402_25V7K
1
1 SP050006W00

CL681
1
CL682
1U_0402_6.3V6K
UL3 8105E@ LAN Conn.
4.7U_0805_10V4Z 2 LAN_MDI0+ RJ45_MIDI0+
1 TD+ TX+ 16
@ 2 LAN_MDI0- RJ45_MIDI0- JLAN
2 TD- TX- 15
3 3
3 CT CT 14
4 13 RJ45_MIDI3- 8
NC NC PR4-
5 NC NC 12
6 11 RJ45_MIDI3+ 7
+3V_LAN rising time (10%~90%) need > 1ms and <100ms. LAN_MDI1+ 7
CT CT
10 RJ45_MIDI1+ PR4+
LAN_MDI1- RD+ RX+ RJ45_MIDI1- RJ45_MIDI1-
8 RD- RX- 9 6 PR2-
RJ45_MIDI2- 5
10/100M transformer_HD245 PR3-
RJ45_MIDI2+ 4 PR3+

1
UL4 8111E@ RJ45_MIDI1+ 3
CL39 1000P_0402_50V7K PR2+ DL1

1
1 24 2 1 1 8111E@ 2 RJ45_MIDI0- 2 AZC199-02SPR7G_SOT23-3
LAN_MDI3- TCT1 MCT1 8111E@ RL11 75_0402_1% RJ45_MIDI3- PR1-
For P/N and footprint 2 TD1+ MX1+ 23

3
LAN_MDI3+ 3 22 RJ45_MIDI3+ RJ45_MIDI0+ 1
Please place them to ISPD page TD1- MX1- CL40 1000P_0402_50V7K PR1+

3
4 TCT2 MCT2 21 2 1 1 8111E@ 2 SHLD1 9
LAN_MDI2- 5 20 8111E@ RL12 75_0402_1% RJ45_MIDI2-
UL1 8105E@ LAN_MDI2+ TD2+ MX2+ RJ45_MIDI2+
6 TD2- MX2- 19 SHLD2 10
CL41 1000P_0402_50V7K

3
7 TCT3 MCT3 18 2 1 1 2
LAN_MDI1- 8 17 RL13 75_0402_1% RJ45_MIDI1- SANTA_130451-D

3
LAN_MDI1+ TD3+ MX3+ RJ45_MIDI1+ @
9 TD3- MX3- 16
CL42 1000P_0402_50V7K AZC199-02SPR7G_SOT23-3

1
RTL8105E-VL-CGT 10 15 2 1 1 2 DL2
LAN_MDI0- TCT4 MCT4 RL15 75_0402_1% RJ45_MIDI0-
11 14

1
LAN_MDI0+ TD4+ MX4+ RJ45_MIDI0+
SA00003PO30 12 TD4- MX4- 13

RJ45_GND 1 2 LANGND
1 1 CL36 1000P_1808_3KV7K 1 1
@ SUPERWORLD_SWG150401 CL37 CL38
4 CL35 CL34 @ 4
0.1U_0402_25V6 0.1U_0402_25V6 SP050006800 220P_0402_50V6K 4.7U_0603_6.3V6K
2 2 2 2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 33 of 51
A B C D E
 5 4 3 2 1

+1.8VS_OUT CC3 close to pin 5

CC2 close to CC3
CC1 is near CC3
www.qdzbwx.com D3E mode +3VS

1
20mil +3VS
RC19

1000P_0402_50V7K
0.22U_0402_6.3V6K

0.1U_0402_16V4Z
1 1 1 1 10K_0402_5%

2
10U_0805_10V6K

G
CC1 CC2 CC3 CC4

2
CC4 close to pin 10 23 CR_CPPE# 1 3 CPPE#
2 2 2 2

S
QC1 2N7002_SOT23-3

D JMB389C RC6 0_0402_5%

SD_CD#
D
24 CR_WAKE# 1 2
+3VS
UC1 +3VS
place near pin 19,20 and 44 +3VS 2 @ 1
CLK_CR# 3 5 1 2 RC18 10K_0402_5%
22 CLK_CR# CLK_CR APCLKN APVDD CC5 0.1U_0402_16V4Z
22 CLK_CR 4 APCLKP APV18 10 40mil 2
NC/TAV33 36 1 2
PCIE_MTX_C_CRRX_N2 9 CC6 0.1U_0402_16V4Z CC12
22 PCIE_MTX_C_CRRX_N2 PCIE_MTX_C_CRRX_P2 APRXN
22 PCIE_MTX_C_CRRX_P2 8 APRXP DV33 19 1 2 0.1U_0402_16V4Z
CC7 0.1U_0402_16V4Z 1
DV33 20
22 PCIE_MRX_C_CRTX_N2 CC8 1 2 0.1U_0402_16V7K PCIE_MRX_CRTX_N2 11 44
CC9 0.1U_0402_16V7K PCIE_MRX_CRTX_P2 12 APTXN DV33 +1.8VS_OUT
22 PCIE_MRX_C_CRTX_P2 1 2 APTXP DV18 18 20mil CC12 close to pin 36
DV18 37 Power On Strapping setting
2 1 APREXT 7
RC3 12K_0402_1% 12mil APREXT XD_SD_MS_D0
MDIO0 48 2 1 Description
47 XD_SD_MS_D1 CC10 CC11 Pin name
+SDV33_18 MDIO1 XD_SD_MS_D2 10U_0805_10V6K
2 1 43 SDDV/MDIO4 MDIO2 46 High low
CC16 2.2U_0603_6.3V6K 39 45 XD_SD_MS_D3 CC11 close to pin18
TXIN/NC MDIO3 SDCMD_MSBS_XDWE# 1 2
CC16 close to pin43 MDIO6/4 41 For intenal LDO's usage
For internal LDO in SD3.0 42 SDCLK_MSCLK_XDCE# 0.22U_0402_6.3V6K MDIO7 on-board★ add-in card
MDIO5 XDWP#_SDWP#
24
JMB389 G/MDIO6
MDIO7 40 XD_CLE
29 XD_SD_D4 CC10 close to pin37 CR_LEDCON# CR_LEDCON#
FCH_PCIE_RST# MDIO8 XD_SD_D5
23,35 FCH_PCIE_RST# 1 XRSTN MDIO9 28 MDIO14 high active low active★
2 27 XD_SD_D6
+VCC_OUT XTEST MDIO10 XD_SD_D7
MDIO11 26
25 XD_RE#
CPPE# MDIO12 XD_RB#
13 CPPE_N MDIO13 23
2 1 XDWP#_SDWP# XD_CD# 14 22 XD_ALE
RC7 10K_0402_5% CR1_CD2N MDIO14
1 2 XD_RB# 30
C RC9 1K_0402_5% MS_CD# NC/SPI_SCK C
15 CR1_CD1N NC/SPI_CSN 33
SD_CD# 16 34
CR1_CD0N NC/SPI_SO
NC/SPI_SI 35
40 mils
+VCC_OUT 17 CR1_PCTLN
APGND 6
NC/GND 31
39 CR_LEDCON# CR_LEDCON# 21 32
CR1_LEDN NC/GND
NC/GND 38

JMB389-LGAZ0A_LQFP48_7X7

Add RC24 and RC17 close to UC1 for xD issue

SDCMD_MSBS_XDWE# 2 1 XDWE#
RC24 22_0402_5%

2 1 SDCMD_MSBS
RC17 0_0402_5%

5 in 1 Card Reader
Change RC17 to 0 ohm for SDXC performance low issue
B SD_CD# XD_CD# JREAD @ B
+VCC_OUT
40 mils MS-VCC 14 +VCC_OUT
1 1 33 15 SDCLK_MSCLK_XDCE#_R
CC22 CC23 XD_CD# XD-VCC MS-SCLK MS_CD#
34 XD-CD-SW MS-INS 17
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 1 XD_RB# 1 21 SDCMD_MSBS
@ CC17 CC18 XD_RE# XD-R/B MS-BS XD_SD_MS_D0
2 XD-RE MS-DATA0 19
2 2 SDCLK_MSCLK_XDCE#_R 3 XD_SD_MS_D1
10U_0805_10V6K 0.1U_0402_16V4Z XD_CLE 4
XD-CE MS-DATA1 20
18 XD_SD_MS_D2
Reserved for EMI,close to UC1.42
2 2 XD_ALE XD-CLE MS-DATA2 XD_SD_MS_D3
5 XD-ALE MS-DATA3 16
XDWE# 6
XDWP#_SDWP# XD-WE SDCLK_MSCLK_XDCE# SDCLK_MSCLK_XDCE#_R
7 XD-WP SD-VCC 23 +VCC_OUT 1 2
24 SDCLK_MSCLK_XDCE#_R RC11 0_0402_5%
XD_SD_MS_D0 SD-CLK SDCMD_MSBS
8 XD-D0 SD-CMD 12 1
XD_SD_MS_D1 9 25 XD_SD_MS_D0 CC13
XD_SD_MS_D2 XD-D1 SD-DAT0 XD_SD_MS_D1 22P_0402_50V8J
26 XD-D2 SD-DAT1 29
XD_SD_MS_D3 27 10 XD_SD_MS_D2 @
XD_SD_D4 XD-D3 SD-DAT2 XD_SD_MS_D3 2
28 XD-D4 SD-DAT3 11
XD_SD_D5 30 35 XDWP#_SDWP#
XD_SD_D6 XD-D5 SD-WP-SW SD_CD#
31 XD-D6 SD-CD-SW 36
XD_SD_D7 32 Change MDIO5 clock trace routing
XD-D7
13
for SDHC issue
4in1-GND
4in1-GND 22
4in1-GND 37
4in1-GND 38

TAITW_R015-211-LM-A_NR

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 34 of 51
5 4 3 2 1
 5 4 3 2 1

+1.5V to +1.05V Transfer

+1.5V
10U_0603_6.3V6M
CT2
+3V +1.5V
UT2 RENE@
+3V

1A
1 RT1
4.7K_0402_5%
2

RENE@
USB30_POK

+1.05V
Close to U102.D7
+3VA
Close to U102.P13
+3VA
U3TXDP1

1
1
RT4
LT1
1
@ 2
0_0402_5%

2 2
U3TXDP1_L USB30_RX0P www.qdzbwx.com
1
2
RT9
LT4
1
@ 1
0_0402_5%

2 2
U3RXDP1_R_L

32 USB20_DP1_R
USB20_DP1_R 4
1
RT5
LT2
4
2
0_0402_5%
@
3 3
USB20_DP1_L
1 5 VIN VOUT 3
RENE@ 9 4
VIN VOUT RENE@ 8P_0402_50V8D 8P_0402_50V8D USB20_DN1_R USB20_DN1_L
6 VCNTL 4 4 3 3 4 4 3 3 32 USB20_DN1_R 1 1 2 2
USB30_POK 7 2 2 1 CT6 CT9
2 POK FB RT2 1 1 1 @ 1 1 1 @ WCM-2012HS-670T _0805 WCM-2012HS-670T _0805 WCM-2012-900T_0805

1
0.1U_0402_16V7K 0.1U_0402_16V7K

10U_0603_6.3V6M
8 1 10K_0402_1% U3TXDN1 1 @ 2 U3TXDN1_L USB30_RX0N 1 @ 2 U3RXDN1_R_L 1 2
+3V EN GND CT4 CT7

CT3
1 RT6 0_0402_5% RT10 0_0402_5% RT7 0_0402_5%
APL5930KAI-TRG_SO8 RT3 RENE@ RENE@ RENE@ RENE@ RENE@
2 CT5 2 2 2 CT8 2 2
32.4K_0402_1%
RENE@ 0.01U_0402_25V7K 0.01U_0402_25V7K SM070001U00 SM070001U00 SM070000K00
Vout=0.8(1+10K/32.4K)

2
2
D 1.042 ~ 1.0469 ~ 1.0519V D
Spec: 0.9975 ~ 1.05 ~ 1.1025

Co-Layout with Hudson M3 internal USB3.0

+3VALW to +3V Transfer +3VALW
Place co-layout resistors close to UT1
+3VALW Follow Vendor recommend.

USB30_RX0N
23 USB30_RX0N
2

2 RENE@
RT37 RENE@ CT42 +3V +1.05V
100K_0402_5% CT41 0.1U_0402_16V4Z +3VA USB30_RX0P
23 USB30_RX0P
RENE@ 0.1U_0402_16V7K

3
1 S
1

G
1 RENE@ 2 2 QT1 1 2 U3TXDN1
23 USB30_TX0N
RT38 47K_0402_5% 2 AO3413_SOT23 CT33 0.1U_0402_16V7K
CT43 D RENE@
1
1

RENE@ D 0.01U_0402_25V7K
2 RENE@ 1 2 U3TXDP1
37,40,45 SYSON 1 23 USB30_TX0P
G CT32 0.1U_0402_16V7K
+3V
QT2 S 2N7002_SOT23-3 RENE@

D10

H11
E11
E12

K11
K12

P13
3

F13
F14

L10

L13
L14
G3
G4

N4
N5
N6

C4
C5
C6
C7
D5

C8
C9
D8
D9

H3
H4

D7
UT1

P3

E3
E4
F3

L9

L5

L8
+3V & +1.05V has power sequence timing:
0.1*VDD(+3V) ~ 0.9*VDD(+1.05V) < 100ms

VDD33
VDD33
VDD33

VDD33
VDD33
VDD33

VDD33
VDD33

VDD33
VDD33

VDD33
VDD33
VDD33
VDD33

VDD10
VDD10
VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

VDD10
VDD10

VDD10
VDD10

VDD10
VDD10
VDD10

VDD10
VDD10
VDD10
VDD10

U3AVDO33

U2AVDD10
CLK_USB30 B2
22 CLK_USB30 PECLKP +USB_VCCB
CLK_USB30# B1
+3V +3VA 22 CLK_USB30# PECLKN
RENE@ +3V:200mA B6 W=80mils
U3TXDP2
22 PCIE_MRX_C_USBTX_P1
CT29 2 1 0.1U_0402_16V7K PCIE_MRX_USBTX_P1 D2 PETXP
22 PCIE_MRX_C_USBTX_N1
CT30 2 1 0.1U_0402_16V7K PCIE_MRX_USBTX_N1 D1 PETXN +1.05V:800mA U3TXDN2 A6 4.7U_0805_10V4Z 0.1U_0402_16V4Z
U2DM2 N8 1
LT3 RENE@ PCIE_MTX_C_USBRX_P1 F2 1 1 1
22 PCIE_MTX_C_USBRX_P1 PERXP +
1 2 PCIE_MTX_C_USBRX_N1 F1 P8 CT26 CT31 CT27 CT28
22 PCIE_MTX_C_USBRX_N1 PERXN U2DP2
C BLM18AG601SN1D_2P B8 C
RENE@ U3RXDP2
1 2 2 2 2
U3RXDN2 A8
CT25
10U_0603_6.3V6M RENE@ FCH_PCIE_RST# H2 220U_6.3V_M_R15 1000P_0402_50V7K
23,34 FCH_PCIE_RST# PERSTB
RENE@ 2 RT12 10_0402_5% 2 USB30_WAKE# K1 G14 OCI2# 1 RT13 2 10K_0402_5% +3V
23,33 FCH_PCIE_WAKE# PEWAKEB OCI2B
CLKREQ_USB30#_R K2 H13 OCL1# RENE@
RT15 PECREQB OCI1B
+3V 1 RENE@ 2 10K_0402_5%
RT16 1 @ 2 100_0402_1% J2
RT17 RENE@ AUXDET
+3V 1 2 10K_0402_5% J1 PSEL PPON2 H14 JUSB30 @
USB30_SMI_R H1 J14 USB30PWRON 1 @ 2 U3TXDP1_L 9
SMI PPON1 USB_CHG_EN# 32,37 SSTX+
USB30_SMI#_IC 0_0402_5% 1 RT18 2 USB30_SMI#_R P4 RT11 0_0402_5% +USB_VCCB 1
RENE@ SMIB U3TXDN1_L VBUS
UPD720200A: 8 SSTX-
+1.05V RT391 RENE@ 2 10K_0402_5% USB20_DP1_L
SMIB Low active +3V P5 PONRSTB U3TX_C_DP1
3 D+ W=80mils
U3TXDP1 B10 T51 7 GND
RENE@ RENE@ RENE@ RENE@ RENE@ 1SS355TE-17_SOD323-2 USB20_DN1_L 2 10
RENE@ RENE@ RENE@ RENE@ SPI_CLK_USB U3TX_C_DN1 U3RXDP1_R_L D- GND
1 2 M2 A10 T52 6 11
RENE@ 1 2 DT3 SPISCK U3TXDN1 SSRX+ GND
1U_0402_6.3V6K

SPI_CS_USB# N2 N10 U2D_DN1_N T53 4 12

SPISCB U2DM1 GND GND
CT16 0.1U_0402_16V7K

CT17 0.01U_0402_25V7K

CT18 0.1U_0402_16V7K

CT19 0.01U_0402_25V7K

CT20 0.01U_0402_25V7K

CT21 0.1U_0402_16V7K

CT22 0.01U_0402_25V7K

CT23 0.01U_0402_25V7K

CT24 0.01U_0402_25V7K

1 2 1 2 2 1 2 2 2 1 SPI_SI_USB N1 U3RXDN1_R_L 5 13
USB30_SMI#_IC SPI_SO_USB SPISI U2D_DP1_N SSRX- GND
For UPD720200: M1 SPISO U2DP1 P10 T54
CT44

SMI high active B12 U3RXDP1_R T55 LOTES_AUSB0003-P001C

U3RXDP1
1

2 1 2 1 1 2 1 1 1 D 2 RENE@ U3RXDN1_R
K13 GND U3RXDN1 A12 T56
Q57 2 1 @ 2 USB30_SMI_R K14 GND
@ G RT21 0_0402_5% J13 GND
S 2N7002_SOT23-3
3

1 @ 2 USB30_SMI#_R
RT40 0_0402_5% P12 RT22 1 RENE@ 2 1.6K_0402_1%
RREF
U2AVSS N12
C14 GND
U2PVSS N11
DT5 @
+3V D6 U3TXDP1_L 1 1 109 U3TXDP1_L
USB30_XT1 U3AVSS
N14 XT1 DT4
RENE@ RENE@ RENE@ USB30_XT2 M14 @ U3TXDN1_L 2 2 98 U3TXDN1_L
RENE@ RENE@ RENE@ XT2 USB20_DP1_L 2 2
1 U3RXDP1_R_L 4 4 77 U3RXDP1_R_L
1
1
CT10 0.01U_0402_25V7K

CT11 0.01U_0402_25V7K

CT12 0.01U_0402_25V7K

CT13 0.01U_0402_25V7K

CT14 0.1U_0402_16V7K

CT15 0.01U_0402_25V7K

2 2 2 2 1 2 USB20_DN1_L 3
B
RT26 3 U3RXDN1_R_L 5 5 66 U3RXDN1_R_L B
P6
100_0402_5% CSEL CSEL=0：24MHz XTAL AZC199-02SPR7G_SOT23-3
RENE@ 3 3
1 1 1 1 2 1 RENE@ CSEL=1：48MHz Clock P14
2

YT1 RENE@ GND 8

A1 GND GND P11
2

2
0_0402_5%

0_0402_5%

1 2 A2 GND GND P9
RT28 RT29 A3 P7 YSCLAMP0524P_SLP2510P8-10-9
24MHZ_12PF_X5H024000DC1H GND GND
A4 GND GND P2
A5 GND GND P1 Change ESD Diode for EMI request
2

12P_0402_50V8J

12P_0402_50V8J

1 1 A7 N13
1

GND GND
0_0402_5%

RT30 CT37 CT38 @ A9 N9

@ GND GND
A11 GND GND N7
RENE@ RENE@ A13 N3
2 2 GND GND +3V
A14 M13
1

GND GND
B3 GND GND M12
+3V B4 M11
GND GND

2
B5 GND GND M10
B7 M9 RT45
GND GND 10K_0402_5%
B9 GND GND M8
B11 M7 RENE@
GND GND DT1
B13 M6

1
GND GND CLKREQ_USB30#_R
B14 GND GND M5 1 2 CLKREQ_USB30# 22
Place as close as possibile to C1
C2
GND GND M4
M3 RB751V40_SC76-2
GND GND
UT1.N14 and UT1.M14 C3 GND GND L12 RENE@
+3V
C10 GND GND L11
C11 L7 1 @ 2
GND GND RT8 0_0402_5%
GND L6

10K_0402_5%
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+3V 2 RT43 1

5
RENE@ QT3B
C12
C13
D3
D4
D11
D12
D13
D14
E1
E2
E13
E14
F4
F6
F7
F8
F9
F11
F12
G1
G2
G6
G7
G8
G9
G11
G12
G13
H6
H7
H8
H9
H12
J3
J4
J6
J7
J8
J9
J11
J12
K3
K4
L1
L2
L3
L4

USB30_SMI#_IC 4 3 USB30_SMI# 23

2
+3V 2N7002DW-T/R7_SOT363-6 QT3A
RENE@
A OCL1# 1 6 USB_OC1# 23,32,37 A
UPD720200AF1-DAP-A
2

10K_0402_5% 2N7002DW-T/R7_SOT363-6
RT32 RT33 +3V 2 RT44 1 RENE@
47K_0402_5% 10K_0402_5% Close to UT1.M2 RENE@
RENE@ RENE@ 35mA
1

SPI_CLK_USB 1 RT34 2
UT4 RENE@ CT39 0_0402_5%
SPI_CS_USB# 1 8 RENE@ 1 2 0.1U_0402_16V7K @ 2
SPI_SO_USB CS# VCC
2 7 1 RT35 210K_0402_5% RENE@
3
SO
WP#
HOLD#
SCLK 6 SPI_CLK_USB_R
SPI_SI_USB
CT40 Security Classification Compal Secret Data Compal Electronics, Inc.
4 GND SI 5
1
0.1U_0402_16V7K Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

MX25L5121EMC-20G SOP 8P
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
SPI_CLK_USB_R 1 RT36 2 SPI_CLK_USB Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
0_0402_5% Custom B
RENE@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 35 of 51
5 4 3 2 1
 5 4 3 2 1

+PVDD 600 mA 0.1U_0402_16V4Z

CA57
1
CA56
1
2
RA2

0_0603_5%
1 0.1U_0402_16V4Z

CA44
1 1
+5VALW
CA43
www.qdzbwx.com
Speaker Connector
placement near Audio Codec
RA13
SPKL+ 2 1 SPK_L1
0_0603_5% 1
RA20 2 2 2 2
+3VS 2 1 0.1U_0402_16V4Z +DVDD_IO 10U_0805_10V6K 10U_0805_10V6K CA19 DA7
FBMH1608HM601-T @ 10U_0805_10V6K 2 2
2 CA24
1 1 place close to chip 1
CA2 CA1 1 1U_0402_6.3V6K 3
@
10U_0805_10V6K +3VS_DVDD CA20 1 PESD5V0U2BT_SOT23-3
D place close to chip 2 2
D
RA14 @ 10U_0805_10V6K JSPK
SPKL- 2 SPK_L2 SPK_L1
1 Remove relates to +5VALW sch 2 1 1 1
RA1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0_0603_5% SPK_L2 2
CA61 RA15 SPK_R1 2
+3VS 2 1 35 mA 3 3
FBMH1608HM601-T +AVDD SPKR+ 2 1 SPK_R1 SPK_R2 4
1 1 2 4
0_0603_5% 1
CA8 CA7 DA6 ACES_85204-0400N
RA3 CA25 2 @
10U_0805_10V6K 2 2 68 mA 10U_0805_10V6K 0.1U_0402_16V4Z 2 1 +5VALW @ 10U_0805_10V6K 2 1
0_0603_5% 2 CA27 3
1 1U_0402_6.3V6K
@ PESD5V0U2BT_SOT23-3

39

46

25

38
1 1 1 1

9
UA1 CA3 CA4 CA5 CA6 CA26 1
RA16 @ 10U_0805_10V6K

DVDD_IO

PVDD1

PVDD2

AVDD1

AVDD2
DVDD
SPKR- 2 SPK_R2
2 1
2 2 2 2 0_0603_5%
place close to chip
10U_0805_10V6K 0.1U_0402_16V4Z
1U_0402_6.3V6K CA9
MIC1_LINE1_R_L 1 2 23 40 SPKL+
Ext. Mic/LINE IN 24
LINE1_L SPK_OUT_L+
41 SPKL- Beep sound
MIC1_LINE1_R_R CA10 1 2
LINE1_R SPK_OUT_L- EC Beep RA7
14 45 SPKR+ 1 2
LINE2_L SPK_OUT_R+ 37 EC_BEEP#
1U_0402_6.3V6K 15 44 SPKR- 47K_0402_5%
4.7U_0805_10V4Z CA21 LINE2_R SPK_OUT_R-
MIC1_LINE1_R_L 2 1 21 32 RA4 75_0402_1%
MIC1_L HP_OUT_L HP_L 31
22 33
MIC1_LINE1_R_R 2 1
MIC1_R HP_OUT_R RA5 75_0402_1%
HP_R 31
PCI Beep RA8
CA13
16 1 2 1 2 MONO_IN
C 4.7U_0805_10V4Z CA22 MIC2_L 23 FCH_SPKR C
17 MIC2_R 47K_0402_5%
10 AZ_SYNC_HD 0.1U_0402_16V4Z
SYNC AZ_SYNC_HD 23
INT_MIC_DATA 2 6 AZ_BITCLK_HD
28 INT_MIC_DATA GPIO0/DMIC_DATA BCLK AZ_BITCLK_HD 23
Change value for Beep
INT_MIC_CLK_R 3 by A51 demand.
GPIO1/DMIC_CLK

2
5 AZ_SDOUT_HD AZ_SDOUT_HD 23 2
SDATA_OUT 2010/08/31 RA12 CA18
EC_MUTE# 4 8 AZ_SDIN0_HD_R 2 1 4.7K_0402_5% 100P_0402_50V8J
37 EC_MUTE# PD# SDATA_IN AZ_SDIN0_HD 23
RA6 33_0402_5%
1
For EMI Change to AGND for

1
AZ_RST_HD# 11 47 For EMI
23 AZ_RST_HD# RESET# EAPD high frequency noise issue
SPDIFO 48
RA44 CA11 1 2 MONO_IN 12 @ CA29
100K_0402_5% 0.01U_0402_25V7K CA12 100P_0402_50V8J PCBEEP AZ_BITCLK_HD 2
MONO_OUT 20 1 1 2 @
@ @ 10_0402_5% RA17
SENSE_A 13 SENSE A
29
10P_0402_50V8J Ext.MIC/LINE IN JACK
MIC2_VREFO
For EMI 18 SENSE B
30 +MIC1_VREFO_R CA23 10U_0805_10V6K RA33 2 RA31 1 +MIC1_VREFO_R
RA41 MIC1_VREFO_R 1K_0402_5% 2.2K_0402_5%
1 2 36 CBP LDO_CAP 28 1 2
INT_MIC_CLK_R CA15 MIC1_LINE1_R_R 2 1
28 INT_MIC_CLK MIC1_R 31
FBMA-10-100505-301T 2.2U_0603_6.3V6K 35 27 AC_VREF
CAM@ CBN VREF
1 +MIC1_VREFO_L 31 19 AC_JDREF2 RA9 1 20K_0402_1% MIC1_LINE1_R_L 2 1
MIC1_VREFO_L JDREF MIC1_L 31
CA28 1 1 1K_0402_5%
CA47 1 2 0.1U_0603_50V7K 27P_0402_50V8J 43 34 CPVEE 1 2 RA32 2 RA29 1 +MIC1_VREFO_L
@ PVSS2 CPVEE CA14 2.2U_0603_6.3V6K CA17 CA16 2.2K_0402_5%
42 PVSS1
B CA48 1 2 B
2 0.1U_0603_50V7K 49 DVSS2 AVSS1 26 2.2U_0603_6.3V6K
2 2 @
7 DVSS1 AVSS2 37
CA49 1 2 0.1U_0603_50V7K 0.1U_0402_16V4Z
+5VALW ALC269Q-VB5-GR _QFN48_7X7
CA50 1 2 0.1U_0603_50V7K place close to chip MIC_SENSE
DGND AGND

6
2 1
RA18 10_0603_5% RA42 QA1A
100K_0402_5% RA28 100K_0402_5%
@ 2N7002DW-T/R7_SOT363-6 2

EC_MUTE# RA22 2 1 4.7K_0402_5%

1
RA43 100K_0402_5%
Sense Pin Impedance Codec Signals Function +3VL
place close to chip
39.2K PORT-I (PIN 32, 33) Headphone out
37 SM_SENSE#
MIC_SENSE 2 1 SENSE_A

3
20K PORT-B (PIN 21, 22) Ext. MIC RA10 20K_0402_1%
SENSE A QA1B

10K PORT-C (PIN 23, 24) 2N7002DW-T/R7_SOT363-6

5 BACK_SENSE 31

31 NBA_PLUG

4
A A
5.1K (PIN 48) RA21 39.2K_0402_1%

39.2K PORT-E (PIN 14, 15)

SENSE B 20K PORT-F (PIN 16, 17)

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

10K PORT-H (PIN 20) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 36 of 51
5 4 3 2 1
 5 4 3 2 1

C436
1
0.1U_0402_16V4Z
1
C437
1
0.1U_0402_16V4Z

C438
1 2
C439 C440
2
C441
+3VL
+3VL

C442
1 2
www.qdzbwx.com BATT_TEMPA 1
C445
2
100P_0402_50V8J
For EMI 0.1U_0402_16V4Z 1000P_0402_50V7K 0.1U_0402_16V4Z ACIN_D 1 2
2 2 2 2 1 1 C446 100P_0402_50V8J

111
125
0.1U_0402_16V4Z 1000P_0402_50V7K

22
33
96

67
9
CLK_PCI_EC U19 KB930@

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
1
R377
10_0402_5%
@ GATEA20 1 21 KB_LED
23 GATEA20 GATEA20/GPIO00 PWM0/GPIO0F KB_LED 38
KB_RST# 2 23 EC_BEEP#
23 KB_RST# EC_BEEP# 36
2
D KBRST#/GPIO01 BEEP#/PWM1/GPIO10 D
1 SERIRQ 3 PWM Output 26
22,38 SERIRQ SERIRQ# FANPWM0/GPIO12 FANPWM 5
C443 LPC_FRAME# 4 27 ACOFF
22,38 LPC_FRAME# LPC_FRAME#/LFRAME# ACOFF/FANPWM1/GPIO13 ACOFF 43
22P_0402_50V8J LPC_AD3 5
22,38 LPC_AD3 LPC_AD3/LAD3
@ LPC_AD2 7
2 22,38 LPC_AD2 LPC_AD2/LAD2
LPC_AD1 8 63 BATT_TEMPA
22,38 LPC_AD1 LPC_AD1/LAD1 BATT_TEMP/AD0/GPI38 BATT_TEMPA 42
LPC_AD0 10 64 USB_OC3# 23
22,38 LPC_AD0 LPC_AD0/LAD0 BATT_OVP/AD1/GPI39
LPC & MISC 65 ADP_I
ADP_I/AD2/GPI3A ADP_I 42,43
CLK_PCI_EC 12 66 ADP_V
22,25 CLK_PCI_EC CLK_PCI_EC/PCICLK AD3/GPI3B ADP_V 43
LPC_RST# 13 AD Input 75
22,38 LPC_RST# PCIRST#/GPIO05 AD4/GPI42 +3VL
ECRST# 37 76 HDPACT
+3VL R378 EC_SCI# EC_RST#/ECRST# AD5/GPI43 HDPACT 38
23 EC_SCI# 20 EC_SCI#/GPIO0E
47K_0402_5% HDPLOCK 38 LID_SW# 2 1
38 HDPLOCK CLKRUN#/GPIO1D
2 1 ECRST# 68 R456 47K_0402_5%
DAC_BRIG/DA0/GPO3C
EN_DFAN1/DA1/GPO3D 70
2 1 DA Output 71 IREF CEC_INT# 2 1
IREF/DA2/GPO3E IREF 43
C444 0.1U_0402_16V4Z KSI0 55 72 CHGVADJ R53 100K_0402_5%
KSI0/GPIO30 DA3/GPO3F CHGVADJ 43
KSI1 56
KSI2 KSI1/GPIO31 CAP_INT# @
57 KSI2/GPIO32 1 2
KSI3 58 83 EC_MUTE# R172 4.7K_0402_5%
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_MUTE# 36
Reserve for ESD test KSI4 59 84 USB_EN#
KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B USB_EN# 31
KSI5 60 85 CAP_INT# +5VS
@ KSI6 KSI5/GPIO35 CAP_INT#/PSCLK2/GPIO4C H_PROCHOT# CAP_INT# 39
61 KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D 86 H_PROCHOT# 7,42,49
1 2 EC_ON KSI7 62 87 TP_CLK
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_CLK 39
C20 22P_0402_50V8J KSO0 39 88 TP_DATA TP_CLK 1 2
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 39
@ KSO1 40 R379 4.7K_0402_5%
EC_RSMRST# KSO2 KSO1/GPIO21 TP_DATA
1 2 41 KSO2/GPIO22 1 2
C21 22P_0402_50V8J KSO3 42 97 VGATE R381 4.7K_0402_5%
KSO3/GPIO23 SDICS#/GPXIOA00 VGATE 49
@ KSO4 43 98 WOL_EN
KSO4/GPIO24 WOL_EN/SDICLK/GPXIOA01 WOL_EN 33
KB_RST# KSO5 SYSON
1
C229
2
22P_0402_50V8J KSO6
44 KSO5/GPIO25 Int. K/B ME_EN/SDIMOSI/GPXIOA02 99
LID_SW#
1
R56
2
4.7K_0402_5%
45 KSO6/GPIO26 Matrix LID_SW#/GPXIOD00 109 LID_SW# 39
@ KSO7 46 SPI Device I/F
LPC_RST# KSO8 KSO7/GPIO27
1 2 47 KSO8/GPIO28
C232 22P_0402_50V8J KSO9 48 119 EC_SI_SPI_SO
C KSO9/GPIO29 SPIDI/MISO EC_SI_SPI_SO 38 C
KSO10 49 120 EC_SO_SPI_SI
KSO10/GPIO2A SPIDO/MOSI EC_SO_SPI_SI 38
KSO11 50 SPI Flash ROM 126 EC_SPI_CLK Reserved for EMI
KSO12 KSO11/GPIO2B SPICLK/GPIO58 SPI_CS#
51 KSO12/GPIO2C SPICS# 128 SPI_CS# 38
KSI[0..7] KSO13 52
24,38,39 KSI[0..7] KSO13/GPIO2D
KSO14 53 KB930@
KSO[0..17] KSO15 KSO14/GPIO2E CIR_IN EC_SPI_CLK 2
38,39 KSO[0..17] 54 KSO15/GPIO2F GPIO40 73 CIR_IN 39 1 SPI_CLK 38
KSO16 81 74 USB_OC0#_R R161 0_0402_5%
KSO17 KSO16/GPIO48 H_PECI/GPIO41 FSTCHG
82 KSO17/GPIO49 GPIO FSTCHG/GPIO50 89 FSTCHG 43
90 BATT_FULL_LED#
BATT_CHG_LED#/GPIO52 BATT_FULL_LED# 39
RP7 91 CAPS_LED#
CAPS_LED#/GPIO53 CAPS_LED# 38
+3VL 1 8 EC_SMB_CK1 EC_SMB_CK1 77 92 BATT_CHG_LOW_LED#
30,42 EC_SMB_CK1 EC_SMB_CK1/SCL0/GPIO44 BATT_LOW_LED#/GPIO54 BATT_CHG_LOW_LED# 39
2 7 EC_SMB_DA1 EC_SMB_DA1 78 93 PWR_ON_LED#
30,42 EC_SMB_DA1 EC_SMB_DA1/SDA0/GPIO45 PWR_LED#/GPIO55 PWR_ON_LED# 39
+3VS 3 6 EC_SMB_CK2 EC_SMB_CK2 79 95 SYSON R341 330K_0402_5%
9,13,32,38,39 EC_SMB_CK2 EC_SMB_CK2/SCL1/GPIO46 SYSON/GPIO56 SYSON 35,40,45
4 5 EC_SMB_DA2 EC_SMB_DA2 80 121 VR_ON +3VL 1 2
9,13,32,38,39 EC_SMB_DA2 EC_SMB_DA2/SDA1/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 40,47,49
127 ACIN_D
2.2K_0804_8P4R_5% AC_IN/GPIO59 D21
SM Bus
ACIN_D 2 1 ACIN 13,23,39,43
SLP_S3# 6 100 EC_RSMRST#
23 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 23
SLP_S5# 14 101 EC_LID_OUT# RB751V40_SC76-2
23 SLP_S5# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 EC_LID_OUT# 23
R1442 EC_SMI# 15 102 EC_ON
23 EC_SMI# EC_SMI#/GPIO08 EC_ON/GPXIOA05 EC_ON 24,39
1 2 USB_CHG_EN#_R 16 103 TP_LED
32,35 USB_CHG_EN# GPIO0A EC_SWI#/GPXIOA06 TP_LED 39
0_0402_5% ESB_CK 17 104 FCH_PWRGD
39 ESB_CK GPIO0B ICH_PWROK/GPXIOA07 FCH_PWRGD 23
ESB_DAT 18 GPIO 105 BKOFF#
39 ESB_DAT GPIO0C BKOFF#/GPXIOA08 BKOFF# 28
GPO RF_OFF#/GPXIOA09 HDPINT
INVT_PWM
19
25
SUS_PWR_DN_ACK/GPIO0D 106
107 CAP_RST#
HDPINT 38 For KB930 and KB9012
28 INVT_PWM INVT_PWM/PWM2/GPIO11 GPXIOA10 CAP_RST# 39
FAN_SPEED1 28 108 BACO_EN#
5 FAN_SPEED1 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 BACO_EN# 17,40
SM_SENSE# 29 KB9012@
36 SM_SENSE# FANFB1/GPIO15
E51_TXD 30 USB_OC0#_R 1 2
32,38 E51_TXD EC_TX/GPIO16
E51_RXD 31 110 CEC_INT# R362 0_0402_5%
32,38 E51_RXD EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01 CEC_INT# 30
@ ON/OFFBTN# 32 112 EC_ENBKL KB930@
39 ON/OFFBTN# ON_OFF/GPIO18 ENBKL/GPXIOD02 EC_ENBKL 28
1 2 SUSP# PWR_SUSP_LED# 34 114 USB_OC1# USB_OC0#_RR 1 2
39 PWR_SUSP_LED# SUSP_LED#/GPIO19 EAPD/GPXIOD03 USB_OC1# 23,32,35 USB_OC0# 23,31
C820 180P_0402_50V8J NUM_LED# 36 GPI EC_THERM#/GPXIOD04 115 R359 0_0402_5%
38 NUM_LED# NUM_LED#/GPIO1A
116 SUSP#
SUSP#/GPXIOD05 SUSP# 40
B 117 PBTN_OUT# B
PBTN_OUT#/GPXIOD06 PBTN_OUT# 23
118 USB_OC0#_RR
CRY1 R991 @ 0_0402_5% CRY1_EC EC_PME#/GPXIOD07
Close to EC 122 XCLK1
CRY2 R992 @ 0_0402_5% CRY2_EC 123 124 +EC_V18R
R990 0_0402_5% XCLK0 V18R
22,25 RTC_CLK
AGND

KB930@ SUSP# R423 2 1 10K_0402_5%

GND
GND
GND
GND
GND

C448
1

1 4.7U_0805_10V4Z VR_ON R462 2 1 10K_0402_5%

R266 KB930QF-A1_LQFP128_14X14
11
24
35
94
113

69

100K_0402_5% C1206
KB930@ 20P_0402_50V8J
2 KB930@
2

1 2 E51_TXD U19
R342 100K_0402_5% KB9012QF
KB9012@

R389
CRY1 1 2 CRY2

10M_0402_5%
@

1 1
@ @
1

A C449 C450 A
Y4
OSC

OSC

2 2
18P_0402_50V8J

18P_0402_50V8J

@
NC

NC
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title
32.768KHZ_12.5PF_Q13MC14610002
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 37 of 51
5 4 3 2 1
 1 2 3 4 5 6 7 8

SPI Flash (128KB)

+3VL
LPC Debug Port
Place JDB under DDR DIMM.
www.qdzbwx.com
18
17
16 16
G18
15 15
G17
14 14 E51_RXD_DB
13 13 1
E51_TXD_DB R23 1
2 E51_RXD 32,37
1 20mils 12 12 2 0_0402_5% E51_TXD 32,37
C451 U22 R24 0_0402_5%
0.1U_0402_16V4Z 11 11
8 VCC VSS 4 10 10 LPC_RST# 22,37
CLK_PCI_DDR
2 9 9 CLK_PCI_DDR 22,25
3 W 8 8 LPC_AD0 22,37
7 7 LPC_AD1 22,37
A 7 HOLD 6 6 LPC_AD2 22,37 A

SPI_CS# 5 5 LPC_AD3 22,37

37 SPI_CS# 1 S 22,37 SERIRQ T31 4 4 LPC_FRAME# 22,37
SPI_CLK 3 3 +3VS
37 SPI_CLK 6 C 2 2
Place T31 close to JDB. 1 1 +3VALW
EC_SO_SPI_SI 5 2 EC_SI_SPI_SO
37 EC_SO_SPI_SI D Q EC_SI_SPI_SO 37
@ JDB
W25X10BVSNIG_SO8 ACES_88512-1641

SPI_CLK 1 R394 2 1 2
10_0402_5% C454 10P_0402_50V8J

For EMI G-Sensor

Keyboard LED JBLG

1 1
2
+5VS_LED Place UG1 on TOP Layer
Q38 KBL@ 2
3 3
+5VS AO3413_SOT23 4 UG1 GSENSOR@ GSENSOR@
B
4 VOUTX CG1 0.033U_0402_16V7K B
GND 5 +3VS_HDP 2 Vdd1 Voutx 3 1 2
S

3 1 +5VS_LED 6 12 5 VOUTY CG2 1 2 0.033U_0402_16V7K

GND Vdd2 Vouty VOUTZ CG3
1 Voutz 7 1 2GSENSOR@
0.033U_0402_16V7K
1

ACES_85201-0405N GSENSOR@
R587 C836 @ +5VS GSENSOR@ +3VS_HDP SELF_TEST
G

4 10
2

10K_0402_5% 0.1U_0402_16V4Z DG1 RB751V40_SC76-2 ST NC1

6 PD NC2 11
KBL@ 2 @
1 2 8 FS NC3 14
2 2 15
2

CG12 UG3 GSENSOR@ NC4

For EMI NC5 16
1U_0402_6.3V6K CG13
Close to JKB GSENSOR@ 1 5 1U_0402_6.3V6K +3VS_HDP 9 1
VIN VOUT Rev GND1
1

D 1 1 GSENSOR@
GND2 13
2 Q52 KSO16 1 2 2
37 KB_LED GND
G 2N7002_SOT23-3 C401 100P_0402_50V8J CG14 TSH352TR LGA 16P
S KBL@ KSO17 1 2 3 4 2 1
3

C402 100P_0402_50V8J SHDN# BP

KSO2 1 2 @
C404 100P_0402_50V8J G9191-330T1U_SOT23-5 0.22U_0402_6.3V6K
KSO1 1 2
C405 100P_0402_50V8J
KSO0 1 2
C406 100P_0402_50V8J
KSO4 1 2
KEYBOARD CONN. KSO3
C407
1
100P_0402_50V8J
2
UG5

C408 100P_0402_50V8J 1 11 HDPACT 37

9,13,32,37,39 EC_SMB_CK2 P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01
KSO5 1 2

2
KSI[0..7] C409 100P_0402_50V8J
KSI[0..7] 24,37,39
KSO14 1 2 SELF_TEST 2 12 RG9
C KSO[0..17] C410 100P_0402_50V8J P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# 47K_0402_5% C
KSO[0..17] 37,39
KSO6 1 2 GSENSOR@
C411 100P_0402_50V8J +3VS_HDP RG3 2 1 3 13

1
KSO7 GSENSOR@ 4.7K_0402_5% RESET# P1_4/TXD0
1 2
JKB C412 100P_0402_50V8J
JKB34 1 2 +3VS KSO13 1 2 RG4 2 1GXOUT 4 14 HDPLOCK 37
34 KSO16 R372 300_0402_5% C413 100P_0402_50V8J GSENSOR@ 4.7K_0402_5% XOUT/P4_7 P1_3/KI3#/AN11/TZOUT
33 KSO8 RG10 47K_0402_5%
32 1 2
KSO17 C415 100P_0402_50V8J 5 15 VOUTZ 2 1
31 KSO9 VSS/AVSS P1_2/KI2#/AN10/CMP0_2 GSENSOR@
30 1 2
C416 100P_0402_50V8J
29 KSO2 KSO10 RG5 2
28 1 2 1GXIN 6 XIN/P4_6 P4_2/VREF 16 +3VS_HDP
KSO1 C417 100P_0402_50V8J GSENSOR@ 4.7K_0402_5%
27 KSO0 KSO11
26 1 2 1
KSO4 C418 100P_0402_50V8J 7 17 VOUTX CG6
25 KSO3 KSO12 VCC/AVCC P1_1/KI1#/AN9/CMP0_1 0.1U_0402_16V4Z
24 1 2
KSO5 C419 100P_0402_50V8J GSENSOR@
23 KSO14 KSO15 RG6 2
22 1 2 2 1 4.7K_0402_5% 8 MODE P1_0/KI0#/AN8/CMP0_0 18 VOUTY
KSO6 C420 100P_0402_50V8J GSENSOR@
21 KSO7 KSI7
20 1 2
KSO13 C421 100P_0402_50V8J RG7 2 1 1K_0402_5% 9 19
19 KSO8 KSI2 37 HDPINT GSENSOR@ P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0
18 1 2
KSO9 C422 100P_0402_50V8J
17 KSO10 KSI3
16 1 2 1 1 10 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 20 EC_SMB_DA2 9,13,32,37,39
KSO11 C423 100P_0402_50V8J CG8
15 KSO12 KSI4 CG7 GSENSOR@
14 1 2
KSO15 C424 100P_0402_50V8J 0.1U_0402_16V4Z 0.1U_0402_16V4Z R5F211B4D34SP GSENSOR@
13 KSI7 KSI0 GSENSOR@ 2 2
12 1 2
KSI2 C425 100P_0402_50V8J
D 11 D
KSI3 KSI5 1 2
10 KSI4 C427 100P_0402_50V8J
9 KSI0 KSI6
8 1 2
KSI5 C429 100P_0402_50V8J
7 KSI6 KSI1
6 1 2
KSI1 C431 100P_0402_50V8J
5
4
JKB4 2 1 +3VS CAPS_LED# 1 2
Security Classification Compal Secret Data Compal Electronics, Inc.
CAPS_LED# R376 300_0402_5% C433 100P_0402_50V8J 2011/01/06 2012/01/06 Title
3 CAPS_LED# 37
NUM_LED#
Issued Date Deciphered Date
1 2
2 NUM_LED#
NUM_LED# 37
C435 100P_0402_50V8J
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
1 Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
ACES_88170-3400 B
@
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 38 of 51
1 2 3 4 5 6 7 8
 5 4 3 2 1

Power Button
+3VL
Caps Sensor/Light Sensor Conn. Touchpad & Light Pipe Connector
www.qdzbwx.com

2
For debug R395 JCS @
+5VALW 1 1
100K_0402_5% +3VL 2
51_ON# 41 2
FBMA-11-100505-301T_0402 +3VS 3

1
ON/OFFBTN# L13 1 ESB_DAZ 3
ON/OFFBTN# 37 37 ESB_DAT 2 4 4

6
TOP side L14 1 2 ESB_CKZ 5
37 ESB_CK 5
1 Q7A FBMA-11-100505-301T_0402 CAP_INT# 6
37 CAP_INT# 6
C458 2N7002DW-T/R7_SOT363-6 CAP_RST# 7
37 CAP_RST# 7
0.1U_0402_25V6 2 8
24,37 EC_ON 9,13,32,37,38 EC_SMB_CK2 8
@ 9 JTPL @
9,13,32,37,38 EC_SMB_DA2 9

2
2
10 1

1
SW3 @ R396 10 +5VS 1
11 GND 37 TP_CLK 2 2
1 3 10K_0402_5% 12 GND 37 TP_DATA 3 3
D 4 D
P-TWO_161021-10021 4
BTM side 2 4 For EMI request 5

1
5

2
6 6
SMT1-05-A_4P @ TP_LED# 7
6
5

KSI6 7
PACDN042Y3R_SOT23-3 24,37,38 KSI6 8 8
JPOWER @ KSO0 9
D86 37,38 KSO0 9
G2 6 For EMI 10 10

3
G1 5 11

1
PWR_ON_LED# GND
4 4 @ R428 C260 @ Q7B
12 GND
3 3 ON/OFFBTN#
1
R22
2
390_0402_5%
+5VALW
ESB_DAZ P-TWO_161021-10021
2 2 1 2 1 2 37 TP_LED 5
1 1 100_0402_5% 100P_0402_50V8J 2N7002DW-T/R7_SOT363-6

4
ACES_85201-0405N D83 @ R427 C261 @
ON/OFFBTN# 2 ESB_CKZ 1 2 1 2
1
PWR_ON_LED# 3 100_0402_5% 100P_0402_50V8J

PESD5V2S2UT_SOT23-3

Screw Hole
B+

DC-IN LED ACIN 13,23,37,43

0.1U_0402_25V6
2 2 2 CPU VGA
C228 C227 C226
5

Q32B H1 H2 H3 H4 H5 H6 H15
0.1U_0402_25V6 H_4P9 H_4P2x4P7 H_4P2x4P7 H_4P2 H_2P9 H_2P9 H_2P9x3P4
DC_IN 1 1 1 @ @ @ @ @ @ @
3 4
Reserve for ESD request 0.1U_0402_25V6

1
2N7002DW-T/R7_SOT363-6
C Q32A in page24 C

+5VS +3VS
Reserve for EMI request
0.1U_0402_25V6
MINI CARD -- TV MINI CARD -- WLAN
2 2 2
C251 C247 C236
@ @ @ H10 H11 H12 H13 H8 H9 H30 H31
0.1U_0402_25V6 0.1U_0402_25V6 Close to H17 H_1P2 H_1P2 H_1P2 H_1P2 H_3P3 H_3P3 H_3P1x3P6N H_3P1N
1 1 1 @ @ @ @ @ @ @ @

HDD LED SATA_LED# 24

1
2

+5VALW B+
+3VS 2 R404 1 6 1
10K_0402_5% B+
5

Q9A 2 2
2N7002DW-T/R7_SOT363-6 C225 C224
HDD_LED# 3 4 0.1U_0402_25V6 @ @ H14 H26 H16 H17 H18 H19 H20 H21 H22
0.1U_0402_25V6 0.1U_0402_25V6 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0 H_3P0
Q9B 2N7002DW-T/R7_SOT363-6 1 1 @ @ @ @ @ @ @ @ @
2 2 2
1 @ 2 C235 C234 C233

1
R50 0_0402_5% @ @ @
0.1U_0402_25V6
1 1 1
0.1U_0402_25V6 H23 H24 H25 H27
H_3P0 H_3P0 H_3P0 H_7P5
Reserve for ESD request @ @ @ @

1
B
PCB Fedical Mark PAD B

FD1 FD2 FD3 FD4

LED/B Connector LOGO/B Connector @ @ @ @

1
WHPROR3@
+5VL
ISPD SA00004C790
2

Remove WIMAX_LED_GND#
R749
JLED @ 10K_0402_5%
+5VALW 1 UV1 WHPROR1@ ZZZ
1 JLOGO @
+5VS 2
1

2
3 3 +5VL 1 1
WL_BT_LED# CIR_IN
24 WL_BT_LED#
DC_IN
4
5
4
5
37 CIR_IN
+5VS
2
3
2
3
SA00004C780 DAZ0K600100
PWR_ON_LED# 6 4
37 PWR_ON_LED# 6 24 LOGO_LED 4
PWR_SUSP_LED# 7 +3VALW 5 216-0810005 A11 WHISTLER PRO PCB LA-7213P
37 PWR_SUSP_LED# 7 5
HDD_LED# 8 6
CR_LEDCON# 8 6
34 CR_LEDCON# 9 9 +3VL 7 7
BATT_FULL_LED# 10 8 U1 HUDM3R1@ PJP1 45@
37 BATT_FULL_LED# 10 37 LID_SW# 8
BATT_CHG_LOW_LED# 11 13 9
37 BATT_CHG_LOW_LED# 11 GND 9
12 12 GND 14 10 10
11
12
GND
GND
SA000043I60 DC30100AA00
ACES_85201-1205N
P-TWO_161021-10021 218-0755022 A13 HUDSON-M3 PJP1

A A

HUDM3R3@
SA000043I70

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 39 of 51
5 4 3 2 1
 A B C D E

+3VALW
+3VALW TO +3VS
+3VS Vgs=10V,Id=9A,Rds=18.5mohm +5VALW
+5VALW TO +5VS
+5VS
Vgs=10V,Id=9A,Rds=18.5mohm
www.qdzbwx.com +1.5V
+1.5V to +1.5VS
+1.5VS

4.7U_0805_10V4Z 4.7U_0805_10V4Z +5VS Vgs=10V,Id=9A,Rds=18.5mohm 4.7U_0805_10V4Z

1 1 1 1 1 1
Q29 C459 C460 Q30 C461 C462 Q31 C463 C464

470_0805_5%

470_0805_5%

470_0805_5%
8 D S 1 8 D S 1 For EMI 8 D S 1

2
7 2 7 2 1U_0402_6.3V6K 7 2
D S 2 2 R406 D S 2 2 R407 D S 2 2 R408

0.1U_0402_16V4Z

0.1U_0402_16V4Z
6 D S 3 6 D S 3 6 D S 3
5 D G 4 5 D G 4 2 2 5 D G 4
1U_0402_6.3V6K C822 C821 1U_0402_6.3V6K
1 SI4800BDY_SO8 1 R409 2 SI4800BDY_SO8 1 R410 2 SI4800BDY_SO8 1 R411 2 1
+VSB +VSB +VSB

3 1

3 1

3 1
47K_0402_5%

0.01U_0402_25V7K
47K_0402_5% @ @ 220K_0402_5%
0.022U_0402_25V7K
4.7U_0805_10V4Z

4.7U_0805_10V4Z

4.7U_0805_10V4Z
1 1 1 1 1 1

6
C466 1 1

0.1U_0402_25V6
C465 R412 Q10A C467 C468 R413 Q11A C469 C470 R414 Q12A
330K_0402_5% Q10B 200K_0402_5% Q11B 820K_0402_5% Q12B
2 2 SUSP 2 2 @ SUSP 2 2 SUSP
2 5 2 5 2 5
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
2

2
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

4
+1.1VS

+1.1VALW to +1.1VS +1.0VSG +1.8VSG +0.75VS +5VALW +5VALW

2
R417
+1.1VALW +1.1VS 470_0805_5% R475 R470 R477 R424 R422
470_0805_5% 470_0805_5% 470_0805_5% 100K_0402_5% 100K_0402_5%
Vgs=10V,Id=14.5A,Rds=6mohm 4.7U_0805_10V4Z VGA@ VGA@ VGA@

3 1
1 1

1
Q44 C476 C472 GPU_PWREN# 45 SUSP SUSP
8 D S 1

6
7 2 Q209B Q190B Q190A
D S

1
2 2 SUSP VGA@ VGA@ D Q189 Q6A
6 D S 3 5
5 4 2N7002DW-T/R7_SOT363-6 2 SUSP Q188A
D G 1U_0402_6.3V6K GPU_PWREN# G GPU_PWREN 2 VGA@ SUSP#
5 2 2 Q6B in page40

4
FDS6676AS_SO8 1 R415 2 +VSB S 2N7002_SOT23-3

3
220K_0402_5% 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6
4.7U_0805_10V4Z

1 1

1
1

6
0.1U_0402_25V6

2 C474 C477 R416 Q209A 2

820K_0402_5%
2 2 SUSP
2 1 2
2N7002DW-T/R7_SOT363-6 R385 0_0402_5%
2

1 +1.5V +1.2VS
1

@
0.1U_0402_25V6

C200

2
2 R478 +5VALW R479 +5VALW
Need to delay after 470_0805_5% 470_0805_5%
+3VS ramp up

2
3 1

3 1
R432 R448
100K_0402_5% 100K_0402_5%

Q210B Q211B
For +VGA_CORE power enable

1
5 SYSON# 5 VR_ON#
2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

6
NOBACO@
+3VS to +3VSG

4
1 2 Q210A Q211A
17,22 PXS_PWREN VGACORE_EN 48
R158 0_0402_5%
DIS@ 2 2
35,37,45 SYSON 37,47,49 VR_ON
37 SUSP# 1 2
R375 0_0402_5% 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6

1
BACO@
1 2 +3VS
17,37 BACO_EN# +3VALW
R380 0_0402_5%

+5VS_ODD
For GPU power enable
2 R433
2
C491 Vgs=-4.5V,Id=3A,Rds<97mohm
+5VS TO +5VS_ODD
3 100K_0402_5% 0.1U_0402_16V7K 3

2
PXS@ PXS@ PXS@

1
PXS_PWREN 1 2 1 R457
GPU_PWREN 46,48
1

3
S
R382 0_0402_5% R426 Q54
G R104 470_0805_5%
DIS@ PXS_PWREN# 1 2 2 0_0805_5%
SUSP# 1 2 DIS@

6 1
R384 0_0402_5% 47K_0402_5% AO3413_SOT23 D +3VSG
2

2
6

PXS@ PXS@
Q206A C492 Q53A
PXS@ PXS@ 0.01U_0402_25V7K
PXS_PWREN 1 ODD_PWR# +5VS
2 1 2
+1.5V to +1.5VSG 2N7002DW-T/R7_SOT363-6
C683
1 C684
1U_0402_6.3V6K 2N7002DW-T/R7_SOT363-6
1

1
+1.5V +1.5VSG 4.7U_0805_10V4Z PXS@ +5VALW
@ 2
Vgs=10V,Id=14.5A,Rds=6mohm 2
2

2
C471 Vgs=-4.5V,Id=3A,Rds<97mohm
1 1 R441 0.1U_0402_16V7K
Q43 VGA@ C478 C475 100K_0402_5%

2
1
470_0805_5%

8 VGA@ 4.7U_0805_10V4Z
D S 1
2

3
S
7 VGA@ R440 Q45 PJ28
S 2

2
1
D 2 2 R429 ODD_PWR# 1
G
6 D S 3 2 2 JUMP_43X79
5 VGA@ +3VSG
D G 4 @ +5VS_ODD

1
1U_0402_6.3V6K VGA@ 47K_0402_5% 2
D

1
FDS6676AS_SO8 1 R431 2 +VSB AO3413_SOT23
3 1

1
2

3
220K_0402_5% Q53B C217
4.7U_0805_10V4Z

1 1
1

6
0.1U_0402_25V6

R458 0.01U_0402_25V7K
C473 C481 R430 Q13A 470_0805_5% 1
1
VGA@ VGA@ 820K_0402_5% VGA@ Q13B PXS@ 5 1
2 2 24 ODD_PWR
VGA@ 2 VGA_PWRGD# 5 2N7002DW-T/R7_SOT363-6 2N7002DW-T/R7_SOT363-6 C680
3 1

2N7002DW-T/R7_SOT363-6 VGA@ C679 1U_0402_6.3V6K

2

4
4.7U_0805_10V4Z 2
1

4 @ 2 4
+5VALW Q206B
2N7002DW-T/R7_SOT363-6 5 PXS_PWREN#
R146 PXS@
1 VGA@ 2
4

100K_0402_5%
3

Security Classification Compal Secret Data Compal Electronics, Inc.

Q188B 2011/01/06 2012/01/06 Title
VGA@
Issued Date Deciphered Date
5
17,22,48 VGA_PWRGD
2N7002DW-T/R7_SOT363-6
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
4

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 40 of 51
A B C D E
 A B C D

www.qdzbwx.com 1 2

VIN @ PR1
@PR1
@ PJP1 PL1 1K_1206_5%
PF1 SMB3025500YA_2P @PD1
@ PD1
1 DC_IN_S1 1 2 DC_IN_S2 1 2 2 1 N3 1 2
+ VIN B+
2 10A_125V_451010MRL RLS4148_LL34-2 @ PR2
@PR2
+ 1K_1206_5%

1000P_0402_50V7K

1000P_0402_50V7K

100P_0402_50V8J
100P_0402_50V8J
- 3
1 2

1
1 1

PC4
PC1

PC2

PC3
- @ PR3
SINGA_2DW-0005-B03 1K_1206_5%

1
@PR4
@ PR4 @ PR5
100K_0402_1% 2.2M_0402_5% @ PR38
@PR38
1 2 2 1 511K_0402_1%
VL

2
N1

@PD2
@ PD2

8
RB715F_SOT323-3 @ PU2B
2 5

P
VIN 44 EN0 +
1 7 O
43 ACON 3 - 6 2 1

1
G
2
LM393DG_SO8 @ PR6
@PR6 @PR35
@ PR35

1
PD3 34K_0402_1% 255K_0402_1% @ PC14
@PC14

43

6251VREF
@ PR36
@PR36 1000P_0402_50V7K
RLS4148_LL34-2 @ PC13
@PC13 @ PR7
@PR7 150K_0402_1%

2
1000P_0402_50V7K 66.5K_0402_1%

2
1

2
@PC16
@ PC16
1000P_0402_50V7K

2
PR8 PR9
PQ4 68_1206_5% 68_1206_5% @PR39
@ PR39

1
D 47K_0402_1%
TP0610K-T1-E3_SOT23-3 @ PQ1 PACIN 43
2 2 1

2
PD4
SSM3K7002FU_SC70-3 G
2 1 N1 3 1
2
BATT+ VS S 2

3
RLS4148_LL34-2
1

1
1

PR10 PC6 N1

1
100K_0402_1% 0.22U_0603_25V7K PC5
2

0.1U_0603_25V7K

8
@PU2A
@ PU2A 2
2

2
+5VALWP
PR11 3

P
1 2 +
39 51_ON# 1 O
22K_0402_1% 2 @ PQ2
@PQ2
-

G
DTC115EUA_SC70-3

3
LM393DG_SO8

4
@ PJ702
@ PJ333 @ PJ332 2 2 1 1
+3VLP 2 2 1 1 +3VL +3VALWP 2 2 1 1 +3VALW JUMP_43X118
JUMP_43X39 JUMP_43X118
@ PJ703
(100mA,40mils ,Via NO.= 2) (5A,200mils ,Via NO.= 10)
+VGA_COREP 2 2 1 1 +VGA_CORE
OCP=7.7A
JUMP_43X118
@ PJ353 @ PJ352
3
(32.6A,1288mils ,Via NO.= 65) 3

VL 2 1 2 1
2 1
JUMP_43X39
+5VL +5VALWP 2 1 +5VALW OCP= 36.19A RTC Battery
JUMP_43X118
(5A,200mils ,Via NO.= 10) @ PJ152
OCP=7.9A 2 1 1
@ PJ72 @ PJ112
2
JUMP_43X118
- PBJ1 + PR13 PR17
560_0603_5% 560_0603_5%
+VSBP 2 2 1 1 +VSB +1.1VALWP 2 2 1 1 +1.1VALW 2 1 1 2 1 2 +RTCBATT +RTCBATT
@ PJ153
JUMP_43X39 JUMP_43X118 2
+1.5VP 2 1 1 +1.5V
(120mA,40mils ,Via NO.= 1) (5.3A,212mils ,Via NO.= 11) JUMP_43X118 @ MAXEL_ML1220T10
OCP=6.81A (DIS 20A, 800mils ,Via NO.= 40,
OCP=24.13A)
@ PJ252 @ PJ102
(UMA 8.5A, OCP=10.44A) SP093MX0000
+2.5VSP 2 2 1 1 +2.5VS +1.0VSGP 2 2 1 1 +1.0VSG
JUMP_43X39 JUMP_43X79
(3A,120mils ,Via NO.= 6)
ACIN
@ PJ182 @ PJ76
+1.8VSGP 2 1 +1.8VSG 2 1
Precharge detector
2 1 +0.75VSP 2 1 +0.75VS
JUMP_43X118 JUMP_43X79
Min. typ. Max.
(2.5A,100mils ,Via NO.= 5) (0.5A,40mils ,Via NO.= 1) H-->L 14.42V 14.74V 15.23V
4 L-->H 15.39V 15.88V 16.39V 4

@ PJ122
+1.2VSP 2 2 1 1 +1.2VS
JUMP_43X118

(6.5A,260mils ,Via NO.= 13)

OCP=8.55A
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 41 of 51
A B C D
 A B C D

www.qdzbwx.com
1 1

VMB
PL2
@ PJP2 PF2 SMB3025500YA_2P
1 BATT_S1 1 2 1 2
1 BATT+
2 2
3 15A_65V_451015MRL
3 BATT_P4
4 4
5 BATT_P5
5

1
10 6 EC_SMDA PC8
GND 6 PC7

1
EC_SMCA @ PC15
11
12
GND 7 7
8 PR14 .1U_0402_16V7K 1000P_0402_50V7K 0.01U_0402_25V7K PH1 under CPU botten side :

2
GND 8 1K_0402_1%
13 GND 9 9 CPU thermal protection at 90 degree C
SUYIN_200045MR009G171ZR Recovery at 56 degree C

2
PD6
Rset = 3 * Rtmh
1

PJSOT24C_SOT23-3 Rhyst = (Rset* Rtml) / (3*Rtml - Rset)

PD5 2
PJSOT24C_SOT23-3 1
3
PR16
Rtmh at 90C = 7.87K, Rtml at 56C = 26.1K
6.49K_0402_1%
Rset = 3 * 7.87K = 23.61K ==> 23.7K
2

2 1
+3VL
Rhyst = (23.7K * 26.1K) / (3 * 26.1K - 23.7K) = 11.33K ==> 11.3K
1

2 VL 2
PR19

1
1K_0402_1%
PR15
2
2

1
23.7K_0402_1%
PC9
PR20 PR21 BATT_TEMPA 37

2
100_0402_1% 0.1U_0603_25V7K
100_0402_1%

2
1

EC_SMB_DA1 30,37

1
PR18
11.3K_0402_1% ADP_I 37,43
PH1

1
PU1 100K_0402_1%_NCP15WF104F03RC
EC_SMB_CK1 30,37 +3VS 1 8 90W@ PR22

2
VCC TMSNS1

2
PR29 2 7 560_0402_1%
7,37,49 H_PROCHOT# GND RHYST1
100K_0402_1%

2
44 VS_ON 3 OT1 TMSNS2 6

1
D 65W@ PR22

1
PQ7 2 4 5 1 2 180_0402_1%
SSM3K7002FU_SC70-3 G OT2 RHYST2

2
S G718TM1U_SOT23-8 90W@ PR28 65W@ PR28

3
1.69K_0402_1% PR27 1.18K_0402_1%
10K_0402_1%

1
PQ5
TP0610K-T1-E3_SOT23-3

3 B+ 3 1 +VSBP 3
0.22U_0603_25V7K
100K_0402_1%
1

PC10
1

1
PR23

PC11 @
VL @ 0.1U_0603_25V7K
Adaptor protection
2

2
2

Adaptor Throttling point ADP_I Recovery point ADP_I

PR24
2

1 2 90W 113.5W 1.783V 86.4W 1.357V

PR25 22K_0402_1%
100K_0402_1% 65W 71.8W 1.5V 62.44W 1.3V
1

D
PR26
1 2 2 PQ6
44,46 POK
G SSM3K7002FU_SC70-3
0_0402_5%
S
3
1

@ PC12
.1U_0402_16V7K
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 42 of 51
A B C D
 A B C D

www.qdzbwx.com 75W@ PQ208

65W@ PQ208
AOS4435

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
AO4407A_SO8
1 8
65W@ PQ203 65W@ PR215 @ @ @ 2 7

1
PC207

PC208

PC209
AOS4435 0.02_2512_1% 3 6
5
B+ CHG_B+

2
PQ203 90W@ P2 PQ204 P3 PR215 90W@ PL201

4
AO4407A_SO8 AO4409L_SO8 0.015_2512_1% 1UH_PH041H-1R0MS_3.8A_20%
@ PQ209 AO4407A_SO8
VIN 8 1 1 8 1 4 2 1
7 2 2 7 1 8
6 3 3 6 2 3 CSIN 2 7
5 5 3 6

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
1 5 1

CSIP
VIN

1
PC231

PC232

PC233

4
2
@ PC211 PR236
1 2
VIN

2
1

5600P_0402_25V7K
200K_0402_1%

0.1U_0603_25V7K

1
1

2
6251VDD
PR210 LDO 5.075V PR226
47K_0402_1% PR212 PR237

2
ACSETIN

PC210
200K_0402_1% 191K_0402_1% 47K_0402_1% PD9

2.2U_0603_6.3V6K
2

PD201 ACOFF
1 2

1 1
1000P_0402_50V7K
PQ210 RB751V-40_SOD323-2 ACSETIN PR238

1
PC212
DTA144EUA_SC70-3 1SS355_SOD323-2 200K_0402_1%

1 1
3

1
2 1
1.26V VIN

1
PC217
2
PR228 PD10
PR227 14.3K_0402_1% PQ215
2 2 1 2

2
PR216 10_1206_5% DTC115EUA_SC70-3

2
10K_0402_1% 1SS355_SOD323-2

2
37 FSTCHG 2 1 PU200
1

1
PC218 PC222

3
1 24 DCIN 2 1 0.1U_0402_25V6
1

VDD DCIN
1

2
0.1U_0603_25V7K
PR213 PR217
2 2 23 ACPRN
PQ211 150K_0402_1% 100K_0402_1% ACSET ACPRN
DTC115EUA_SC70-3 PR229 20_0402_5%
2

2
6251_EN 3 22 1 2 CSON
EN CSON
6

1
D D
PC219
3

5
6
7
8
2 0.047U_0402_16V7K PACIN 2
G 4 21 1 2 CSOP PQ201 G

1
CELLS CSOP AO4466L_SO8 PQ216
PR230 20_0402_5% S

3
2
S PQ212A PC213 SSM3K7002FU_SC70-3 2
1

DMN66D0LDW-7_SOT363-6 1 2 5 ICOMP CSIN 20 2 1

2
PR231 4
PC214 PC220
PQ212B 6800P_0402_25V7K 20_0402_5%
SB00000EO00 1 2 1
PR218
2 6 19
0.1U_0603_25V7K
1 2
DMN66D0LDW-7_SOT363-6

1
VCOMP CSIP
3

D PR232 PL202
10K_0402_1% 2_0402_5% 10UH_MSCDRI-104A-100M-E_4.6A_20% PR235 BATT+
5 0.01U_0402_25V7K PR219

3
2
1
G 1 2 7 18 LX_CHG 1 2 CHG 1 4
37,42 ADP_I ICM PHASE
PR211 100_0402_1%

1
5
6
7
8
22K_0402_5% S PC215 2 3
2.39V
4

1 2 1 2 41 8 17 DH_CHG PQ202
41 PACIN 6251VREF VREF UGATE PR206
PR220 AO4466L_SO8 0.02_1206_1%

10U_1206_25V6M

10U_1206_25V6M

10U_1206_25V6M
154K_0402_1% .1U_0402_16V7K PR205 PC205 4.7_1206_5%
37 IREF 2 1 9 16 BST_CHG 1 2 BST_CHGA 2 1
41 ACON

2
CHLIM BOOT

1
3.3_0603_1% 4
0.01U_0402_25V7K

90W@
1

1
0.1U_0603_25V7K

PC202

PC203

PC204
PR222
PD202
1

1
6251VREF
1 2 6251aclim 10 15 6251VDDP
ACLIM VDDP
1

PQ213 RB751V-40_SOD323-2 PC206

PC216

2
PR221 53.6K_0402_1%
DTC115EUA_SC70-3 1 2 6251VDD 680P_0603_50V7K

2
3
2
1
ACOFF 2 120K_0402_1% 11 14 DL_CHG PR233 4.7_0603_5%
37 ACOFF
2

VADJ LGATE
1

2
2

PC221
90W@ PR223 12 13 4.7U_0603_6.3V6M

1
GND PGND
20K_0402_1%
3

65W@ PR222 ISL6251AHAZ-T_QSOP24

75k_0402_1%

65W@ PR223
20k_0402_1%
PR224
3
37 CHGVADJ 1 2 3

15.4K_0402_1%
2

PR225
31.6K_0402_1% 6251VDD

VIN
1

PR241

1
10K_0402_1%

1
PR240 1 2 ACIN 13,23,37,39
47K_0402_1% PR242
PR246
10K_0402_1%
309K_0402_1%
2

2
PACIN PR247

2
10K_0402_1%

1
1 2 ADP_V 37
PQ214
DTC115EUA_SC70-3

1
ACPRN 2 PR243 PR248 PC223
CP mode CP= 92%*Iada 14.3K_0402_1% 47K_0402_1% .1U_0402_16V7K

2
CC=0.25A~3.6A

2
Vin Detector
3

IREF=0.9133*Icharge UMA
IREF=0.228V~3.288V Iada=0~3.421A(65W) CP=3.147A
High 18.089V
4
VCHLIM need over 88mV Vaclim=0.619V(65W) PR222=75k, PR223=20k, PR215=0.02 4

Low 17.44V
CHGVADJ=(Vcell-4)*9.445 DIS 1.26 / 14.3 * 205.3 = 18.089V
Vcell CHGVADJ Iada=0~4.74A(90W) CP=4.36A
4V 0V Vaclim=0.735V(90W) PR222=53.6k, PR223=20k, PR215=0.015
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title
4.2V 1.889V SCHEMATIC, MB A7213
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4.35V 3.30575V Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 43 of 51
A B C D
 5 4 3 2 1

www.qdzbwx.com
2VREF_8205

D D

1
PC363
1U_0603_10V6K

2
PR362 PR364
13K_0402_1% 30K_0402_1%
1 2 1 2

PR363 PR365
RT8205_B+ 20K_0402_1% 19.1K_0402_1%
1 2 1 2 RT8205_B+
PJ331
@ JUMP_43X118

ENTRIP1
ENTRIP2
B+ 2 2 1 1 +3VLP PR337 PR357
150K_0402_1% 150K_0402_1%
1

1
PC360 1 2 1 2 PC366
10U_1206_25V6M 10U_1206_25V6M
2

2
4.7U_0805_10V6K
8
7
6
5

5
6
7
8
PU330

1
PQ331 PQ351

PC361

VREF
ENTRIP2

VFB2

TONSEL

VFB1

ENTRIP1
C AO4466L_SO8 C
25

2
P PAD
4 4
7 VO2 VO1 24 POK 42,46

PC335 8 VREG3 PGOOD 23 PC355

PR335 PR355 AO4466L_SO8
1
2
3

3
2
1
0.1U_0603_25V7K
1 2 1 2 BST_3V 9 VBST2 VBST1 22 BST_5V 1 2 1 2 0.1U_0603_25V7K
PL332 2.2_0603_1% 2.2_0603_1% PL352
UG_3V 10 21 UG_5V
4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20% DRVH2 DRVH1 4.7UH_VMPI0703AR-4R7M-Z01_5.5A_20%
LX_3V LX_5V
+5VALWP
+3VALWP 1 2 11 LL2 LL1 20 1 2

LG_3V 12 19 LG_5V
DRVL2 DRVL1
1

8
7
6
5

5
6
7
8

1
SKIPSEL

330U_6.3V_M
PQ332

VREG5
PR356

VCLK
1 PR336 1

GND
EN0
4.7_1206_5%

VIN
4.7_1206_5%
+ 41 EN0 +

PC352
PC332
1 2

1 2
4 PR360 TPS51125ARGER_QFN24_4X4 4
330U_6.3V_M

13

14

15

16

17

18
PC336 499K_0402_1%
2 PC356 2
15mohm 680P_0603_50V7K
B+ 1 2 PQ352 15mohm
680P_0603_50V7K
2

2
Ipeak=5A AO4712L_SO8 AO4712L_SO8

100K_0402_5%
1
2
3

3
2
1
1
1
Imax=3.5A VL

PR361
PC362
F=305KHz

1
1U_0402_6.3V6K
PC364
2
B Total Capacitor 330uF 4.7U_0805_10V6K
B

2
ESR 15mohm RT8205_B+ Ipeak=5A

2
Imax=3.5A
F=245KHz
ENTRIP1 ENTRIP2 Total Capacitor 330uF
ESR 15mohm

1
PC365
2VREF_8205
6

D D 0.1U_0603_25V7K

2
2 5
PQ360A G G PQ360B
DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
S S
1

SB00000EO00
PR370
VL 2 1
100K_0402_1%
1

42 VS_ON

PR371
VS 1 2 2
100K_0402_1%
0.01U_0402_16V7K
42.2K_0402_1%

PQ361
1

A A
1

DTC115EUA_SC70-3
PR372

@PC370

3
2
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 44 of 51
5 4 3 2 1
 A B C D

www.qdzbwx.com
PJ151
@ JUMP_43X118
2 2
DIS
1 1 B+
Ipeak=20A

4.7U_0805_25V6-K

4.7U_0805_25V6-K
Imax=14A

1
PC153

PC154
1 Rtrip=14K, OCP=24.13A 1

F=315KHz

2
Total Capacitor 1500uF,
ESR 2.73mohm

5
PR164
255K_0402_1%
HW side:
1 2 PR521 C106 390uF 10m
0_0603_5% PQ151 C218 390uF 10m
PR155 1 2 4
PR160 BST_1.5V 1 2 TPCA8065-H_PPAK56-8-5
65W@ PL152
VGA@ CV122 390uF 10m
35,37,40 SYSON 1 2 2.2_0603_1% 1.8uH @ C189 330uF 15m
0_0402_5%

3
2
1
1
90W@ PL152

15

14
PC160 @

1
PU150 PC155 1UH_MMD-10DZ-1R0M-X1A_18A_20%
.1U_0402_16V7K BST_1.5V-1 1 2 2 1 +1.5VP

EN_SKIP

TP

BST
2

2 13 DH_1.5V 0.1U_0603_25V7K
TON DH
LX_1.5V
UMA
3 OUT LX 12

1
PR161 90W@ PR157 PQ603 Ipeak=8.5A
1 2 4 11 1 2 PR156 1 Imax=5.95A
+5VALW VCC ILIM +5VALW

TPCA8059-H_PPAK56-8-5
14K_0402_1% 4.7_1206_5%
100_0603_5% + PC152 Rtrip=5.9K, OCP=10.44A
5 FB VDD 10
330U_6.3V_M F=315KHz

2
1

PC161 6 9 DL_1.5V 4
PGOOD DL 2

AGND

PGND
4.7U_0603_6.3V6K Total Capacitor 1110uF,

2
65W@ PR157
ESR 3.75mohm
2

1
5.9K_0402_1% PC162 PC156
2
G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K 680P_0603_50V7K 2

3
2
1

2
PR162
1 2
10K_0402_1%
1

PR163
10K_0402_1%
2

+1.5V

1
@PJ75
@ PJ75

1
JUMP_43X79

2
2
3 3

PU75
PU25 1 VIN VCNTL 6 +3VALW
APL5508-25DC-TRL_SOT89-3
PJ251
+3VS PC261 2 5
GND NC

1
1 2 2 3 +2.5VSP 4.7U_0805_6.3V6K
1 2 IN OUT

1
3 7 PC264
@ JUMP_43X39 PR282 PR280 VREF NC

2
GND 0_0402_5% 1K_0402_1% 1U_0603_10V6K
4 VOUT NC 8
1

1 2
PC251 1 PC252 40 SUSP 9

2
1U_0603_10V6K 4.7U_0805_6.3V6K TP
2

G2992F1U_SO8

.1U_0402_16V7K
+0.75VSP

1
D

SSM3K7002FU_SC70-3
PQ260

1K_0402_1%

PC263
2

1
G

2
S PR281 PC262

3
1
10U_0805_6.3V6M

2
@ PC260
.1U_0402_16V7K
2

For shortage changed

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 45 of 51
A B C D
 5 4 3 2 1

www.qdzbwx.com 2
PJ401
2 1 1 B+

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@ JUMP_43X118

1
PC413

PC414
2

2
D D

5
6
7
8
PQ401

PR414
255K_0402_1% 4
1 2
PR410 PR405
0_0402_5% 2.2_0603_1%
1 2 1 2 AO4466L_SO8
42,44 POK

3
2
1
1
PL402

15

14
PC405

1
@ PC410 PU400 2.2UH_VMPI0703AR-2R2M-Z01_8A_20% Ipeak=5.3A
.1U_0402_16V7K BST_1.1V 1 2 1 2

EN_SKIP

TP

BST
+1.1VALWP

2
Imax=3.71A
2 13 DH_1.1V 0.1U_0603_25V7K
TON DH Rtrip=14K, OCP=6.64A

4.7_1206_5%
PR411 3 OUT LX 12 LX_1.1V F=315KHz

5
6
7
8

PR406
100_0603_1%
+5VALW
1 Total Capacitor 330uF,

330U_6.3V_M
+5VALW 1 2 4 VCC ILIM 11 1 2
+ ESR 15mohm

PC402
PR407

2
5 10 14K_0402_1%
FB VDD
1

1
DL_1.1V 2
6 PGOOD DL 9 4

AGND

PGND

680P_0603_50V7K
PC411

PC406
4.7U_0603_6.3V6K @ PC114
2

2
47P_0402_50V8J PC412
C 1 2 G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K PQ402 C

3
2
1
AO4712L_SO8

PR412
4.75K_0402_1%
1 2
1

PR413
10K_0402_1%
2

PU180 90W@
SY8033BDBC_DFN10_3X3 90W@ PL182
4

PJ181 @ 1UH_FMJ-0630T-1R0 HF_11A_20%

+3VALW 2 2 1 10 2 LX_1.8V 1 2 +1.8VSGP Ipeak=2.5A
PG

B 1 PVIN LX B
ILIM = 4A

68P_0402_50V8J
JUMP_43X39 9 3
PVIN LX

1
F=1MHz

4.7_1206_5%
1

1
90W@ PC184 8 Total Capacitor 44uF,
SVIN PR183 90W@ PC187
22U_0805_6.3VAM PR186
FB=0.6Volt 20K_0402_1% 90W@

22U_0805_6.3VAM
6

22U_0805_6.3VAM
2

2
FB 90W@
5

2
EN

1
NC

NC
TP

PC183
PC182
2
90W@ PR181 FB_1.8V
11

2
1

680P_0603_50V7K
40,48 GPU_PWREN 1 2 EN_1.8V PC186

1
90W@
150K_0402_1%
PR184 90W@
2
1

10K_0402_1% 90W@ 90W@

1

PR182 @ PC185 90W@

2
499K_0402_1% 0.1U_0402_10V7K
2
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 46 of 51
5 4 3 2 1
 5 4 3 2 1

www.qdzbwx.com

D D

PJ451
1.2V_B+ 2 1 B+
2 1

4.7U_0805_25V6-K

4.7U_0805_25V6-K
@ JUMP_43X118

1
PC463

PC464
5
6
7
8
C C

2
PQ451

PR462
255K_0402_1% 4
1 2
PR455
PR460
2.2_0603_1%
1 2 1 2 AO4466L_SO8
37,40,49 VR_ON

3
2
1
0_0402_5%
1

PL452

15

14
1 PC455
@ PC460 PU450 2.2UH_VMPI0703AR-2R2M-Z01_8A_20%
.1U_0402_16V7K BST_1.2V 1 2 1 2
EN_SKIP

TP

BST
+1.2VSP
2

2 13 DH_1.2V 0.1U_0603_25V7K
TON DH

1
PR461 3 12 LX_1.2V PR456 Ipeak=6.5A
OUT LX

5
6
7
8
100_0603_1% 4.7_1206_5% 1
Imax=4.55A

330U_2.5V_M
+5VALW 1 2 4 11 1 2 +5VALW
VCC ILIM +

PC452
PR457
Rtrip=18K, OCP=8.37A

680P_0603_50V7K
5 10 18K_0402_1%
FB VDD F=315KHz
1

1
2

PC456
6 9 DL_1.2V 4
PGOOD DL Total Capacitor 720uF,
AGND

PGND

PC461

1
4.7U_0603_6.3V6K @ PC123 ESR 6mohm
2

2
47P_0402_50V8J PC462
1 2 G5603RU1U_TQFN14_3P5X3P5 4.7U_0805_10V6K PQ452 HW side:
7

3
2
1
B AO4712L_SO8 B
C130 390uF 10m
PR465
6.04K_0402_1%
1 2
1

PR466
10K_0402_1%
2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 47 of 51
5 4 3 2 1
 5 4 3 2 1

PL601 90W@
www.qdzbwx.com
HCB4532KF-800T90_1812
1 2 B+_core
B+

10U_1206_25VAK

10U_1206_25VAK
Ipeak=32.6A

4.7U_0805_25V6-K
1

1
Imax=20.3A

90W@ PC620

90W@ PC621
Rtrip=165K, OCP=36.19A

1
PC622
2

2
D F=290KHz D

5
Total Capacitor 1220uF,

2
@
+3VS ESR 4.59mohm

2
90W@ PR520
90W@ PR620 0_0603_5% PQ601 90W@ HW side:
10K_0402_1% 1 2 4
TPCA8065-H_PPAK56-8-5 CV221 390u 17m
CV224 390u 17m

1
PU700 90W@ PR605 90W@ PC605 90W@
1 10 BST_VCORE 1 2 1 2
17,22,40 VGA_PWRGD

3
2
1
PGOOD VBST 0_0603_5%
90W@ PR624
1 2 2 9 DH_VCORE 0.1U_0603_25V7K PL602 90W@ +VGA_COREP
TRIP DRVH 0.56UH_ETQP4LR56WFC_21A_20%
PR623 165K_0402_1%
1 2 3 8 LX_VCORE 1 2
40 VGACORE_EN EN SW PR626 90W@
1

560U_2.5V_M
TPCA8059-H_PPAK56-8-5
.1U_0402_16V7K
0_0402_5% 4 7 1 2 +5VALW
VFB V5IN

5
PC623
90W@ 0_0603_5% @ PR606 1

90W@ PC602
5 6 DL_VCORE PQ602 PQ604 4.7_1206_5%
90W@
2

RF DRVL

1
90W@ @ +

2
@ 11 PC636

2
TP PC628 90W@

2
90W@ RT8237CZQW(2) WDFN 2
2.2U_0603_6.3V6K 4 4 0.1U_0402_25V6

1
PR625

1
1 470K_0402_1% TPCA8059-H_PPAK56-8-5 @ PC606
680P_0603_50V7K

3
2
1

3
2
1

2
90W@ PR631
C 2 1 C
VCORE_SENSE 15
100_0402_1%

10K_0402_1%
+3VSG +3VSG

6.19K_0402_1%
2

10K_0402_1%
@ PR633

PR640
90W@ @

2
PR642 @

PR634
10K_0402_1%
2.94K_0402_1%

1 1

1 1
2

PR632 PR643 @ PR635 90W@

90W@ D 13 GPU_VID1 D 5.1K_0402_1%13 GPU_VID0

SSM3K7002FU_SC70-3
5.1K_0402_1%

1
PQ606
2 1 2 2 1 2

.1U_0402_16V7K

.1U_0402_16V7K
G G

2
S S
1

3
1

1
90W@ PC633
90W@PC633
@ @ PR644 PQ605 PR636 90W@

PC634
10K_0402_5% 90W@ 10K_0402_5%
SSM3K7002FU_SC70-3

2
1

1
@
1

Rtrip = 165K, OCP = 36.19A @PC635

@PC635 @PR637 +VGA_COREP
PR641 90W@
6.98K_0402_1% 2 1 1 2
Rrf = 470K, FSW = 290KHz
1000P_0402_50V7K 2.94K_0402_1%
2

B B

+1.5V +5VALW
GPU VID1 GPU VID0 Capilano LP Whistler Pro

1
PC108

1
@ PJ101 90W@

1
X L 1 1 JUMP_43X79 1U_0603_6.3V6M

2
2
4.7U_0805_6.3V6K
X H 0.9 0.9 90W@

2
PC109 PU100 APL5930KAI-TRG_SO8
90W@ 6
H L VCNTL

1
5 VIN VOUT 3 +1.0VSGP
9 VIN VOUT 4

1
90W@
H H

1
8 PR101 PC102 90W@
90W@ EN 1.82K_0402_1%
PR105 7 2 22U_0805_6.3V6M

GND
10K_0402_1% POK FB

2
40,46 GPU_PWREN 1 2

2
1
1

1
PC105 90W@ 90W@ PC106 90W@
1U_0402_16V6K PR106 0.01U_0402_25V7K

2
7.32K_0402_1%

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 48 of 51
5 4 3 2 1
 5 4 3 2 1

CPU_B+

www.qdzbwx.com PL501
HCB4532KF-800T90_1812
1 2 B+

2200P_0402_50V7K
10U_1206_25V6M

0.01U_0402_25V7K
10U_1206_25V6M
1

1
PC563

PC564

PC565

PC567
5
Ipeak=27.5A

2
PLACE NEAR NB choke Imax=15.75A
NB@ PR517 Ri=845, Rdroop=976,OCP=34.92A
NB@ PR509 0_0603_5% PQ501
10_0402_5% NB@ PC556 NB@ F=300KHz
1 2 4
2 1 0.01U_0402_25V7K~N VSUMG+ TPCA8065-H_PPAK56-8-5 Total Capacitor 660uF,

1
ESR 8.5mohm

2.61K_0402_1%
2 1

2
D D

NB@ PR572
NB@ PL502

0.1U_0402_10V7K

0.047U_0402_16V7K
7 APU_VDDNB_RUN_FB_L

3
2
1
NB@ PC557 0.36UH_PCMC104T-R36MN1R17_30A_20% HW side:

11K_0402_1%
330P_0402_50V7K 1 4
7 APU_VDDNB_SENSE

1
2 1 +CPU_CORE_NB C160 330u 17m

2
+CPU_CORE_NB

NB@ PC573

NB@PC571
NB@PC571

NB@ PR573
10_0402_5% 2 3 C201 330u 17m

5
2 1

2
10K_0402_1%_TSM0A103F34D1RZ

1
NB@ PC558 NB@ @C163 330u 9m

1
NB@ PR508 NB@PQ502
NB@PQ502
330P_0402_50V7K NB@ PH504 PR506

2
TPCA8059-H_PPAK56-8-5 4.7_1206_5%
PLACE NEAR NB L-MOS
4 NB@PR570

1 2
VSUMG-
3.65K_0402_1%
NB@ NB@ NB@ NB@ PC506 VSUMG+ 2 1
PC533 PR533 PR534
470P_0402_50V7K 143K_0402_1% 2.26K_0402_1% NB@ PH4
680P_0603_50V7K

3
2
1

2
845_0402_1%
2 1 2 1 2 1 470K_0402_5%_TSM0B474J4702RE
PC570 NB@ NB@ PR571
1 2
1_0402_1%

NB@ PR575
0.1U_0603_50V7K

2
NB@PR514 VSUMG- 2 1
1

NB@ +5VS 27.4K_0402_1%

2
PR531 2 1 2 1 2 1 1 2 1 2
100K_0402_1%
NB@PC531
NB@PC531 NB@ PR532
NB@PR532 NB@ PC532 NB@ PR550

BOOT1_NB 6.65K_0402_1%
3.83K_0402_1%
100P_0402_50V8J 324_0402_1% 1000P_0402_50V7K
2

0_0603_5%

2
NB@PR505
NB@PR505 PC505
NB@PC505
NB@

PR563

NB@ PR548
DIS@
2.2_0603_1% 0.1U_0603_50V7K
2

2 1 2 1
2

NB@ PR530 NB@ PC530

PROG2 1
1000P_0402_50V7K

NTC_NB
8.06K_0402_1%
1

CPU_B+
1

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
PC583

PC584

PC585
1 1 1 1
Rfset(Kohm)=(Period(uS))-0.29)*2.65

100U_25V_M
100U_25V_M

100U_25V_M
48

47

46

45

44

43

42

41

40

39

38

37

47U_25V_M

PC574
+ + + +

PC568

PC566

PC569
PU500 PR518
0_0603_5%
C C

ISEN2_NB

VSEN_NB

RTN_NB

ISUMP_NB

LG1_NB
ISEN1_NB

ISUMN_NB

NTC_NB

BOOT1_NB

UG1_NB

PH1_NB
PROG2
UGATE1 1 2 4

2
2 @ 2 @ 2 2

1 36 +5VS PQ503
FB2_NB PWM2_NB
BOOT2 TPCA8065-H_PPAK56-8-5 PL504

3
2
1
2 FB_NB BOOT2 35 0.36UH_PCMC104T-R36MN1R17_30A_20%
PHASE1 4 1
3 COMP_NB UG2 34 UGATE2 +CPU_CORE

1
+3VS

0_0603_5%

680P_0603_50V7K 4.7_1206_5%
PHASE2 PR561 PC525 3 2
4 33

PR526
VW_NB PH2 0.22U_0603_10V7K PR591

PR562
0_0603_5% BOOT1 2 ISEN1
5 32 LGATE2 1 2 1 2 1
PGOOD_NB LG2 PR525
1

PR510 0_0402_5% @ 10K_0402_1%

2
0_0603_5%
1 SDA

2
7 APU_SVD 2 6 SVD VCCP 31 LGATE1
1

PR541 PR511 0_0402_5% ISL6267HRZ-T_QFN48_6X6 4

PR592 PR590
100K_0402_5% 2 1 ALERT# 7 30 PWM3

1
PC526
22 APU_PWRGD_L PWROK PWM3 PQ504 VSUM+ ISEN2

1
2 1 2 1

1U_0603_10V6K
PR512 0_0402_5%
2

PC554
@
7 APU_SVC 2 1 SCLK 8 SVC LG1 29 LGATE1 3.65K_0402_1% 10K_0402_1%
PR513

3
2
1

2
@
2

2
100K_0402_5% PHASE1 TPCA8059-H_PPAK56-8-5 PR593 If the layout of each phase to CPU
37,40,47 VR_ON 9 ENABLE PH1 28 VSUM- 2 1
UGATE1
is symmetric, the two res. can be
37 VGATE 10 PGOOD UG1 27 1_0402_1%
removed.
11 26 BOOT1 They are used for phase current
7,37,42 H_PROCHOT# PROC_HOT BOOT1
PR544 3.83K_0402_1% PR545 27.4K_0402_1%
balance adjustment.
ISEN3/FB2

2 1 2 1 12 NTC PROG1 25 1 2 CPU_B+

ISUMN

ISUMP
COMP

ISEN2

ISEN1

VSEN

PR560

5
VDD
RTN

VIN
VW

6.65K_0402_1%
FB

TP

Ipeak=54A

4.7U_0805_25V6-K

4.7U_0805_25V6-K

4.7U_0805_25V6-K
2 1

PC580

PC581

PC582
PLACE NEAR Phase1 L-MOS PR519 Imax=36A
13

14

15

16

17

18

19

20

21

22

23

24

49

PH502 470K_0402_5%_TSM0B474J4702RE

1
0_0603_5% Ri=976, Rdroop=2.67K,OCP=65.21A
UGATE2 1 2 4
CPU_B+ F=300KHz
1U_0603_10V6K

2
2 PR559
1
Total Capacitor 1320uF,
1

0_0603_5% PQ505
1

PR546
2 1 +5VS TPCA8065-H_PPAK56-8-5 PL503 ESR 2.25mohm

3
2
1
PC539 PR558 0.36UH_PCMC104T-R36MN1R17_30A_20%
B B
0.22U_0603_25V7K

8.06K_0402_1% 1000P_0402_50V7K 1_0603_5%

2

Rfset(Kohm)=(Period(uS))-0.29)*2.65 PC540 33P_0402_50V8K PHASE2 HW side:

2

4 1 +CPU_CORE
PC549

1 2
C145 330u 9m
PC515
2

3 2
0.22U_0603_10V7K C146 330u 9m
ISEN2

PC548
ISEN1

680P_0603_50V7K 4.7_1206_5%
BOOT2 2 1 2 1 C147 330u 9m

PR516
PR515
0_0603_5% PR580 PR581 C148 330u 9m
PR547 VSUM+ ISEN2 ISEN1
100K_0402_1% PC541 PC542 2 1 2 1
PR543 @
1

2
2 1 2 1 2 1 2 1 LGATE2 10K_0402_1% 10K_0402_1%
PR557 4
324_0402_1% PQ508
2.61K_0402_1%
0.22U_0402_10V6K

0.01U_0402_16V7K

68P_0402_50V8J 1000P_0402_50V7K
11K_0402_1%

1
PC516
1

PC543 PR549 PR551 TPCA8059-H_PPAK56-8-5 PR582

VSUM+
2

2 1
PC550

PC551

PR556

3
2
1
2 1 2 1 2 1
VSUM-

2
2 1 @ 3.65K_0402_1%
2

470P_0402_50V7K 143K_0402_1% 2.67K_0402_1%

PC562 0.22U_0402_6.3V6K PH503 PR583
VSUM-
2

2 1
2 1 10K_0402_1%_TSM0A103F34D1RZ
PR554 1_0402_1%
PR524 PC544 0.22U_0402_6.3V6K 976_0402_1%
2

10_0402_5% 2 1 VSUM-
+CPU_CORE 2 1
1

2 1 PC553
PLACE NEAR Phase1 choke 0.1U_0603_50V7K
2

PC545
7 APU_VDD_SENSE
1

330P_0402_50V7K
PC547
7 APU_VDD_RUN_FB_L
330P_0402_50V7K
2

2 1
PR527
10_0402_5% PC546
2 1 0.01U_0402_25V7K~N

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 49 of 51
5 4 3 2 1
NO DATE

2011/03/30
PAGE

42
MODIFICATION LIST

Change PR22 to 180Ω,PR28 to 1.18KΩ

Change PR22 to 523Ω,PR28 to 3KΩ
PURPOSE
--------------------------------------------------------------------------------------------------------------------------------
For 65W SKU
For 90W SKU
www.qdzbwx.com
43 Change PC217 to SE074102K80,PR236 to 200KΩ,PR237 to 47KΩ Circuit modify
PR205 to 3.3Ω,PR235 to SD00000S120,Add PR206,PC206,
Delete PC211
Change PR222 to 53.6KΩ,PR223 to 20KΩ,Delate PQ209 For 90W SKU
Change PR222 to 75KΩ For 65W SKU

44 Change PR335,PR355 to 2.2Ω,PC332,PC352 to SF000002080 Circuit modify

,PL332,PL352 to SH00000KN00,Add PR336,PR356,PC336,PC356
45 Change PR155 to 2.2Ω,PC152 to SF000002080, Circuit modify
Add PR156,PC156,PR521,Delete PC260
Change PR157 to 5.9KΩ,PL152 to SH00000IP00 For 90W SKU
Change PR157 to 14KΩ,PL152 to SH00000CN00 For 65W SKU

46 Change PR405 to 2.2Ω,PC402 to SF000002080,Add PR406,PC406 Circuit modify

Change PR407 to 14KΩ,PL402 to 2.2UH 7*7
47 Change PR455 to 2.2Ω,PR457 to 18KΩ,PL452 to 2.2UH 7*7 Circuit modify
Add PR456,PC456

48 Change PR624 to 165KΩ,PR631 to 100Ω,Delete PR630, Circuit modify

Add PC636,PR520
49 Change PR505 to 2.2Ω,PR560 to 6.65KΩ,PR551 to 2.67KΩ Circuit modify
Change PH503,PH504 to SL200000W00,PC569,PC574 to SF000003W00
Add PC506,PR506,PR517,PR518,PR519

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 50 of 51
 5 4 3 2 1

HW PIR (Product Improve Record)

QHRAE LA-7213P SCHEMATIC CHANGE LIST
www.qdzbwx.com
REVISION CHANGE: 0.1 TO 0.2

D Item Date Page Solution Request D

--------------------------------------------------------------------------------------------------------------------------
1. 3/17 P23 Remove level-shifter for ODD_PLUGIN# ODD has internal 1K pull-down
2. 3/17 P34 Add level-shifter for CR_CPPE# For leakage issue
3. 3/17 P23 Change HDMI_HPD to GEVENT10# and reserve GEVENT19# GEVENT9# has issue
4. 3/17 P24 Change LOGO_LED to GPIO176 and WL_BT_LED to GPIO177 For LED flash issue after power-on
5. 3/24 P10 Add C295,C316,C324,C325 For EMI test
6. 3/28 P39 Reserve C20,C21,C229,C231~C236,C247,C251 For ESD test)
7. 3/29 P38 Change LPC debug port to 16pins connector To support new debug card
8. 3/30 P07 Add R70,R102,R105 Pull-down for unused HPD port
---------------------------------------------------------------------------------------------------------------------

REVISION CHANGE: 0.2 TO 1.0

Item Date Page Solution Request

--------------------------------------------------------------------------------------------------------------------------
C C
1. 4/15 P31 Reserve D24, D25
2. 4/27 P22 Change R257 form 100k to 10k for leakage issue.
3. 4/27 P37 Add BACO_EN# to EC To inform EC GPU thermal sensor status

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2011/01/06 Deciphered Date 2012/01/06 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A7213
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019D8
Date: Monday, July 04, 2011 Sheet 51 of 51
5 4 3 2 1