STF18N60M2

Datasheet

N-channel 600 V, 0.255 Ω typ., 13 A MDmesh M2

Power MOSFET in a TO-220FP package

Features
Order code VDS @TJmax RDS(on) max. ID

STF18N60M2 650 V 0.280 Ω 13 A

• Extremely low gate charge

3 • Excellent output capacitance (COSS) profile
2
1
• 100% avalanche tested
TO-220FP • Zener-protected

D(2)

Applications
• Switching applications
• LCC converters
G(1)
• Resonant converters

Description
This device is an N-channel Power MOSFET developed using MDmesh M2
S(3) AM15572v1_no_tab
technology. Thanks to its strip layout and an improved vertical structure, the device
exhibits low on-resistance and optimized switching characteristics, rendering it
suitable for the most demanding high efficiency converters.

Product status link

STF18N60M2

Product summary

Order code STF18N60M2

Marking 18N60M2
Package TO-220FP
Packing Tube

DS9710 - Rev 4 - June 2019 www.st.com

For further information contact your local STMicroelectronics sales office.
 STF18N60M2
Electrical ratings

1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VGS Gate-source voltage ±25 V

Drain current (continuous) at TC = 25 °C 13 A

ID (1)
Drain current (continuous) at TC = 100 °C 8 A

IDM (2)
Drain current (pulsed) 52 A

PTOT Total power dissipation at TC = 25 °C 25 W

dv/dt (3) Peak diode recovery voltage slope 15 V/ns

dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns

Insulation withstand voltage (RMS) from all three leads to external heat
VISO 2.5 kV
sink (t = 1 s; TC = 25 °C)

Tstg Storage temperature range

-55 to 150 °C
Tj Operating junction temperature range

1. Limited by maximum junction temperature.

2. Pulse width limited by safe operating area.
3. ISD ≤ 13 A, di/dt ≤ 400 A/µs; VDS(peak) < V(BR)DSS, VDD = 400 V
4. VDS ≤ 480 V

Table 2. Thermal data

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case 5 °C/W

Rthj-amb Thermal resistance junction-ambient 62.5 °C/W

Table 3. Avalanche characteristics

Symbol Parameter Value Unit

Avalanche current, repetitive or not repetitive

IAR 3 A
(pulse width limited by Tjmax)

EAS Single pulse avalanche energy (starting Tj=25 °C, ID= IAR, VDD=50 V) 135 mJ

DS9710 - Rev 4 page 2/12

 STF18N60M2
Electrical characteristics

2 Electrical characteristics

(TC = 25 °C unless otherwise specified).

Table 4. On /off states

Symbol Parameter Test conditions Min. Typ. Max. Unit

Drain-source breakdown
V(BR)DSS ID = 1 mA, VGS = 0 V 600 V
voltage
VGS = 0 V, VDS = 600 V 1 µA
Zero gate voltage
IDSS VGS = 0 V, VDS = 600 V,
drain current 100 µA
TC = 125 °C (1)

Gate-body leakage
IGSS VDS = 0 V, VGS = ± 25 V ±10 µA
current
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2 3 4 V

Static drain-source
RDS(on) VGS = 10 V, ID = 6.5 A 0.255 0.280 Ω
on-resistance

1. Defined by design, not subject to production test.

Table 5. Dynamic

Symbol Parameter Test conditions Min. Typ. Max. Unit

Ciss Input capacitance - 791 - pF

VDS = 100 V, f = 1 MHz,
Coss Output capacitance - 40 - pF
VGS = 0 V
Crss Reverse transfer capacitance - 1.3 - pF

Coss eq. (1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 164.5 - pF

RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 5.6 - Ω

Qg Total gate charge VDD = 480 V, ID = 13 A, - 21.5 - nC

Qgs Gate-source charge VGS = 0 to 10 V (see - 3.2 - nC

Figure 14. Test circuit for gate
Qgd Gate-drain charge charge behavior) - 11.3 - nC

1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.

Table 6. Switching times

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time VDD = 300 V, ID = 6.5 A, - 12 - ns

tr Rise time RG = 4.7 Ω, VGS = 10 V - 9 - ns

td(off) Turn-off delay time (see Figure 13. Test circuit for - 47 - ns
resistive load switching times
and Figure 18. Switching time
tf Fall time - 10.6 - ns
waveform)

DS9710 - Rev 4 page 3/12

 STF18N60M2
Electrical characteristics

Table 7. Source-drain diode

Symbol Parameter Test conditions Min. Typ. Max. Unit

ISD Source-drain current - 13 A

ISDM (1) Source-drain current (pulsed) - 52 A

VSD (2) Forward on voltage ISD = 13 A, VGS = 0 V - 1.6 V

trr Reverse recovery time ISD = 13 A, di/dt = 100 A/µs - 305 ns

Qrr Reverse recovery charge VDD = 60 V (see - 3.3 µC

Figure 15. Test circuit for
IRRM Reverse recovery current inductive load switching and - 22 A
diode recovery times)
trr Reverse recovery time ISD = 13 A, di/dt = 100 A/µs - 417 ns

Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 4.6 µC

(see Figure 15. Test circuit for
IRRM Reverse recovery current inductive load switching and - 22 A
diode recovery times)

1. Pulse width limited by safe operating area.

2. Pulsed: pulse duration = 300 μs, duty cycle 1.5%.

DS9710 - Rev 4 page 4/12

 STF18N60M2
Electrical characteristics (curves)

2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance

AM15834v1
ID K GC20940
(A)

10 s
ai
re on)
si a DS(
th R 10 -1
in ax 10µs
n
it o by m
ra
pe ed
1 O imit
L 100µs

1ms
10 -2
Tj=150°C 10ms
0.1
Tc=25°C
Single
pulse
0.01 10 -3
0.1 1 10 100 VDS(V) 10 -4 10 -3 10 -2 10 -1 10 0 t p (s)

Figure 3. Output characteristics Figure 4. Transfer characteristics

AM15837v1 AM15838v1
ID ID
(A) VGS=7, 8, 9, 10V (A) VDS = 18V
30 30

25 25

6V
20 20

15 15

10 10
5V
5 5
4V
0 0
0 5 10 15 20 VDS(V) 0 2 4 6 8 10 VGS(V)

Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance

AM15839v1 AM15840v1
VGS VDS RDS(on)
(V) (V) (Ω)
VDS VGS=10V
12 0.270
VDD = 480 V 500
ID = 13 A
10
400 0.265
8
300 0.260
6
200 0.255
4

2 100 0.250

0 0 0.245
0 5 10 15 20 25 Qg (nC) 0 2 4 6 8 10 12 ID(A)

DS9710 - Rev 4 page 5/12

 STF18N60M2
Electrical characteristics (curves)

Figure 8. Normalized gate threshold voltage vs.

Figure 7. Capacitance variations
temperature
AM15841v1
C
VGS(th) GIPG070815BQ6KLVTH
(pF)
(norm.)
ID = 250 µA
1.1
1000
Ciss
1.0

100
0.9
Coss
0.8
10

0.7
1 Crss
0.1 1 10 100 VDS (V) 0.6
-75 -25 25 75 125 TJ (°C)

Figure 9. Normalized on-resistance vs temperature Figure 10. Source-drain diode forward characteristics
AM15842v1
RDS(on) GIPG070815BQ6KLRON
VSD(V)
(norm.)
VGS = 10 V 1.4
2.4
1.2
2.0 TJ=-50°C
1.0
1.6
0.8
1.2
0.6 TJ=25°C
TJ=150°C
0.8 0.4

0.4 0.2

0.0 0.0
-75 -25 25 75 125 TJ (°C) 0 2 4 6 8 10 12 ISD(A)

Figure 11. Normalized V(BR)DSS vs temperature Figure 12. Output capacitance stored energy
AM15843v1
V(BR)DSS GIPG070815BQ6KLBDV Eoss
(norm.) (µJ)
ID = 1 mA
1.12 6

1.08 5

1.04 4

1.00 3

0.96 2

1
0.92

0.88 0
-75 -25 25 75 125 TJ (°C) 0 100 200 300 400 500 600 VDS (V)

DS9710 - Rev 4 page 6/12

 STF18N60M2
Test circuits

3 Test circuits

Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior

VDD

12 V 47 kΩ
1 kΩ
100 nF
RL
2200 3.3
+ μF μF VDD
VD IG= CONST
VGS 100 Ω D.U.T.

VGS
RG D.U.T. pulse width +
2.7 kΩ
2200 VG
pulse width μF
47 kΩ

1 kΩ

AM01468v1 AM01469v1

Figure 15. Test circuit for inductive load switching and

Figure 16. Unclamped inductive load test circuit
diode recovery times

A A A L
D VD
fast 100 µH
G D.U.T. diode 2200 3.3
S B 3.3 1000 + µF µF VDD
B B
25 Ω D
µF + µF VDD ID
G D.U.T.
+ RG S
Vi D.U.T.
_
pulse width

AM01471v1
AM01470v1

Figure 18. Switching time waveform

Figure 17. Unclamped inductive waveform
ton toff
V(BR)DSS
td(on) tr td(off) tf
VD

90% 90%
IDM

10% VDS 10%

ID 0

VDD VDD VGS 90%

0 10%
AM01472v1
AM01473v1

DS9710 - Rev 4 page 7/12

 STF18N60M2
Package information

4 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

4.1 TO-220FP package information

Figure 19. TO-220FP package outline

7012510_Rev_13_B

DS9710 - Rev 4 page 8/12

 STF18N60M2
TO-220FP package information

Table 8. TO-220FP package mechanical data

mm
Dim.
Min. Typ. Max.

A 4.40 4.60
B 2.50 2.70
D 2.50 2.75
E 0.45 0.70
F 0.75 1.00
F1 1.15 1.70
F2 1.15 1.70
G 4.95 5.20
G1 2.40 2.70
H 10.00 10.40
L2 16.00
L3 28.60 30.60
L4 9.80 10.60
L5 2.90 3.60
L6 15.90 16.40
L7 9.00 9.30
Dia 3.00 3.20

DS9710 - Rev 4 page 9/12

 STF18N60M2

Revision history

Table 9. Document revision history

Date Revision Changes

04-Jun-2013 1 First release.

– Added: note 2 in Table 2
– Modified: typical value for Ciss, Coss eq., Qg, Qgs, Qgd
05-Jun-2013 2
– Modified: Figure 10 and 11
– Minor text changes
– Modified: note 1 in Table 2
28-Feb-2014 3 – Rthj-case value in Table 3
– Minor text changes
Modified Figure 8. Normalized gate threshold voltage vs. temperature,
Figure 9. Normalized on-resistance vs temperature and Figure 11. Normalized
19-Jun-2019 4 V(BR)DSS vs temperature.
Minor text changes.

DS9710 - Rev 4 page 10/12

 STF18N60M2
Contents

Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1 TO-220FP package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

DS9710 - Rev 4 page 11/12

 STF18N60M2

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DS9710 - Rev 4 page 12/12