5.

CMOS Inverter

Institute of
Microelectronic
Systems

Overview

• Logic levels
• Noise Margin
• CMOS Inverter
– static behaviour
– dynamic behaviour

Courtesy Quiller Electronics Limited

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5: CMOS Inverter Systems 2
 Inverter as simplest logic gate
V+
V
+ R

v v v
I O O
vI VO

V DD VCC

R R

v v
i O
i O
D C
VI
vI
vI
M Q
S S

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Logic Voltage Levels

VOL: Nominal voltage

corresponding to a low logic v
O
state at the output of a logic V
gate for vI = VOH. +
V
Generally V- ≤ VOL. OH Slope = -1

VOH: Nominal voltage

corresponding to a high logic
state at the output of a logic
gate for vI = VOL.
Generally VOH ≤ V+.
Slope = -1
VIL: Maximum input voltage that
will be recognised as a low V
OL
input logic level. v
NML NM I
VIH: Minimum input voltage that will 0 H
be recognised as a high input V- 0 V V V V V+
OL IL IH OH
logic level.
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 Noise Margins

vO vI
V+

"1"
NML: Noise margin associated with V OH "1"
a low input level NMH
VIH

NML = VIL - VOL Undefined

Logic State
NMH: Noise margin associated with
a high input level V IL

NM L
NMH = VOH - VIH "0"
VOL

"0"
V-

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Dynamic Response of Logic Gates

v
I
• Rise time tr: time required for the VOH
transition from V10% to V90%. 90%

• Fall time tf: time required for the 50% V +V

OH OL
transition from V90% to V10%. 2
10%
VOL
V10% = VOL + 0.1(VOH - VOL) (a) t
tr tf
V90% = VOL + 0.9(VOH - VOL)
vO
τ PHL τ PLH
VOH
• Propagation delay τP: difference 90%
in time between the input and V +V
OH OL
50%
output signals reaching V50%. 2
10%
VOL
V50% = (VOH + VOL)/2
(b) t 1 t t2 t3 t t4 t
τ PLH + τ PHL
f r

τP = Switching waveforms for an idealised inverter

(a) Input voltage signal (b) Output voltage waveform
2
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 MOS Inverter with Resistive Load

V =5V
DD
• NMOS switching device MS
designed to force vO to VOL R

v
• Resistor load R to pull the output O
up toward the power supply VDD i
D
+
• VOH = VDD (driver in cut off v M v
⇒ iD = 0) I S DS
• VOL determined by W/L ratio of
MS -

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Example

V = 5V V DD= 5V
DD i
DD

R R 95 k Ω

v =V =5V
O OH
v =V
O OL
0 50 µA
M +
S
M v = 0.25 V
S DS
2.06
1 -
v =V <V v =V =5V
I OL TH I OH
(a) (b)

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 On - Resistance
V V
DD DD

R R

VOH VOL

v = V OL v =V
I I OH

R on R on
(a) (b)

vDS 1 Ron 1
Ron = = VOL = VDD = VDD
iD W ⎛ v ⎞ Ron + R 1+
R
K 'n ⎜ vGS − VTN − DS ⎟ Ron
L ⎝ 2 ⎠

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Transistor Alternatives to the Load Resistor

VDD VDD
ML ML
+
vO vO
vI MS vI MS

(a) NMOS inverter with gate of the load (b) NMOS inverter with gate
device connected to its source of the load device grounded

V DD V DD
VGG
ML ML

vO vO
vI MS VI
MS

(c) Saturated load inverter (d) Linear load inverter

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 CMOS Inverter Technology
V (0 V) v V (5 V)
SS I DD

B S D vo D S B
p+ n+ n+ p+ p+ n+
n-well
Ohmic NMOS transistor
contact PMOS transistor Ohmic
contact
p-type substrate

C M O S T ra n sisto r P a ra m e te rs
N M O S D e vice P M O S D e vice
VTO 1 V -1 V
γ 0 .5 0 V 0 .7 5 V
2 φF 0 .6 0 V 0 .7 0 V
K' 25 µA /V 2 1 0 µA /V 2

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Complementary MOS (CMOS) Logic Design

VDD = 5 V VDD = 5 V
• Inverter with resistive S
load ⇒ power R onp
dissipation when the M
P
input is high. G
• If an NMOS and D v
I
PMOS transistor is v v
v O
I D O
used ⇒ CMOS.
• One transistor is G
M
N
always off while the
other is on ⇒ no S
R onn
static power
consumption.

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 CMOS voltage transfer Characteristic

VIL
1 2
4.0V M N off M N saturated
M P linear
v o = v I - VTP
vo M and M P saturated
N
2.0V 3

M P saturated
M N linear
VIH
v o= v I - VTN 5
0V 4 M P off
0V 1.0V 2.0V v 3.0V 4.0V 5.0V
I
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Regions of Operation of Transistors in a

Symmetrical Inverter

Region Input Voltage vI Output NMOS PMOS

Voltage vO Transistor Transistor

1 vI ≤ VTN VOH = VDD Cutoff Linear

2 VTN < vI ≤ vO + VTP High Saturation Linear

3 vI ≈ VDD/2 VDD/2 Saturation Saturation

4 vO + VTN < vI ≤ (VDD + VTP) Low Linear Saturation

5 vI ≥ (VDD + VTP) VOL = 0 Linear Cutoff

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 What happens, if the inverter is not
symmetrical?
6.0V 6.0V
VDD = 5 V
vO= vI
VDD = 4 V
4.0V 4.0V KR= 5
VDD = 3 V v O= vI
VDD = 2 V K R= 1
2.0V 2.0V

K R = 0.2

0V 0V

0V 1.0V 2.0V 3.0V 4.0V 5.0V 6.0V 0V 1.0V 2.0V 3.0V 4.0V 5.0V
vI vI

Symmetrical inverter (Kn = Kp) Asymmetrical inverter (KR = Kn / Kp)

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Calculation of VIL

Equating currents for saturated nMOS and nonsaturated pMOS device

(Region 2):
Kn
2
K
2
[
(Vin − VTn )2 = p 2(VDD − Vin − VTp )(VDD − Vout ) − (VDD − Vout )2 ]
The derivation condition (dVout / dVin) = -1 has to be evaluated for
IDn(Vin) = IDp(Vin , Vout):

dVout (dI Dn / dVin ) − (∂I Dp / ∂Vin )

= = −1
dVin ∂I Dp / ∂Vout
Evaluating the derivation gives:
⎛ K ⎞ K
VIL ⎜⎜1 + n ⎟⎟ = 2Vout + n VTn − VDD − VTp
⎝ Kp ⎠ Kp
This equation has to be solved together with the first equation ⇒ VIL
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 Calculation of VIH
At the point VIH the NMOS device is nonsaturated and the PMOS
transistor is saturated (region 4):

[ ] = p (VDD − VIH − VTp )

Kn K
2(VIH − VTn )Vout − Vout
2 2

2 2
The derivation condition (dVout / dVin) = -1 has to be evaluated for
IDn(Vin, Vout) = IDp(Vin):

dVout (dI Dp / dVin ) − (∂I Dn / ∂Vin )

= = −1
dVin ∂I Dn / ∂Vout
which gives:

⎛ K ⎞
VIH ⎜⎜1 + p ⎟⎟ = 2Vout + VTn + p (VDD − VTp )
K
⎝ Kn ⎠ Kn
This equation forms together with the first equation a quadratic in VIH
which has to be solved. Institute of
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5: CMOS Inverter Systems 17

Calculation of Vth

For Vth = Vin = Vout both transistors are

V IL Vin=Vout
saturated (λ is assumed to be 0): 1 2
4.0V
(Vth − VTn ) = (VDD − Vth − VTp )
Kn 2 Kp 2

2 2 vo
M N and M P saturated
Solving for Vth yields: 2.0V 3
VTn + K p / K n (VDD − VTp )
Vth = VIH
1+ K p / Kn 0V 4 5
0V 1.0V 2.0V 3.0V 4.0V 5.0V
vI

Vth

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 Design of CMOS inverter (I)

• NMH = VOH - VIH = VDD - VIH 4.0

• NML = VIL - VOL = VIL - 0 = VIL

Noise Margin (Volts)

3.5

• KR = Kp / Kn 3.0 NM
H

⎛W ⎞ 2.5
• Remember: K n = K 'n ⎜ ⎟
⎝ L ⎠n 2.0
⎛W ⎞
K p = K'p ⎜ ⎟ 1.5
⎝ L ⎠p
NM L
⇒Influence of the symmetry via 1.0
W/L of transistors!
0.5
0 1 2 3 4 5 6 7 8 9 10 11
KR

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Design of CMOS inverter (II)

Kp µ p (W L ) p
The ratio (W/L) in CMOS design is =
used to set the level of Vth. Kn µn (W L )n

The ratio required to establish a K n VDD − Vth − VTp

given inverter threshold voltage is: =
Kp Vth − VTn
To get a symmetrical voltage
K n 12 VDD − VTp
transfer curve, Vth is set to VDD/2: = 1
K p 2 VDD − VTn
If in a process |VTp| = VTn, the
(W L ) p µn
device aspect ratios for a =
symmetrical inverter are related by: (W L )n µ p
Since µn / µp ≈ 2.5, a minimum area CMOS inverter will have (W/L)n ≈ 1 and
(W/L)p ≈ 2.5. In this case the voltage transfer function is completely symmetric.

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 Summary

So what did we accomplish until

V IL
now?
1 2
4.0V
• We know how a CMOS inverter
vo works.
2.0V
• VOL, VOH - do you still know it?
3
• We know how to set the W/L ratios
of the transistors to get optimal
VIH
noise margins.
0V 4 5 • So we make every inverter the
0V 1.0V 2.0V 3.0V 4.0V 5.0V same, that is to say minimal -or?
vI

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Dynamic Behavior of the CMOS Inverter

High to Low Output Transition (I)

MN goes from Cutoff over Saturation into Nonsaturation region for the given
input.
The border between Saturation and Nonsaturation is reached at the time tx
and the output voltage Vout = VOH - VTn v
I

V DD = 5 V + 5V

MP
0V t
v I = 5V v O (0+) = 5V 0
v
O
MN C MN saturated
VOH = 5V
MN nonsaturated
(Vin - VTn)
VOL = 0 V t
t1 tX t2

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 High to Low Output Transition (II)

In order to simplify the final expressions, the dQ dV

i= = COUT OUT
integrations on the right for computing tHL are dt dt
done with the borders from VDD to V0 dV
(V1 = 0,9 VDD, V0 = 0,1 VDD) ∫ dt = COUT ∫ iOUT

Saturation:
VDD −VTn
dVOUT 2CoutVTn
t x − t1 = −COUT ∫ =
K n (VDD − VTn )
2
VDD
Kn
(VDD − VTn )2
2
Nonsaturation:
V0
⎛ ⎞
V0
dVOUT 2C 1 VOUT
t 2 − t x = −COUT ∫ = − OUT ln⎜⎜
K n 2(VDD − VTn ) ⎝ 2(VDD − VTh ) − VOUT
⎟⎟ =
Kn
VDD −VTn
2
[
2(VDD − VTn )VOUT − VOUT
2
] ⎠ VDD −VTn

COUT ⎛ 2(VDD − VTn ) ⎞

= ln⎜⎜ − 1⎟⎟
K n (VDD − VTn ) ⎝ V0 ⎠
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High to Low Output Transition (III)

dx 1 ⎛ xn ⎞
We have used the following integral: ∫ x a + bx n = an ln⎜⎜⎝ a + bx n ⎟⎟⎠
( )
dx 1 ⎛ x ⎞
In our case: n = 1, b = −1 ∫ ax − x 2
= ln⎜ ⎟
a ⎝a−x⎠

t HL = (t x − t1 ) + (t 2 − t x )
⎡ 2VTn ⎛ 2(VDD − VTn ) ⎞⎤
therefore: t HL = τ ⎢ + ln⎜⎜ − 1⎟⎟⎥
V − V
⎣ DD Tn ⎝ V 0 ⎠⎦

COUT
where τ=
K n (VDD − VTn )

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 Low to high output transition

From symmetry (VTn → VTp; Kn → Kp) follows for the high to low transition

( )
time:
⎡ 2 VTp ⎛ 2 VDD − VTp ⎞⎤
+ ln⎜ − 1⎟⎥
COUT
⇒ t LH = ⎢
K p VDD − VTp ⎢VDD − VTp
⎣
⎜
⎝( V0 ) ⎟⎥
⎠⎦

V =5V
DD v
I

+ 5V
MP

0V t
V =0V
I 0
v (0+) = 0V
O v
O
M C
N + 5V

0V t
0

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Dynamic Behavior of the CMOS Inverter

(cont’d)
• The choice of size of the NMOS and PMOS transistors can be dictated by the
desired average propagation delay τP
t PHL + t PLH
• For symmetrical inverter: τP = = t PHL = t PLH Kn' ≈ 2.5 K p'
2
tr = t f = 2τ P
Example:
VDD= 5 V
V DD= 5 V V DD= 5 V

M 5 32.5
P 1 M M 20
P 1 P 1
v v v v
I o I v I v
o o

M 2 13 8
N C M M
1 N 1 N 1
1 pF 2 pF

(a) (b)

Symmetrical reference inverter Scaled inverters

| VTP | = VTN = 1V τP = 6.4 ns a) τP = 1 ns b) τP = 3.2 ns
C = 1 pF tr = tf = 12.8 ns
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 Power Dissipation
6.0V
• Two kinds of power
dissipation in digital Output Voltage
electronics: 40uA

– static power dissipation 4.0V

(logic gate output is
stable)
– dynamic power
20uA
dissipation (during 2.0V
switching of logic gate)
Drain Current
• With CMOS nearly no static
power dissipation! 0V 0A >>
0V 2.0V vI 4.0V 6.0V

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Dynamic Power Dissipation (I)

R1 Switch closes at t = 0

Power dissipation due to charge and

discharge of capacitances i(t) Non-linear +
Resistor C
The total energy ED delivered by the V + vc (t)
DD
source is given by -
∞
-
ED = ∫ P(t )dt (a) vc (0) = 0
0

The power P(t) = VDDi(t), and because The current supplied by source VDD is
VDD is a constant, also equal to the current in capacitor C,
and so ∞ dv
∞ ∞
ED = VDD ∫ C C
dt
ED = ∫ VDD i (t )dt = VDD ∫ i (t )dt dt
0

0 0 VC ( ∞ )
= CVDD ∫ dvC
VC ( 0 )

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 Dynamic Power Dissipation (II)

Integrating from t = 0 to t = ∞, with The total energy ETD dissipated in

VC(0) = 0 and VC (∞) = VDD results in the process of first charging and
then discharging the capacitor is
ED = CVDD
2 equal to

We know that the energy Es stored in

⎛ CVDD
2
⎞ ⎛ CVDD
2
⎞
capacitor C is given by ETD = ⎜⎜ ⎟⎟ + ⎜⎜ ⎟⎟
2
CVDD ⎝ 2 ⎠Charge ⎝ 2 ⎠ Discharge
ES = = CVDD
2
2
and thus the energy EL lost in the
resistive element must be
2
CVDD
EL = ED − ES =
2
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Dynamic Power Dissipation (III)

Thus, every time a logic gate goes through a complete switching cycle, the
transistors within the gate dissipate an energy equal to ETD. Logic gates
normally switch states at some relatively high frequency (switching
events/second), and the dynamic power PD dissipated by the logic gate is
then

PD = CVDD
2
f

In effect, an average current equal to (CVDDf) is supplied from the source

VDD.

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 Dynamic Power Dissipation (IV)

• Power dissipation due to the “short circuit current” (when both transistors
are on during transition)
• The short circuit current reaches a peak for Vin = Vout = VDD/2
VDD = 5 V
5.0 V
vO
Voltage

R onp
Vin = Vout = VDD/2
vI
0.0 V vout
30uA
i DD
Current

R onn

0 uA
0s 4ns 8ns 12ns 16ns
Time
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Summary
Let’s repeat:
6.0V
• What is the dynamic behaviour of
Output Voltage
40uA the inverter?
4.0V • What do we need it for?
• What kind of power dissipation is
there?
20uA
2.0V • What kind of power dissipation is
dominant with CMOS logic?
Drain Current

0V 0A >>
0V 2.0V v 4.0V 6.0V
I

PD = CVDD
2
f
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