Programmable Logic Array

Dr. Mohammed Najm Abdullah

Why Programmable Logic?

• Facts:
– It is most economical to produce an IC in large volumes
– Many designs required only small volumes of ICs
• Need an IC that can be:
– Produced in large volumes
– Handle many designs required in small volumes
• A programmable logic part can be:
– made in large volumes
– programmed to implement large numbers of different
low-volume designs

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Programmable Logic - More Advantages

• Many programmable logic devices are field- programmable, i. e.,

can be programmed outside of the manufacturing environment
• Most programmable logic devices are erasable and
reprogrammable.
– Allows “updating” a device or correction of errors
– Allows reuse the device for a different design - the ultimate in re-usability!
– Ideal for course laboratories
• Programmable logic devices can be used to prototype design that
will be implemented for sale in regular ICs.
– Complete Intel Pentium designs were actually prototyped with specialized
systems based on large numbers of VLSI programmable devices!

Programming Technologies
• Programming technologies are used to:
– Control connections
– Build lookup tables
– Control transistor switching
• The technologies
– Control connections
• Mask programming
• Fuse
• Antifuse
• Single-bit storage element

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 – Build lookup tables
• Storage elements (as in a memory)
– Transistor Switching Control
• Stored charge on a floating transistor gate
– Erasable
– Electrically erasable
– Flash (as in Flash Memory)
• Storage elements (as in a memory)

Technology Characteristics
• Permanent - Cannot be erased and reprogrammed
• Mask programming
• Fuse
• Antifuse
• Reprogrammable
– Volatile - Programming lost if chip power lost
• Single-bit storage element
– Non-Volatile
• Erasable
• Electrically erasable
• Flash (as in Flash Memory)

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 Programmable Configurations
• Read Only Memory (ROM) - a fixed array of
AND gates and a programmable array of OR
gates
• Programmable Array Logic (PAL) - a
programmable array of AND gates feeding a fixed
array of OR gates.
• Programmable Logic Array (PLA) - a
programmable array of AND gates feeding a
programmable array of OR gates.
• Complex Programmable Logic Device (CPLD)
/Field- Programmable Gate Array (FPGA) -
complex enough to be called “architectures” - See
VLSI Programmable Logic Devices reading supplement

ROM, PAL and PLA Configurations

Fixed Programmable Programmable
Inputs AND array OR array Outputs
(decoder) Connections

(a) Programmable read-only memory (PROM)

Programmable Programmable Fixed

Inputs Outputs
Connections AND array OR array

(b) Programmable array logic (PAL) device

Programmable Programmable Programmable Programmable

Inputs Outputs
Connections AND array Connections OR array

(c) Programmable logic array (PLA) device

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Read Only Memory
• Read Only Memories (ROM) or Programmable Read
Only Memories (PROM) have:
– N input lines,
– M output lines, and
– 2N decoded minterms.
• Fixed AND array with 2N outputs implementing all N-
literal minterms.
• Programmable OR Array with M outputs lines to
form up to M sum of minterm expressions.

• A program for a ROM or PROM is simply a multiple-

output truth table
– If a 1 entry, a connection is made to the
corresponding minterm for the corresponding
output
– If a 0, no connection is made
• Can be viewed as a memory with the inputs as
addresses of data (output values), hence ROM or
PROM names!

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Read Only Memory Example
• Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines)
• The fixed "AND" array is a
“decoder” with 3 inputs and 8 X X
D7 X
outputs implementing minterms. D6
• The programmable "OR“ D5 X
X
X
D4
array uses a single line to A A2 D3 X
represent all inputs to an B
D2
A1 D1 X X
OR gate. An “X” in the C A0 D0 X
array corresponds to attaching the
minterm to the OR
• Read Example: For input (A2,A1,A0)
= 011, output is (F3,F2,F1,F0 ) = 0011.
F3 F2 F1 F0
• What are functions F3, F2 , F1 and F0 in terms of (A2, A1, A0)?

Programmable Array Logic (PAL)

• The PAL is the opposite of the ROM, having a
programmable set of ANDs combined with fixed ORs.
• Disadvantage
– ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
• Advantages
– For given internal complexity, a PAL can have larger N and M
– Some PALs have outputs that can be complemented, adding
POS functions
– No multilevel circuit implementations in ROM (without external
connections from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.

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Programmable Array Logic Example
AND gates inputs
0 1 2 3 4 5 6 7 8 9
X
Product 1
term
X X
2 F1

I 15 A
X X X
4
X X
5 F2
X X
6

I2 5 B
X X
7
X X
8 F3
X
9
I3 5 C
X X
10
X X
11 F4
X
12
I4
0 1 2 3 4 5 6 7 8 9

Programmable Logic Array (PLA)

• Compared to a ROM and a PAL, a PLA is the most
flexible having a programmable set of ANDs
combined with a programmable set of ORs.
• Advantages
– A PLA can have large N and M permitting implementation
of equations that are impractical for a ROM (because of
the number of inputs, N, required
– A PLA has all of its product terms connectable to all
outputs, overcoming the problem of the limited inputs to
the PAL Ors
– Some PLAs have outputs that can be complemented,
adding POS functions

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 • Disadvantages
– Often, the product term count limits the application of a
PLA.
– Two-level multiple-output optimization is required to
reduce the number of product terms in an
implementation, helping to fit it into a PLA.
– Multi-level circuit capability available in PAL not available
in PLA. PLA requires external connections to do multi-level
circuits.

Programmable Logic Array Example

A
 What are the equations for F1 and F2?
B  Could the PLA implement the
functions without the XOR gates?
C
X X 1 X X AB

X X 2 X BC X Fuse intact
Fuse blown
X X 3 X AC

X X 4 X AB
X 0
C C B B AA
X 1
• 3-input, 3-output PLA F1
with 4 product terms
F2

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9
 Read Only Memory (ROM)
• “Permanent” binary information is stored
• Non-volatile memory
– Power off does not erase information stored

K-bit address ROM

N-bit Data Output
lines 2k words
K N
N-bit per work

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32x8 ROM
32x8 ROM
5 8
Each
represents
A4 0 32 wires
1
A3 2
5-to-32 3
A2
Decoder
A1
28
A0 29
30
31

Fuse can be
implemented as
a diode or a D7 D6 D5 D4 D3 D2 D1 D0
pass
20 transistor

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 Programming the 32x8 ROM
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 1
0 0 0 0 1 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 1 1 0 0 0 0
… … … … … … … … … … … … …
1 1 1 0 1 0 0 0 1 0 0 0 0
1 1 1 1 0 0 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1 0 0 0 0 1

A4 0
1
A3 2
5-to-32
A2
A1 Decoder

A0 29
30
31

D7 D6 D5 D4 D3 D2 D1 D0 21

Example: Lookup Table

• Design a square lookup table for F(X) = X2 using ROM

X F(X)=X2 X F(X)=X2
0 0 000 000000
1 1 001 000001
2 4 010 000100
3 9 011 001001
4 16 100 010000
5 25 101 011001
6 36 110 100100
7 49 111 110001

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 Square Lookup Table using ROM

0
X F(X)=X2 1
X2 3-to-8 2
000 000000
001 000001 X1 3
Decoder 4
010 000100
X0 5
011 001001
6
100 010000
7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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Square Lookup Table using ROM

0
X F(X)=X2 1
X2 3-to-8 2
000 000000
001 000001 X1 3
Decoder 4
010 000100
X0 5
011 001001
6
100 010000
7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0
Not Used = X0

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 Square Lookup Table using ROM

0
X 2
F(X)=X
1
X2 3-to-8 2
000 000000
X1 3
001 000001 Decoder 4
010 000100 X0 5
011 001001 6
100 010000 7
101 011001
110 100100
111 110001
F5 F4 F3 F2 F1 F0

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Classifying Three Basic PLDs

Programmable
Connections
Fixed AND plane Programmable
INPUT (decoder) OR plane
OUTPUT

(Programmable) Read-Only Memory (ROM)

Programmable
Connections
Programmable Programmable
AND plane OR plane
INPUT OUTPUT

Programmable Logic Array (PLA)

Programmable Fixed F/F

INPUT AND plane OR plane
OUTPUT
Programmable Array Logic (PAL) Devices
PAL: trademark of AMD, use PAL as an adjective or
26 expect to receive a letter from AMD’s lawyers

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 Programmable Logic Array (PLA)
A Programmable
OR Plane
B

Programmable
AND Plane

C C B B A A

F2
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Example using PLA

F1(A, B, C)   m(0,1,2,4)
F2(A, B, C)   m(0,5,6,7)

F1  A B  AC  BC
F1  AB  AC  BC

F2  AB  AC  A BC
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 Example using PLA
A F1  AB  AC  BC
B F2  AB  AC  A BC
C
AB

AC

BC

ABC

C C B B A A

F1
F2
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16
17
18
 A A B
PAL Device
B IO1 IO2 IO1 IO1

Programmable IO1
AND Plane

IO2

Fixed
OR Plane

38

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 PAL Device Design Example
A A B B C C D D IO1 IO1

IO1

Not programmed
A

IO2

IO1  ABC  A BCD

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IO2  ABC  A BCD  ACD  A BCD

CPLD and FPGA [Brown&Rose 96]

• Complex Programmable Logic Device (CPLD)
– Multiple PLDs (e.g. PALs, PLAs) with programmable
interconnection structure
– Pioneered by Altera
• Field-Programmable Gate Array (FPGA)
– High logic capacity with large distributed interconnection
structure
• Logic capacity  number of 2-input NAND gates
– Offers more narrow logic resources
• CPLD offers logic resources w/ a wide number of inputs (AND planes)
– Offer a higher ratio of Flip-flops to logic resources than CPLD
• HCPLD (High Capacity PLD) is often used to refer to both
CPLD and FPGA

40

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 CPLD structure
Logic block

PLD PLD PLD PLD I/O block

Interconnects

PLD PLD PLD PLD

41

FPGA Structure
Logic block

I/O block

Interconnects

42

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 FPGA Programmability
• Floating gate transistor
– Used in EPROM and EEPROM
• SRAM-controlled switch  Control
– Pass transistors
– Multiplexers (to determine how to route inputs)
• Antifuse
– Similar to fuse
– Originally an Open-Circuit
– One-Time Programmable (OTP)
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