University of Technology Computer Engincering and Information Techaology Department Final Examinations for Year 2010/2011 1 Systems Design Class: r. Mohammed Najm Abdullah . Time allowed: 180 min. pbs Coe Conall SN.geall C9 ih pple Ald esi OE Capls Aad Qe a) For the following function: LOW, X,Y Z)> En 43.6.7.9,11.1213,14,15), 1, Write fas a standard Product of sums. 2. Draw the Karough map for f 3. Group the 1's on the K- map and find the Prime implicants (P1) and the Essential Prime Implicants (EPI). 4. Wsite Cas a minimum Sum of Products 5.Draw the logic circuit for f. b) Consider a Fall Subtractor (FS) Logic model 1. Determine the truth table for FS 2. Implement FS using programmable logic array (PLA) 3. Implement FS using Read only Memory (ROM) ‘ ' [18 Mark] Qu 2) An 8o-] multiplexer has inputs A, B and C connected to the selection inputs 82. $I and $0, respectively. The data inputs lp through ly, are as follo bh=0; = 14 =D! and Ig = D. Determine the Boolean function that the multiplexer impternents 1. Draw the simplified form of the Boolean function F(4,B,C,D) using NOR gates only. 2. Implement the function F(A,B,C,D) using 2-to-4 decoders and an external OR gate. 3. Implement the function F(A,B,C,D) using two 4-to-1 multiplexers with an external OR gate. b) You need to build an adder that can add two binary numbers each representing a deeimal number up to (1000)i0 1. How many bits should this adder have? 2. How many 4-bit adders are required to build this adder? 3. Build this adder using 4-bit adders. Draw the block diagram and specify ALL the inputs and outputs. ! ) [18 Mark] Qs: a) Obtain SR-FF from D-FF, find the truth table then minimize the excitation equation and realize the minimized expression. b) Determine the prime implicants and essential prime implicants using tabular method (Quine McCluskey method)for the following switching function: F(X1, x2, Xa, Xa) =D M4, 5, 6, 8, 9, 10, 13) + d(0, 7, 15) [18 Mark] Qu a) Determine the odd parity bit generated when the message consists of ten decimal digits in 3321 code then design the logic circuit using NAND gates only by You need to design a synchronous counter that counts in the following decimal sequence: 023456574543 515052R5... 1, How many states does this counter have? ! ' 2. How many flip flops are required to build this counter? 3. Draw the state diagram for this circuit 4, If J-K flip flops are to be used, write the excitation equation for the flip flops inputs. 5, Draw the logic circuit for this counter. [18 Mark}Qs: Multiple Choice Questions (Rha! Sigal Ma te Ga) 1, Accorrect output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the: A. clock is LOW B. slave is transferring C. flip-flop is reset D. clock is HIGH 2. The half adder has: A. three inputs and two outputs C. 6wo inputs and three outputs B. three inputs and three outputs D. two inputs and two outputs 3. Which of the following is a universal gate? () AND (1) NAND (il) NOR A.(D only B. (I) only C. (1) and (111) only —_‘D. (I) and (11) and (111) : ~_AB 4. The minimal Product of Sums for f shown in the K-map is: CD00 O11 10 A. C+D B. cD CA+B DA oo Es Ts ots o Ps pps fx u x fo] s 5. Which device has one input and many outputs 10 vt be A. flip flop B. multiplexer C. demultiplexer ‘D. counter 6 U22)5= A. (52)10 B. (84)10 C.(S2)ncv D.(84)acv 7. The simplest register is: A. buffer register B. shift register C. controlled buffer register D. bidirectional register 8. Ina 7 segment display the segments a,¢,d,f.g are lit. The decimal number displayed will be ALS B.9 C4 D.2 , 9. A decade counter skips A. binary states 1000 to Ht B. binary states 0000 to 0011 C. binary states 1010 to 1111 D. binary states 1111 and higher 10. Two 16:1 and one 2:1} multiplexers can be connected to form a B. 32:1 multiplexer C. 64:1 multiplexer D.8:1 multiplexer 11. (D3 ie~ CIE jie = A. (B5)i6 B. (5B)i6 C.(CE)6 D. (CF jis 12. A counter has 4 flip flops.{t divides the input frequency by Ad B.2 C8 D.16 13.A flip flop isa A. combinational circuit B. memory clement —_C. arithmetic element _D, memory or arithmetic 14. 111+ ’ ALOT B.111111, C0112 D.101110; 15. The result of (1@ Z @ Z ), using the rules of Boolean algebra, is: AZ BZ co D1 16. Numbers are stored and transmitted inside a computer in A. binary form B. ASCII code form C. decimal form D. alphanumeric form {16 Mark} Wishing you all the successdo | ial ape EP Ay ta a) eee ~FGiingy,2)= | [(Os2)4,,5, 8,10 a — I rr | Lae r7) hE | | Prop rrp ere pr op pte| = Ae TO 2 Ss So5.S4 Sg S25i Se | | } | a = na 42 Mig NX se My iy10algo dodt ts I ry 4 Ply yh]No. of states -8 Nos EFS a= 1we. of staho= 2 Q>G) Ik