IEEE TRANSACIIONS ON CIRCUITS AND SYSTEMS, VOL. 35, NO.

NOVEMBER

z-Domain Model for Discrete-Time PLL's

JERRELL P. HEIN, MEMBER, IEEE, AND JEFFREY W.SCOTT

Ah*# sAmain-The for continuous-time comparing the continuous- and discretetime models with
(PU's) a fundamental t d for linearized of a PLL timestep simulator, and actual measured devices. In
systems For PLL's inputs md
dmtetime aodel reuIptdy In Appendix the assumptions needed linearize the net-
this -
em is -bed for obtaining an accurate z-domain work analysis will be discussed and it will be shown that
of a dlscrrte-tlne PU, method is an alternative rppmsch these assumptions are identical to those required to ana-
to the in modeling technqw transforms lyze the PLL with the use of linearized difference equa-
of the PU directly into the r-domain, requiring tions. Finally, in Appendix B, the analysis methodology
only manipulations even loop filters.
This methodology is for simple loop measure-
will be extended to PLL's with switched capacitor loop
mnts from digital interface (DSI) integrated circuit are used filters.
to analysis results for a mom
I&e z-domain rltllough incrementally 11. DISCRETE-TIME
MODELDEVELOPMENT
the $-domain to be more accurate,
cspocisny freqwndcz. A. Continuous-Time PLL's and the s-Domain Model
functional block diagram for a continuous-time PLL
I. INTRODUCTION is shown in Fig. 1. The block diagram of the associated
s-domain PLL model is shown in Fig. 2. This model
T HE basic s-domain PLL model presented in numer-
ous texts [1]-[3] treats a loop in the locked condition
as a linear continuous-time system. The input and output
assumes that the input waveform is phase modulated
sine wave, i.e., it has the form,
waveforms are assumed to be sinusoidal and the phase
sa( t ) a-sin t
detector is modeled as a linear analog multiplier with an
inherent ideal low-pass filter. Although the linear continu- The input phase modulation +,(r), and oscillator output
ous-time model is useful within these constraints, many t ) are continuous functions of time.
PLL's operate under conditions not accurately represented In Fig. the summing node and K p gain block repre-
by these assumptions. In particular, a large class of PLL's sent the operation of the phase detector in the frequency
used most notably in data communications have digital domain. The phase detector is assumed to be a linear
waveforms as both inputs and outputs. For these PLL's, analog multiplier which multiplies the input and output
the phase information is contained in the digital waveform waveforms. The result is a multifrequency signal which
transitions and should be viewed as a discrete-time se- contains the phase difference information desired
quence. The linear, continuous-time model can approxi- in the low frequency portion of the phase detector
mate the operations of these loops only if the jitter fre- output spectrum. The higher frequency multiplicative
quencies of interest much less than the incoming data products are ignored in the analysis. The effect of this last
transition rate. assumption can be included by assuming that an ideal
To obtain an accurate discrete-time model of a PLL, one low-pass filter sits behind the multiplier. In practice, the
can write the complete set of differential equations describ loop filter following the phase detector approximates this
ing the system, convert these into difference equations, ideal filter.
linearize the equations along the way, and finally z-trans- Finally, the loop filter (F(s)) and voltage-controlled
form the result to obtain H ( r ) , the z-domain jitter transfer oscillator ( K , / s ) are included in the block diagram.
function. This procedure quickly becomes cumbersome for In general, the loop filter is modeled accurately as
all but the simplest loop filters as noted by Gardner linear continuous-time element, especially if it is imple-
In this paper, a z-domain description for a PLL is mented with passive components. Relaxation and current
presented which is incrementally more complicated ramping oscillators exhibit linear and wideband voltage-
than the linear continuous-time model. The model uses the to-frequency relationships and are accurately modeled
impulse invariant transformation to convert the s-domain as linear continuous-time elements.
description of a portion of the loop directly into the The jitter transfer characteristic for the s-domain model
z-domain. In addition the model derivation and imple- is also shown in Fig. 2. H ( j ) will be used to compare the
mentation for a simple loop filter, results will be shown accuracy of the s- and z-domain models in a later section.
The assumption inherent in the application of the s-
Manuscript recdvcd October 16, 1987; revised March 18, This domain model to a PLL are generally valid for loops
pa r mmmcndcd b Editor T. operating with sinusoidal inputs and outputs (continuous-
K e wrhors Loboratoria, PA
EEE Log Number 8823450. time PLL's). It will be shown, however, that for PLL's

0098-4094/88/11100-1393$01.00 01988 IEEE

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 IEEE TRANSACTIONSON AND VOL. 35, NOVEMBER

Fig. F u n c t i d block diagram for continuous-time PLL.

Fig. 4. Digital phase detector operation.

BOW I b

8
data pattern (as shown in Fig. would have T =
l/(recovered clock frequency.
For small phase errors, the pulses driving the loop filter
Fs model block diagram. can be modeled accurately as weighted impulses. The
accuracy of this approximation is calculated in Appendix
A for a simple RC loop filter. The phase detector samples
operating with digital inputs and outputs (discretetime
the difference between the data and clock phases at inter-
PLUS), some of the assumptions may result in significant vals of T seconds and drives the loop filter with weighted
inaccuracies in the analysis. In these cases, it is necessary
impulses. The gain factor K p simply represents the conver-
to develop a discretetime model which more accurately
sion factor between input phase error and output impulse
reflects the actual operation of the loop.
area. Therefore, the digital phase detector in a discrete-time
PLL can be modeled as a summing node and gain block in
B. Discrete-Time PLL.3 and the z-Domain Model
the z-domain. Note that the type of blocks required
The functional block diagram for a discrete-time PLL is model the digital phase detector in the t-domain are the
shown in Fig. 3. The input waveform to the PLL can be same type of blocks used to model the analog phase
described detector in the s-domain.
With the digital phase detector now properly modeled in
the z-domain, the problem remaining is the accurate mod-
eling of the continuous-time loop filter and VCO elements
where sgn is the signum function. The difference between in the z-domain. For arbitrary signals driving the loop
the discrete- and the continuous-time PLL structures lies filter and VCO,it would be impossible to accurately map
in the implementation of the phase detector. The phase the elements' entire s-domain response into the zdomain.
detector for a discrete-time PLL is a digital circuit which But the loop filter and VCO are not being driven by
drives a pulse width modulated digital pulse into the loop arbitrary signals, they are being driven by a series of
filter. The width of the pulse is determined by the time weighted impulses from the phase detector. Therefore, it is
difference between the input data reference edge and the only necessary to preserve the loop filter and VCO's im-
recovered clock edge. The digital phase detector operation pulse response in transforming from the s- to z-domain. In
is depicted in Fig. Phase difference information arrives other words, the essential characteristics of the loop filter
at the phase detector input only when data reference edges and VCO will be preserved if the derived discrete-time
occur. Therefore, the phase error between the data and network has a unit impulse response with values equal T
clock is properly viewed a discrete-time sequence with spaced samples of the continuous-time impulse response.
values spaced at intervals approximately equal the time A transformation exists which guarantees exactly this type
between input data reference edges. For a repetitive data of relationship- the impulse invariant transformation.
pattern, time interval between data pulses is given by: Fig. illustrates the relationship guaranteed by the
T l/(recovered clock frequency-input data one's den- impulse invariant transformation. Given a continuous-time
sity). For example, a repetitive return-to-zero (RZ) network with impulse response h , ( t ) , thc impulse invari-

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HEIN AND SCOTT: Z -DOMAIN MODEL FOR PU’S

(2) transformation of the loop filter and VCO s-domain

descriptions into the z-domain using the impulse invariant
transformation. The model accurately represents the oper-
ation of the digital phase detector with digital data and
clock inputs, and correctly transforms the continuous-time
networks F(s) and K o / s into the r-domain. The applica-
tion of this technique to a second-order PLL will be
demonstrated in the next section.
C. Application of z-Domain Model a Second-Order PLL
In this section, the zdomain analysis will be performed
on a discrete-time PLL with a first-order loop filter. For
comparison purposes, the classical s-domain model of this
PLL will be described first.
4( The s-domain PLL model is shown in Fig. 2. first-order
transimpedance loop fiiter transfer function F(s),(see Fig.
Fig. 5. Impulse invariant transformation. 11) is given by

where R and C are the series resistance and capacitance of

the loop filter. Using this filter transfer function in the
expression for H ( s ) shown in Fig. yields the following
jitter transfer characteristic:
1
r l -
RC
H,(s ) RK,Kp
KoKp
RKoKps

where the subscript denotes the continuous-time na-

ture of the jitter transfer expression; K O is the voltage-to-
frequency conversion gain of the VCO; and K p is the
F(@ phase detector conversion gain given by
3
Kp dIP/2r
Fig. 6. Z-domain model block diagram.
where d is the one’s density of the PLL input data and I,,
is the magnitude of the phase detector pump current.
ant transformed discrete-time network will have a unit The loopgain expression required for root locus con-
sample response h [ n ] where the h [ n ] values are equal to
struction is given by
the h , ( t ) values sampled at intervals of T seconds The
actual transformation of some function F(s) to F ( z ) is a KO
loopgain K p . .F(s)
straightforward process which will be demonstrated in a
later section. Basically, the function F(s) must be divided 1
using partial fraction methods into simple irk) and
l/s2 terms. Each of these terms then transforms directly
into the r-domain. Poles at sk in the s-domain map to
poles at zk eQTin the rdomain. Zeros in the s-domain where K is defined as
move to points in the z-plane which depend on the pole K K,KpR.
locations. Because the impulse-invariant transformation is
not an algebraic mathematical mapping, the combined The root locus for the PLL modeled in the s-domain is
loop filter and VCO s-domain terms (K,F(s)/s)must be shown in Fig. 7. There are two open loop poles at the
transformed together. origin of the s-plane and one open loop zero at s =l/RC.
Once the loop filter and VCO are transformed into Note that, since the loopgain parameter K contains the
F ( r ) , the entire loop can be evaluated in the z-domain. one’s density information, the closed-loop pole locations of
The z-domain model is shown in Fig. 6 along with the the s-domain jitter transfer model depend on the input
jitter transfer characteristic H( The development of the data pattern. However, it is of further interest to note that
complete discrete-time PLL model involves only two steps: the s-domain model never predicts an unstable loop for
(1)calculation of the phase detector gain constant K p , and any combination of PLL parameters.

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 IEEE TRANSACTIONSON cincuirs AND SYSTEMS. VOL. 35. NO. NOVEMBER

I
U

Fig. S-domain root locus.

The discrete-time or z-domain analysis of the second-

order PLL begins by applying the impulse invariant trans- Fig. Z-domain root locus.
formation to the term KoF( For the first order loop
filter under investigation, this term is given by
Using this transformed filter/VCO transfer function in the
1 expression for H(z) shown in Fig. yields the following
S+-
KO RC jitter transfer characteristic:
. F ( s ) RK,-
S S2
KoKpR z(2-a)
Hd(z) 1 K,K,R 2- a K , K p R 1
Z+
1 KoKpR KoK,R
The impulse response of this section of the PLL is found
by taking the inverse Laplace transform, which yields where the subscript "d denotes the discrete-time nature
KO
of the jitter transfer expression, and K p is the phase
h,(Z)=-[r+ RC]u(t). detector conversion gain given by
The impulse-invariant property requires that IP
h [ n ]= h , ( n T ) 2TfVCO
where I,, is the magnitude of the phase detector pump KO
=--[nT+ RC]u[n]
C ' current.
where T is the effective sampling or impulse arrival rate The loopgain expression required for z-domain root
given by T = l / d f , where d is the one's density of the locus construction is given by
incoming data and f, is the VCO recovered clock fre-
quency. The desired z-domain description of the loop filter loopgain K p - F (t)
and VCO is found by taking the z-transform of h [ n ] (the z(z-a)
nT-U [n] term is most easily transformed by invoking the K-
differentiation property), which results in the following (Z4)*
expression for F(z):
where the loopgain parameter K is again defined as
TI-' RC K,KpR.
F(.)=X"[ The root locus for the PLL modeled in the z-domain is
c shown in Fig. 8. There are two open loop poles at z 1
and open loop zeros at z 0 and z a. It is interesting
RKo +-cl-;)] note that, since the open-loop zero location is a func-
tion of the input data one's density, the z-domain model
can predict unstable loop performance for the condition of
For simplification, let a 1 ( T / R C ) . Then T 2RC (in which an open-loop zero resides on the
Z(L - a ) negative real axis outside the unit circle).
F( Z ) RKo- For T e RC, the quantity a is close unity. In this
(Pl)* case, the z- and s-domain models predict similar jitter

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HEIN AND SCOlT: 2-DOMAIN W D E L FOR PLL'S 1397

transfer characteristics for jitter frequencies within the I I I I I 1 I 1 1

loop's bandwidth. Mathematically, the reason is that mini-

mal aliasing occurs as the loop filter/VCO s-domain
transfer characteristic is transformed to the z-domain;
physically, the results predicted by the two models con-
verge in this because the s-domain assumption con-
cerning the ability of the loop filter to reject phase detector
high frequency output energy is valid. The two models
diverge for jitter frequencies outside the loop's bandwidth
where the z-domain analysis correctly models the repeti- (0.1
-3
tive nature of the input/output jitter spectra. For wider
bandwidth loops, the z- and s-domain models will diverge
even for jitter frequencies within the loop's bandwidth. (OK 1 OOK
The reason is that the relatively wideband loop filter does
not reject high frequency phase detector components as Fig. lIf([)l using simulators.
the s-domain approximation would suggest. In the next
section, it will be that the and z-domain models
begin to diverge for jitter frequencies within the loop's
bandwidth for practical PLL's. The two models will also
be compared with experimental results taken from the DSI
(Digital Signaling Interface) integrated circuit.

111. MEASURED RESULTS

In the design of the wideband PLL used for clock
recovery in the DSI device, three modeling techniques were
used to estimate loop performance. The jitter transfer
characteristic was derived using both the linear and
z-domain models presented in this paper. In addition, a
timestep simulator was written in Fortran which per- 1K (OK
formed a transient analysis on the loop in the locked
condition using time domain models of the loop elements. Fig. 10. comparisons using measured data.
The timestep simulation was thought to be the most accu-
rate of the three methods because it included a number of were then entered into both the and z-domain models
nonlinear effects in the element models. For example, in and H(/)was calculated in both cases. The results were
the timestep simulator, the output of the phase detector compared with the measured H(f)for the device under
was treated as finite width pulse, instead of a weighted test. The measured H(f)is defined to be the output jitter
impulse and the finite pull range of the VCO was taken amplitude (peak-to-peak) at the input jitter frequency di-
into account. vided by the input jitter amplitude (pk-pk). Fig. 10 shows
The nominal design parameters were entered into each the three curves. It is that the z-domain results agree
of three models and the jitter response was evaluated. For with the measured results within the +OS-dB measure-
the timestep simulator, a 0.1 Unit Interval (1 U.I. 1 clock ment error bars. Again, the s-domain H(f)tracks the
period) input jitter magnitude was used as the "small r-domain H(f)for low jitter frequencies, but diverges at
signal" input. Plots of the magnitude of H ( f ) are shown about 1/20th the input data transition rate. The agreement
in Fig. 9. It is seen that the timestep simulator results agree of the timestep simulator, fabricated PLL, and z-domain
with the z-domain model results within kO.3 dB over all H(f ) verifies the accuracy of the discrete-time linear
frequencies. With an input data transition rate of 193 kHz model.
and VCO clock rate of MHz the linear models agree
within f0.3 dB up to about 1/20th of the input transition
rate. For the z-domain model and the timestep simulator, IV. SUMMARY AND CONCLUSIONS
the loop response is periodic with a period of 96.5 kHz, In this paper, two classes of PLL's were described:
whereas the s-domain response continues to roll off at continuous-time and discrete-time PLL's. Classic s-domain
higher frequencies. analysis, although valid for continuous-time PLL's, cannot
result of these simulations, the
z-domain model and timestep simulator were chosen as the always accurately predict the behavior of discrete-time
design tools for determining loop parameters in the actualloops. The z-domain model, presented here, takes into
PLL. account the sampled data nature of the digital phase
Upon receipt of silicon, the individual loop parameters detector and accurately predicts overall loop performance.
were measured for specific device. These parameters The interface between discrete- and continuous-time ele-

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 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL. NO. NOVEMBER

ments is handled using the impulse invariant s-to-z-

domain transformation. In this way, the entire PLL is
analyzed in the discrete-time domain. Measured results
from the DSI phase-locked loop support the z-domain
model.
The modeling philosophy presented in this paper can be
generalized to many systems in which discrete- and oontin-
uous-time elements coexist. One such system, a PLL
switched capacitor loop filter driving a continuous
VCO, is described in Appendix B. In this case, the inter- I
face waveform is staircase in nature; therefore, the step
invariant transformation is appropriate. In general, if a
well-defined interface waveshape exists, an appropriate
transformation can be chosen to convert all s-domain
elements into the z-domain. In this way, a complete linear
model for the mixed continuous-time/discrete-timesystem Fig. 11. PLL response to finite width pulse input.
can be developed.
3) Finally, in the model using the impulse invariant
transformation, it was assumed that the pulse width modu-
APPENDIX A
NETWORK LINEARIZATION APPROXIMATIONS
lated output of the digital phase detector could be approxi-
mated as a series of weighted impulses. The validity of this
In the derivation of the z-domain model for discrete-time approximation can be investigated by analyzing the loop
PLL's presented in this paper, a number of approxima- filter and VCO response to a finite width pulse for a
tions were made to linearize the network. In Gardner simple RC loop filter. In Fig. 11, a simple RC charge
uses the difference equation approach to derive a discrete- pump loop filter is shown. The loop filter is driven with a
time PLL's response to an input phase ramp (frequency current pulse of magnitude I p and duration
step). In linearizing the difference equations, a number of The output of the loop filter from time 0 to T (the time
approximations are also required. In this appendix, each of at which the next reference data edge arrives) is given by
the linearizing assumptions will be discussed. It will be
shown that the assumptions required to derive the z- I
domain model through the impulse invariant transforma- uc(t)=IpR+Lt,
C
tion are the same as the assumptions required to linearize
the difference equations. Therefore, both approaches lead
to the same results, although the impulse invariant ap-
proach significantly reduces the amount of computation
required. The VCO integrates its control voltage to produce an
Linearizing Assumptions output phase shift. Therefore, the total phase shift at time
1) In any linear PLL model, it must be assumed that the T caused by the finite width pulse starting at time 0 is
loop filter and VCO operate in a linear fashion. As stated given by
previously, many practical loop filters and VCO's are well T
modeled as linear elements. A+=K,J uc(t)dt
0
2) In both discrete-time models, it must be assumed
that phase samples occur at constant intervals and that the
loop responds symmetrically to leading and lagging phase
information. This implies that:
K*
a) the phase tracking errors are small, 2( RC T
2c
b) the data pattern is constant,
c) the bit-to-bit data jitter is small, From this equation, one can see that the phase shift is a
d) no significant amount of high frequency energy linear function of pulse area I p - 7 ) if 2 - (RC T )
can propagate directly around the loop, generating For reasonable loop filter components and small tracking
asymmetric behavior for leading and lagging phase errors, this is a very good approximation. For the wide-
errors. band loop used to verify the z-domain model in this paper,
the RC time constant of the loop filter was much
Typically, the finite high frequency response of the VCO larger than the maximum phase tracking error 50 ns).
and of ripple filters built into the loop filter-remove this Therefore, approximating the finite width pulse with a
high frequency energy sufficiently to allow the loop to weighted impulse of area I; introduces negligible error
operate in a linear fashion. in the analysis.

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HElN SCOTT: I-DOMAIN MODEL FOR PLL'S 1399

series of impulses. In other PLL architectures, switched

capacitor loop filters may be used drive a continuous-
time VCO. In these cases, an extension of the modeling
philosophy presented in this paper can be used to develop
a discrete-time linear model for the PLL.
The functional block diagram for such a switched-
capacitor loop filter/continuous-time VCO interface is
shown in fig. 12. The output of loop filter is a staircase
waveform which changes values at intervals of T seconds.
This staircase waveform can be viewed as a superposition
of step functions whose value for the k th time interval is
given by the difference between the output of the SWC
loop filter in the k and (k 1)th intervals. Quantitatively,
if s ( k ) is the output step function in kth interval,
then:
r(k-1)
U,( k U,( k 1) s k
Fig. Switched capacitor loop filter/continuous-time VCO interface.

or
I

Transforming this relationship into the z-domain yields

3
Therefore, the input to the VCO can be modeled as a
Fig. 13. Z-domain model for swc loop filter/VCo interface using
step invariant transformation. summation of step functions s( k ) if the output of the loop
filter u,(k) is passed through a first-differencing block
with transfer characteristic 1 The first-differencing
block, of course, does not exist in the real system, it is only
In the difference equation analysis from the
required in the model in order represent the loop filter
term was dropped from (A13) in order to lin- output as a sum of step functions.
earize the equation. This is equivalent dropping the
The treatment of a continuous-time system being driven
nonlinear term in (1) above. Thus, the difference equa-
by a series of weighted step functions is analogous to the
tion approach also approximates the finite width pulses
treatment of continuous-time network being driven by a
coming from the digital phase detector as a series of
weighted sum of impulses. For a step function input the
weighted impulses.
VCO, it is necessary to use the step invariant transforma-
From the above analysis, it is shown that the linearizing tion model the VCO in the z-domain. A reconstruction
approximations required for the impulse invariant trans- filter or VCO finite frequency response can be handled by
formation method and difference equation method are the
including these s-domain singularities with the basic K , / s
same. Also, for most practical PLL's, the linearizing as-
VCO term and step transforming the entire expression into
sumptions are valid and the loop operates in a linear
the z-domain. The resulting z-domain model for the SWC
fashion for small phase tracking errors.
loop filter/continuous-time VCO interface is shown in
Fig. 13.
APPENDIX B Once the continuous-time elements have been trans-
EXTENSION OF MODELTO SWITCHED-CAPACITOR LOOP formed into the z-domain using the step invariant method,
FILTER/CONTINUOUS TIME VCO INTERFACE the discrete-time analysis of the PLL can proceed com-
The previous sections of this paper have dealt with a pletely in the discrete-time domain.
PLL architecture which consisted of a digital phase detec- REFERENCES
tor which was well modeled directly in the z-domain and a F. Gardner. Phuselock Techni ues. New Yo& Wiley. 1979.
continuous-time loop filter and VCO which were described P. Gray and R. Meyer. Anatsis Design Analog Integrated
by s-domain transfer functions. The modeling technique 131 R Fkst, PNcw York: Wilcy, 1984.
h a s r L m k d Loop. New York:McGraw-Hill, Inc. 1984.
presented addressed the problem of converting the contin- 4 F. Gardner, Charge pump hase lock loops," IEEE Com-
uous-time components of the PLL into the discrete-time vol. COM-28. Nov. 1983.
Op enheim and R. Schafer, Digita! Signal Procossing. Engle-
domain when the loop filter is being driven by a weighted &irk, NJ: Prentice-Hall, 1975.

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 1400 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS,VOL. 35. NO. NOVEMBER

Jerrell P. Heia (S’82-Mi13) received h e B.S.EE. Jeffrey W. received the B.S.E.E.degree

degree from Penn State University, Slate Col- from khigh University, Bethlehem, PA, in 1983
lege, in and the M.S.E.E. degree from and the M.S.E.E from the Massachusetts
Stanford University, Stanford, CA, in Institute of.Technology. Cambridge, in
He joined AT&T Bell Laboratories in as He is currently a Member of the Technical
Mcmbcr of Technical Staff, designing analog Staff at AT&T Bell Laboratories in Reading. PA,
VLSl devices for data communications. In his activities and interests include anal%
he moved Crysial Semiconductor Corpora- MOS circuit design, digital signal processing.
tion, Austin. TX. as Local Area Network IC oversampled data conversion. and high speed
design engineer. He rejoined Bell Laboratories in clock recovery.
and is currently involved in the develop Mr.Scott is a member of Phi Beta Kappa and
meat of T-curier data communications devices, voiceband can- Eta Kappa Nu.
cellers, and phase-locked loops.
Mr. H a n is a member of Eta Kappa Nu and Tau Beta Pi.

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