1

EE 560
MOS TRANSISTOR THEORY
PART 1

Kenneth R. Laker, University of Pennsylvania

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TWO TERMINAL MOS STRUCTURE
VG (GATE VOLTAGE)
GATE
OXIDE
SiO2
SUBSTRATE
tox
p-type doped Si
(NA = 1015 to 1016 cm-3)

VB (SUBSTRATE VOLTAGE)
EQUILIBRIUM: n p = ni2 (ni ≈ 1.45 x 1010 cm-3)
Let SUBSTRATE be uniformy doped @ NA
n i2
np 0 ≈ and pp0 = NA
Kenneth R. Laker, University of Pennsylvania
NA (BULK concentrations)
 3

ENERGY BAND DIAGRAM FOR p - TYPE SUBSTRATE

qΧ = electron affinity of Si

E F − Ei
φF = q
volts

Work Function
q ΦS = q χ + (E c − E F )

kT n i (N >> n ) kT N D
φFp = ln A i
φF n = ln (ND >> ni)
q NA q ni
ni = 1.45 x 10-10 cm-3 @ room temp,
k = 1.38 x 10-23 J/oK,
=> kT/q = 26 mV @ room temp
q = 1.6 x 10 C-19

Kenneth R. Laker, University of Pennsylvania

 4
ENERGY BAND DIAGRAMS FOR
COMPONENTS OF MOS STRUCTURE
METAL (Al) OXIDE SEMICONDUCTOR (Si)
Eo qΦM = qχox= 0.95 eV
qχm = 4.1 eV Ec qχSi = 4.15 eV
EFm
Ec
qΦS band-gap: Eg = 1.1 eV
qΦM -> metal work band-gap: Ei
function (eV) Eg = 8 eV qφFp < 0
qΦS -> EFp
semiconductor work Ev
function (eV)
Ev

Kenneth R. Laker, University of Pennsylvania

 VG = 0 5

Equilibrium

Oxide ΦS > ΦM or EMS < 0 => p-type Si

ΦM > ΦS or EMS > 0 => n-type Si

p-type Si Substrate

VB = 0
Flat-band voltage:
VFB = ΦM - ΦS volts Equilibrium

Built-in potential:
EMS = qVFB eV Ec
qΦM qΦS
Ei
qφs qφF
EFm EFp
φs = surface potential Ev
METAL (Al) OXIDE SEMICONDUCTOR (Si)
Kenneth R. Laker, University of Pennsylvania
 MOS SYSTEM WITH EXTERNAL BIAS 6

Accumulation Region VG < 0

ACCUMULATION Region
EOX EOX Oxide holes
ACCUMULATED on the Si
surface;
p-type Si Substrate electrons
near surface repelled into
Si bulk
VB = 0
VG = 0

Equilibrium
Oxide

p-type Si Substrate

VB = 0
Kenneth R. Laker, University of Pennsylvania
 MOS SYSTEM WITH EXTERNAL BIAS 7

VG > 0 (small)
Depletion Region

EOX EOX Oxide

0 x DEPLETION Region
xd d holes
p-type Si Substrate near surface repelled
into Si bulk, leaving
negatively charged
VB = 0 acceptor ions behind and
region depleted of all
mobile carriers

Ec
Ei
qφF
qVG qφs EFp
xd
EFm Ev
METAL (Al) OXIDE SEMICONDUCTOR (Si)
Kenneth R. Laker, University of Pennsylvania
 MOS SYSTEM BIASED IN DEPLETION REGION 8
VG > 0 (small)

xd = f(φS)
EOX EOX Oxide
0 x DEPLETION Region
xd d
x p-type Si Substrate

VB = 0
Mobile hole charge density in
thin layer parallel to Si surface
Change in surface potential
to displace dQ (Poisson eq)

Depletion Region Charge Density

Kenneth R. Laker, University of Pennsylvania

 MOS SYSTEM WITH EXTERNAL BIAS 9

VG > 0 (large)
Inversion Region
INVERSION Region
electrons
EOX EOX Oxide attracted to Si surface;
xdm holes
repelled deeper into Si bulk
p-type Si Substrate QB0 = Q|x = x = -qNAxdm
d dm

Inversion Condition VB = 0
φs = -φF QB0 -> depletion density charge at
surface inversion (φs = -φF)
2ε Si | 2φF |
x dm = x d φs = − φF = Ec
qN A
Ei
EFp
EFm qVG φs = -φF Ev
METAL (Al) OXIDE SEMICONDUCTOR (Si)
Kenneth R. Laker, University of Pennsylvania
 G G
10
G G G G

D S D S S DS D S D S

B B B B
B B
n-channel enhancement p-channel enhancement
I DS I DS
IDS IDS
-V
-VTp
Tp
VGS
V
0 GS

VGS
V
0 GS
+V
+VTn
Tn
n-channel depletion I DS
G
IDS
I p-channel depletion
I
DS +V
+VTpTp
DS V
VGS
GS
D S 0

B
VGS
V
-V
-VTn 0 GS
Tn Kenneth R. Laker, University of Pennsylvania
 B S G D 11
W

L
oxide

n+ n+

conducting
channel
substrate depletion layer
or bulk B
p

N-CHANNEL ENHANCEMENT-TYPE MOSFET

nMOS Layout

polysilicon gate
active area
metal
contact area
W
L Kenneth R. Laker, University of Pennsylvania
 B S G D D G S B 12

p+ p+ n+ n+
n-well

p -substrate

VGS < VTn CUT-OFF REGION

DEPLETION REGION
0 < VGS < VTn VGS VDS

G oxide
B (G2) S D
CGC
C
GC
nn++ CBC nn++
CBC
depletion region
depletion region

substrate
substrate
p
or or
bulk B B
bulk
p
Kenneth R. Laker, University of Pennsylvania
 VGS > VTn INVERSION REGION 13

VGS VDS

G oxide
B (G2 ) S D
C
CGCGC
nn++ CBC nn++
CBC
conducting
channel
substrate
substrate depletion region
or
or
or
orbulk
bulkBB inversion
inversionregion
region
pp

Underneath Gate Ec
VG = VTn
Ei
φF
2φF EFp
EFm qVTn -φF
Ev
METAL (Al) OXIDE SEMICONDUCTOR (Si)
Kenneth R. Laker, University of Pennsylvania
 MOS Capacitance C = WLC , C = ε ox 14
[tox -> TOX in SPICE]
GC ox ox
t ox
[Cox -> COX in SPICE]
tox = 50 nm, εox = 0.34 pF/cm => Cox = 6.8 x 10-8 F/cm2
W x L = 50 µm x 50 µm => CGC = 170 fF
Depletion Capacitance C BC = WLC j , C j = εSi
xd
[NSUB -> NSUB in SPICE]
NSUB (p - substrate)
kT n i
ln φFp =
q NA
NA = 3 x 1017 cm-3, ni = 1.45 x 1010 cm-3 => φF = -0.438 V
(recall that at room temp or 27oC kT/q = 26 mV)
VSB = 0 V, εSi = 1.06 pF/cm, q = 1.6 x 10-19 C, NA, φF => xd = 6.22 µm
εSi, xd => Cj = 0.17 x 10-8 F/cm2
W x L = 50 µm x 50 µm => CBC = 42.5 fF
Kenneth R. Laker, University of Pennsylvania
 15

Threshold Voltage for MOS Transistors

n-channel enhancement
[VT0 -> VT0 in SPICE]
For VSB = 0, the threshold voltage is denoted as VT0 or VT0n,p

QB 0 Q ox
VT 0 = ΦGC − 2φF − −
C ox C ox
Threshold Voltage factors: (+ for nMOS and - for pMOS)
[2φ F = PHI in SPICE]
-> Gate conductor material;
-> Gate oxide material & C/cm2 [N A = NSUB in SPICE]
thickness;
QB0 -> depletion charge density at surface inversion (φs = -φF
-> Substrate doping;
-> Impurities in Si-oxide
interface;
ΦGC = φF(substrate) -φM metal gate
ΦGC = φF(substrate) -φF (gate) polysilicon gate
-> Source-bulk voltage VSB;
-> Temperature. [Qox = qNSS in SPICE]
Qox -> charge density at gate Si-oxide interface due to
impurities and lattice imperfections at the interface.
Kenneth R. Laker, University of Pennsylvania
 16
Threshold Voltage for MOS Transistors
n-channel enhancement
For : the threshold voltage is denoted as VT or VTn,p

QB Q ox
VT = ΦGC − 2φF − −
C ox C ox
Q B 0 Q ox Q B − Q B0
= ΦGC − 2φF − − −
C ox C ox C ox
where VT0

(γ = Body-effect coefficient) [γ = GAMMA in SPICE]

+

Kenneth R. Laker, University of Pennsylvania

 17

Threshold Voltage for MOS Transistors

n-channel -> p-channel

****BE CAREFULL*** WITH SIGNS

• φF is negative in nMOS, positive in pMOS
• QB0, QB are negtive in nMOS, positive in pMOS
• γ is positive in nMOS, negative in pMOS
• VSB is negative in nMOS, positive in pMOS
C BC
NOTE: γ ∝
C GC

Kenneth R. Laker, University of Pennsylvania

 18
Threshold Voltage for MOS Transistors
VT0
3V nMOS NBULK = NA
VT0n

14 16 NABULK
N
10 10
pMOS
VT0p NBULK = ND
-3V

VT
16
3V (nMOS 10 /cm 3 ) VTn

(nMOS 3 x10 /cm 3 )

14 VTn
0
V
VBSSB
3 6
16
(pMOS 10 /cm3 )

-3V
VTp
Kenneth R. Laker, University of Pennsylvania
 19
EXAMPLE 3.2 Calculate the threshold voltage VT0 at VBS = 0, for
a polysilicon gate n-channel MOS transistor with the following
parameters:
substrate doping density NA = 1016 cm-3,
polysilicon doping density ND = 2 x 1020 cm-3,
gate oxide thickness tox = 500 Angstroms,
oxide-interface fixed charge density Nox = 4 x 1010 cm-2,
dielectric permativities: εox = 0.34 x 10-12Fcm-1, εSi = 1.06 x 10-12Fcm-1
QB 0 Q ox
VT 0 = ΦGC − 2φF(sub) − −
C ox C ox
φF(sub), ΦGC: ΦGC = φF(sub) − φF(gate)
kT n i  1.45x1010 
φF(sub) = ln = 0.026Vln  = −0.35V
q NA  10 16

kT N D  2 x10 20 
φF( gate) = ln = 0.026 Vln  10  = 0.60 V
q ni  1.45x10 
ΦGC = φF(sub) − φF(gate) = -0.35 V - 0.60 V = -0.95 V
Kenneth R. Laker, University of Pennsylvania
 QB 0 Q ox 20
EXAMPLE 3-2 CONT. VT 0 = ΦGC − 2φF(sub) − −
C ox C ox
QB0:

= − 2(1.6x10 −19 C)(1016 cm −3 )(1.06 x10 −12 Fcm −1 ) | 2 x 0.35V|

F = C/V
-8 2
= - 4.87 x 10 C/cm
Cox: εox = 0.34 x 10-12Fcm-1,
−1 εSi = 1.06 x 10 Fcm
-12 -1
−12
ε ox 0.34 x10 Fcm −8
C ox = = = 6.8x10 F/cm 2

t ox 500 x10 −8 cm

Qox:
Q ox = qNox = (1.6x10 −19 C)(4 x1010 cm −2 ) = 6.4 x10 −9 C/cm 2

Q B 0 −4.87x10 C/cm −8 2 Q ox 6.4 x10 −9 C/cm 2

= = -−0.716
0.72 VV = −8 2 = 0.09
0.094VV
−8 2 Cox 6.8x10 F/cm
C ox 6.8x10 F/cm
VT 0 = −0.95V− (−0.70 V) − (−0.72 V) − (0.09V) = 0.38V
Kenneth R. Laker, University of Pennsylvania
 EXAMPLE 3.3 Consider the n-channel MOS transistor with the 21
following process parameters:
substrate doping density NA = 1016 cm-3,
polysilicon doping density ND = 2 x 1020 cm-3,
gate oxide thickness tox = 500 Angstroms,
oxide-interface fixed charge density Nox = 4 x 1010 cm-2,
dielectric permativities: εox = 0.34 x 10-12Fcm-1, εSi = 1.06 x 10-12Fcm-1.
In digital circuit design, the condition VSB = 0 can not always be
quaranteed for all transistors. Plot the threshold voltage VT as a
function of VSB.

γ - Body-effect coefficient: F = C/V

2 qN A e Si 2(1.6 x10 −19 C)(1016 cm −3 )(1.06 x10 −12 Fcm −1 )
γ= =
C ox 6.8x10−8 F/cm 2
5.824 x10 −8 C/V −1/ 2 cm 2
= = 0.85V1/ 2

6.8x10−8 C/Vcm 2
Kenneth R. Laker, University of Pennsylvania
 22
EXAMPLE 3-3 CONT.

where
VT 0 = 0.38V (from EX 3-2)
γ = 0.85V1 /2

VT(Volts)
1.60
1.40
1.20
1.00
0.80
0.60
0.40
0.20 VSB(Volts)
-1 0 1 2 3 4 5 6
Kenneth R. Laker, University of Pennsylvania