class transaction;

rand bit w_en,r_en;

rand bit [addr_width-1:0] r_addr;
rand bit [data_width-1:0] w_data;
rand bit [addr_width-1:0] w_addr;
bit [data_width-1:0] r_data;

constraint wr_rd_c{w_en!=r_en};

end transaction
///////////////////////////////////////////////////////////////////generator///////
/////////////////////////////////////

class generator;

rand transaction trans;

mailbox gen2driv;
int repeat_count;
event ended;

function new(gen2driv, event ended);

this.gen2driv=gen2driv;
this.ended=ended;
endfunction

task main();
repeat (repeat_count)
begin
tans =new();
if(!trans.randomize())
$fatal("transaction failed");
gen2driv.put(trans);
end
-> ended;

endtask
end class

////////////////////////////////////////////////////////////interface//////////////
//////////////////////////////////////

interface intf (input clk,rst);

logic w_en,r_en;
logic [addr_width-1:0] r_addr;
logic [data_width-1:0] w_data;
logic [addr_width-1:0] w_addr;
logic [data_width-1:0] r_data;

clocking driver_cb @(posedge clk);

default input #1 output #1;
output r_addr;
output w_addr;
output w_en;
output r_en;
output w_data;
 input r_data;
endclocking

modport DRIVER (clocking driver_cb,input clk,rst);

endinterface

/////////////////////////////////////////////////////driver////////////////////////
///////////////////////////////////////

class driver;

int no_transactions;
mailbox gen2driv;
virtual interface intf vif;

function new(mailbox gen2driv, virtual interface intf vif);

this.gen2driv=gen2driv;
this.vif=vif;
endfunction

task rst;
wait(vif.rst);
$display("--------- [DRIVER] Reset Started ---------");
vif.w_en <= 0;
vif.r_en <= 0;
vif.w_addr <= 0;
vif.w_data <= 0;
vif.r_addr <= 0;
//`DRIV_IF.r_data <= 0;
wait(!vif.rst);
$display("--------- [DRIVER] Reset Ended ---------");
endtask

task main();
forever begin
transactin trans;
vif.r_en<=0;
vif.w_en<=0;
gen2driv.get(trans);
$display("------- [DRIVER-TRANSFER: %0d] -------",no_transactions);
@(posedge vif.clk);

vif.w_addr<=trans.w_addr;
vif.r_addr<=trans.r_addr;

if(trans.w_en)
begin
vif.w_en <= trans.en;
vif.w_addr <= trans.w_data;
$display("w_addr= %b, w_data=%b",trans.w_addr,trans.w_data);
@(posedge vif.clk);
end

if(trans.r_en)
begin
vif.r_en <= trans.r_en;
vif.r_data <= trans.r_addr;
 $display("r_addr= %b, r_data=%b",trans.r_addr,trans.r_data);
@(posedge vif.clk);
end
no_transactions++;
end
endtask
endclass

///////////////////////////////////////////environment/////////////////////////////
////////////////////

`include "generator.sv"
`include "driver.sv"
`include "transaction.sv"
class environment;

generator gen;
driver driv;
mailbox gen2driv;

event gen_ended;

virtual interface intf vif;

function new(virtual interface intf vif);

this.vif=vif;
gen2driv=new();
gen=new(gen2drive, gen_ended);
drive=new(gen2drive, vif)
endfunction

task pre_test();
driv.rst();
endtask

task test();
fork
gen.main();
driv.main();
join_any
endtask

task post_test();
begin
wait(gen_ended.triggered);
wait(gen.repeat_count == driv.no_transactions);
end
endtask

task run();
begin
pre_test();
test();
post_test;
$finish();
end
endtask
 endclass

/////////////////////////////////////////programtest///////////////////////////////
///////////
`include "environment.sv"
program test(intf kf);
environment env;
initial begin
env=new(kf);
env.gen.repeat_count=5;
env.run();
end
endprogram

////////////////////////////////////////top////////////////////////////////////////
//////////

`include "interface.sv"
`include "test.sv"

module top();
bit clk,rst;

always #5 clk = ~clk;

//reset Generation
initial begin
rst = 1;
#5 rst =0;
end

//creatinng instance of interface, inorder to connect DUT and testcase

intf kf(clk,reset);

//Testcase instance, interface handle is passed to test as an argument

test t1(kf);

//DUT instance, interface signals are connected to the DUT ports

dpram DUT(
.clk(kf.clk),
.rst(kf.rst),
.r_addr(kf.r_addr),
.w_addr(kf.w_addr),
.w_en(kf.w_en),
.r_en(kf.r_en),
.w_data(kf.w_data),
.r_data(ff.r_data)
);

//enabling the wave dump

initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule