Abstract of Research for the Conference

Hassan bin Qasim 2019-MS-EE-38

Abstract:
In this abstract, we have design three devices, a homo p-n, a hetero p-n, and, a Schottky
junction. We will use CdTe semiconductor materials to implement these devices. CdTe
devices have reached efficiencies of 22.1% due to continuing improvements in bulk material
properties, including minority carrier lifetime. Device modelling has helped guide these
device improvements by quantifying the impacts of material properties and different device
designs on device performance. One of the barriers to truly predictive device modelling is the
interdependence of these material properties. For example, interfaces become more critical as
bulk properties, particularly hole density and carrier lifetime, increase. We present device‐
modelling analyses that describe the effects of recombination at the interfaces and grain
boundaries as lifetime and doping of the CdTe layer change. The doping and lifetime should
be priorities for maximizing open‐circuit voltage (Voc) and efficiency improvements.
However, interface and grain boundary (GB) recombination become bottlenecks to device
performance at increased lifetime and doping levels. This work quantifies and discusses these
emerging challenges for next‐generation CdTe device efficiency. In our paper we are
following a research paper and doing simulation of CdTe solar cell on AFROS-HET software
and then we will compare our results with paper result